linux/drivers/net/wireless/ath/ath9k/xmit.c
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   1/*
   2 * Copyright (c) 2008-2011 Atheros Communications Inc.
   3 *
   4 * Permission to use, copy, modify, and/or distribute this software for any
   5 * purpose with or without fee is hereby granted, provided that the above
   6 * copyright notice and this permission notice appear in all copies.
   7 *
   8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15 */
  16
  17#include <linux/dma-mapping.h>
  18#include "ath9k.h"
  19#include "ar9003_mac.h"
  20
  21#define BITS_PER_BYTE           8
  22#define OFDM_PLCP_BITS          22
  23#define HT_RC_2_STREAMS(_rc)    ((((_rc) & 0x78) >> 3) + 1)
  24#define L_STF                   8
  25#define L_LTF                   8
  26#define L_SIG                   4
  27#define HT_SIG                  8
  28#define HT_STF                  4
  29#define HT_LTF(_ns)             (4 * (_ns))
  30#define SYMBOL_TIME(_ns)        ((_ns) << 2) /* ns * 4 us */
  31#define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5)  /* ns * 3.6 us */
  32#define TIME_SYMBOLS(t)         ((t) >> 2)
  33#define TIME_SYMBOLS_HALFGI(t)  (((t) * 5 - 4) / 18)
  34#define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
  35#define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
  36
  37
  38static u16 bits_per_symbol[][2] = {
  39        /* 20MHz 40MHz */
  40        {    26,   54 },     /*  0: BPSK */
  41        {    52,  108 },     /*  1: QPSK 1/2 */
  42        {    78,  162 },     /*  2: QPSK 3/4 */
  43        {   104,  216 },     /*  3: 16-QAM 1/2 */
  44        {   156,  324 },     /*  4: 16-QAM 3/4 */
  45        {   208,  432 },     /*  5: 64-QAM 2/3 */
  46        {   234,  486 },     /*  6: 64-QAM 3/4 */
  47        {   260,  540 },     /*  7: 64-QAM 5/6 */
  48};
  49
  50static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
  51                               struct ath_atx_tid *tid, struct sk_buff *skb);
  52static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
  53                            int tx_flags, struct ath_txq *txq,
  54                            struct ieee80211_sta *sta);
  55static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
  56                                struct ath_txq *txq, struct list_head *bf_q,
  57                                struct ieee80211_sta *sta,
  58                                struct ath_tx_status *ts, int txok);
  59static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
  60                             struct list_head *head, bool internal);
  61static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
  62                             struct ath_tx_status *ts, int nframes, int nbad,
  63                             int txok);
  64static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
  65                              int seqno);
  66static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
  67                                           struct ath_txq *txq,
  68                                           struct ath_atx_tid *tid,
  69                                           struct sk_buff *skb);
  70static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
  71                          struct ath_tx_control *txctl);
  72
  73enum {
  74        MCS_HT20,
  75        MCS_HT20_SGI,
  76        MCS_HT40,
  77        MCS_HT40_SGI,
  78};
  79
  80/*********************/
  81/* Aggregation logic */
  82/*********************/
  83
  84static void ath_tx_status(struct ieee80211_hw *hw, struct sk_buff *skb)
  85{
  86        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  87        struct ieee80211_sta *sta = info->status.status_driver_data[0];
  88
  89        if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) {
  90                ieee80211_tx_status(hw, skb);
  91                return;
  92        }
  93
  94        if (sta)
  95                ieee80211_tx_status_noskb(hw, sta, info);
  96
  97        dev_kfree_skb(skb);
  98}
  99
 100void ath_txq_unlock_complete(struct ath_softc *sc, struct ath_txq *txq)
 101        __releases(&txq->axq_lock)
 102{
 103        struct ieee80211_hw *hw = sc->hw;
 104        struct sk_buff_head q;
 105        struct sk_buff *skb;
 106
 107        __skb_queue_head_init(&q);
 108        skb_queue_splice_init(&txq->complete_q, &q);
 109        spin_unlock_bh(&txq->axq_lock);
 110
 111        while ((skb = __skb_dequeue(&q)))
 112                ath_tx_status(hw, skb);
 113}
 114
 115void __ath_tx_queue_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
 116{
 117        struct ath_vif *avp = (struct ath_vif *) tid->an->vif->drv_priv;
 118        struct ath_chanctx *ctx = avp->chanctx;
 119        struct ath_acq *acq;
 120        struct list_head *tid_list;
 121        u8 acno = TID_TO_WME_AC(tid->tidno);
 122
 123        if (!ctx || !list_empty(&tid->list))
 124                return;
 125
 126
 127        acq = &ctx->acq[acno];
 128        if ((sc->airtime_flags & AIRTIME_USE_NEW_QUEUES) &&
 129            tid->an->airtime_deficit[acno] > 0)
 130                tid_list = &acq->acq_new;
 131        else
 132                tid_list = &acq->acq_old;
 133
 134        list_add_tail(&tid->list, tid_list);
 135}
 136
 137void ath_tx_queue_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
 138{
 139        struct ath_vif *avp = (struct ath_vif *) tid->an->vif->drv_priv;
 140        struct ath_chanctx *ctx = avp->chanctx;
 141        struct ath_acq *acq;
 142
 143        if (!ctx || !list_empty(&tid->list))
 144                return;
 145
 146        acq = &ctx->acq[TID_TO_WME_AC(tid->tidno)];
 147        spin_lock_bh(&acq->lock);
 148        __ath_tx_queue_tid(sc, tid);
 149        spin_unlock_bh(&acq->lock);
 150}
 151
 152
 153void ath9k_wake_tx_queue(struct ieee80211_hw *hw, struct ieee80211_txq *queue)
 154{
 155        struct ath_softc *sc = hw->priv;
 156        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 157        struct ath_atx_tid *tid = (struct ath_atx_tid *) queue->drv_priv;
 158        struct ath_txq *txq = tid->txq;
 159
 160        ath_dbg(common, QUEUE, "Waking TX queue: %pM (%d)\n",
 161                queue->sta ? queue->sta->addr : queue->vif->addr,
 162                tid->tidno);
 163
 164        ath_txq_lock(sc, txq);
 165
 166        tid->has_queued = true;
 167        ath_tx_queue_tid(sc, tid);
 168        ath_txq_schedule(sc, txq);
 169
 170        ath_txq_unlock(sc, txq);
 171}
 172
 173static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
 174{
 175        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
 176        BUILD_BUG_ON(sizeof(struct ath_frame_info) >
 177                     sizeof(tx_info->rate_driver_data));
 178        return (struct ath_frame_info *) &tx_info->rate_driver_data[0];
 179}
 180
 181static void ath_send_bar(struct ath_atx_tid *tid, u16 seqno)
 182{
 183        if (!tid->an->sta)
 184                return;
 185
 186        ieee80211_send_bar(tid->an->vif, tid->an->sta->addr, tid->tidno,
 187                           seqno << IEEE80211_SEQ_SEQ_SHIFT);
 188}
 189
 190static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
 191                          struct ath_buf *bf)
 192{
 193        ieee80211_get_tx_rates(vif, sta, bf->bf_mpdu, bf->rates,
 194                               ARRAY_SIZE(bf->rates));
 195}
 196
 197static void ath_txq_skb_done(struct ath_softc *sc, struct ath_txq *txq,
 198                             struct sk_buff *skb)
 199{
 200        struct ath_frame_info *fi = get_frame_info(skb);
 201        int q = fi->txq;
 202
 203        if (q < 0)
 204                return;
 205
 206        txq = sc->tx.txq_map[q];
 207        if (WARN_ON(--txq->pending_frames < 0))
 208                txq->pending_frames = 0;
 209
 210}
 211
 212static struct ath_atx_tid *
 213ath_get_skb_tid(struct ath_softc *sc, struct ath_node *an, struct sk_buff *skb)
 214{
 215        u8 tidno = skb->priority & IEEE80211_QOS_CTL_TID_MASK;
 216        return ATH_AN_2_TID(an, tidno);
 217}
 218
 219static struct sk_buff *
 220ath_tid_pull(struct ath_atx_tid *tid)
 221{
 222        struct ieee80211_txq *txq = container_of((void*)tid, struct ieee80211_txq, drv_priv);
 223        struct ath_softc *sc = tid->an->sc;
 224        struct ieee80211_hw *hw = sc->hw;
 225        struct ath_tx_control txctl = {
 226                .txq = tid->txq,
 227                .sta = tid->an->sta,
 228        };
 229        struct sk_buff *skb;
 230        struct ath_frame_info *fi;
 231        int q;
 232
 233        if (!tid->has_queued)
 234                return NULL;
 235
 236        skb = ieee80211_tx_dequeue(hw, txq);
 237        if (!skb) {
 238                tid->has_queued = false;
 239                return NULL;
 240        }
 241
 242        if (ath_tx_prepare(hw, skb, &txctl)) {
 243                ieee80211_free_txskb(hw, skb);
 244                return NULL;
 245        }
 246
 247        q = skb_get_queue_mapping(skb);
 248        if (tid->txq == sc->tx.txq_map[q]) {
 249                fi = get_frame_info(skb);
 250                fi->txq = q;
 251                ++tid->txq->pending_frames;
 252        }
 253
 254        return skb;
 255 }
 256
 257
 258static bool ath_tid_has_buffered(struct ath_atx_tid *tid)
 259{
 260        return !skb_queue_empty(&tid->retry_q) || tid->has_queued;
 261}
 262
 263static struct sk_buff *ath_tid_dequeue(struct ath_atx_tid *tid)
 264{
 265        struct sk_buff *skb;
 266
 267        skb = __skb_dequeue(&tid->retry_q);
 268        if (!skb)
 269                skb = ath_tid_pull(tid);
 270
 271        return skb;
 272}
 273
 274static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
 275{
 276        struct ath_txq *txq = tid->txq;
 277        struct sk_buff *skb;
 278        struct ath_buf *bf;
 279        struct list_head bf_head;
 280        struct ath_tx_status ts;
 281        struct ath_frame_info *fi;
 282        bool sendbar = false;
 283
 284        INIT_LIST_HEAD(&bf_head);
 285
 286        memset(&ts, 0, sizeof(ts));
 287
 288        while ((skb = __skb_dequeue(&tid->retry_q))) {
 289                fi = get_frame_info(skb);
 290                bf = fi->bf;
 291                if (!bf) {
 292                        ath_txq_skb_done(sc, txq, skb);
 293                        ieee80211_free_txskb(sc->hw, skb);
 294                        continue;
 295                }
 296
 297                if (fi->baw_tracked) {
 298                        ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
 299                        sendbar = true;
 300                }
 301
 302                list_add_tail(&bf->list, &bf_head);
 303                ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
 304        }
 305
 306        if (sendbar) {
 307                ath_txq_unlock(sc, txq);
 308                ath_send_bar(tid, tid->seq_start);
 309                ath_txq_lock(sc, txq);
 310        }
 311}
 312
 313static void ath_tx_update_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
 314                              int seqno)
 315{
 316        int index, cindex;
 317
 318        index  = ATH_BA_INDEX(tid->seq_start, seqno);
 319        cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
 320
 321        __clear_bit(cindex, tid->tx_buf);
 322
 323        while (tid->baw_head != tid->baw_tail && !test_bit(tid->baw_head, tid->tx_buf)) {
 324                INCR(tid->seq_start, IEEE80211_SEQ_MAX);
 325                INCR(tid->baw_head, ATH_TID_MAX_BUFS);
 326                if (tid->bar_index >= 0)
 327                        tid->bar_index--;
 328        }
 329}
 330
 331static void ath_tx_addto_baw(struct ath_softc *sc, struct ath_atx_tid *tid,
 332                             struct ath_buf *bf)
 333{
 334        struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
 335        u16 seqno = bf->bf_state.seqno;
 336        int index, cindex;
 337
 338        index  = ATH_BA_INDEX(tid->seq_start, seqno);
 339        cindex = (tid->baw_head + index) & (ATH_TID_MAX_BUFS - 1);
 340        __set_bit(cindex, tid->tx_buf);
 341        fi->baw_tracked = 1;
 342
 343        if (index >= ((tid->baw_tail - tid->baw_head) &
 344                (ATH_TID_MAX_BUFS - 1))) {
 345                tid->baw_tail = cindex;
 346                INCR(tid->baw_tail, ATH_TID_MAX_BUFS);
 347        }
 348}
 349
 350static void ath_tid_drain(struct ath_softc *sc, struct ath_txq *txq,
 351                          struct ath_atx_tid *tid)
 352
 353{
 354        struct sk_buff *skb;
 355        struct ath_buf *bf;
 356        struct list_head bf_head;
 357        struct ath_tx_status ts;
 358        struct ath_frame_info *fi;
 359
 360        memset(&ts, 0, sizeof(ts));
 361        INIT_LIST_HEAD(&bf_head);
 362
 363        while ((skb = ath_tid_dequeue(tid))) {
 364                fi = get_frame_info(skb);
 365                bf = fi->bf;
 366
 367                if (!bf) {
 368                        ath_tx_complete(sc, skb, ATH_TX_ERROR, txq, NULL);
 369                        continue;
 370                }
 371
 372                list_add_tail(&bf->list, &bf_head);
 373                ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
 374        }
 375}
 376
 377static void ath_tx_set_retry(struct ath_softc *sc, struct ath_txq *txq,
 378                             struct sk_buff *skb, int count)
 379{
 380        struct ath_frame_info *fi = get_frame_info(skb);
 381        struct ath_buf *bf = fi->bf;
 382        struct ieee80211_hdr *hdr;
 383        int prev = fi->retries;
 384
 385        TX_STAT_INC(txq->axq_qnum, a_retries);
 386        fi->retries += count;
 387
 388        if (prev > 0)
 389                return;
 390
 391        hdr = (struct ieee80211_hdr *)skb->data;
 392        hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_RETRY);
 393        dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
 394                sizeof(*hdr), DMA_TO_DEVICE);
 395}
 396
 397static struct ath_buf *ath_tx_get_buffer(struct ath_softc *sc)
 398{
 399        struct ath_buf *bf = NULL;
 400
 401        spin_lock_bh(&sc->tx.txbuflock);
 402
 403        if (unlikely(list_empty(&sc->tx.txbuf))) {
 404                spin_unlock_bh(&sc->tx.txbuflock);
 405                return NULL;
 406        }
 407
 408        bf = list_first_entry(&sc->tx.txbuf, struct ath_buf, list);
 409        list_del(&bf->list);
 410
 411        spin_unlock_bh(&sc->tx.txbuflock);
 412
 413        return bf;
 414}
 415
 416static void ath_tx_return_buffer(struct ath_softc *sc, struct ath_buf *bf)
 417{
 418        spin_lock_bh(&sc->tx.txbuflock);
 419        list_add_tail(&bf->list, &sc->tx.txbuf);
 420        spin_unlock_bh(&sc->tx.txbuflock);
 421}
 422
 423static struct ath_buf* ath_clone_txbuf(struct ath_softc *sc, struct ath_buf *bf)
 424{
 425        struct ath_buf *tbf;
 426
 427        tbf = ath_tx_get_buffer(sc);
 428        if (WARN_ON(!tbf))
 429                return NULL;
 430
 431        ATH_TXBUF_RESET(tbf);
 432
 433        tbf->bf_mpdu = bf->bf_mpdu;
 434        tbf->bf_buf_addr = bf->bf_buf_addr;
 435        memcpy(tbf->bf_desc, bf->bf_desc, sc->sc_ah->caps.tx_desc_len);
 436        tbf->bf_state = bf->bf_state;
 437        tbf->bf_state.stale = false;
 438
 439        return tbf;
 440}
 441
 442static void ath_tx_count_frames(struct ath_softc *sc, struct ath_buf *bf,
 443                                struct ath_tx_status *ts, int txok,
 444                                int *nframes, int *nbad)
 445{
 446        struct ath_frame_info *fi;
 447        u16 seq_st = 0;
 448        u32 ba[WME_BA_BMP_SIZE >> 5];
 449        int ba_index;
 450        int isaggr = 0;
 451
 452        *nbad = 0;
 453        *nframes = 0;
 454
 455        isaggr = bf_isaggr(bf);
 456        if (isaggr) {
 457                seq_st = ts->ts_seqnum;
 458                memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
 459        }
 460
 461        while (bf) {
 462                fi = get_frame_info(bf->bf_mpdu);
 463                ba_index = ATH_BA_INDEX(seq_st, bf->bf_state.seqno);
 464
 465                (*nframes)++;
 466                if (!txok || (isaggr && !ATH_BA_ISSET(ba, ba_index)))
 467                        (*nbad)++;
 468
 469                bf = bf->bf_next;
 470        }
 471}
 472
 473
 474static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
 475                                 struct ath_buf *bf, struct list_head *bf_q,
 476                                 struct ieee80211_sta *sta,
 477                                 struct ath_atx_tid *tid,
 478                                 struct ath_tx_status *ts, int txok)
 479{
 480        struct ath_node *an = NULL;
 481        struct sk_buff *skb;
 482        struct ieee80211_hdr *hdr;
 483        struct ieee80211_tx_info *tx_info;
 484        struct ath_buf *bf_next, *bf_last = bf->bf_lastbf;
 485        struct list_head bf_head;
 486        struct sk_buff_head bf_pending;
 487        u16 seq_st = 0, acked_cnt = 0, txfail_cnt = 0, seq_first;
 488        u32 ba[WME_BA_BMP_SIZE >> 5];
 489        int isaggr, txfail, txpending, sendbar = 0, needreset = 0, nbad = 0;
 490        bool rc_update = true, isba;
 491        struct ieee80211_tx_rate rates[4];
 492        struct ath_frame_info *fi;
 493        int nframes;
 494        bool flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
 495        int i, retries;
 496        int bar_index = -1;
 497
 498        skb = bf->bf_mpdu;
 499        hdr = (struct ieee80211_hdr *)skb->data;
 500
 501        tx_info = IEEE80211_SKB_CB(skb);
 502
 503        memcpy(rates, bf->rates, sizeof(rates));
 504
 505        retries = ts->ts_longretry + 1;
 506        for (i = 0; i < ts->ts_rateindex; i++)
 507                retries += rates[i].count;
 508
 509        if (!sta) {
 510                INIT_LIST_HEAD(&bf_head);
 511                while (bf) {
 512                        bf_next = bf->bf_next;
 513
 514                        if (!bf->bf_state.stale || bf_next != NULL)
 515                                list_move_tail(&bf->list, &bf_head);
 516
 517                        ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, ts, 0);
 518
 519                        bf = bf_next;
 520                }
 521                return;
 522        }
 523
 524        an = (struct ath_node *)sta->drv_priv;
 525        seq_first = tid->seq_start;
 526        isba = ts->ts_flags & ATH9K_TX_BA;
 527
 528        /*
 529         * The hardware occasionally sends a tx status for the wrong TID.
 530         * In this case, the BA status cannot be considered valid and all
 531         * subframes need to be retransmitted
 532         *
 533         * Only BlockAcks have a TID and therefore normal Acks cannot be
 534         * checked
 535         */
 536        if (isba && tid->tidno != ts->tid)
 537                txok = false;
 538
 539        isaggr = bf_isaggr(bf);
 540        memset(ba, 0, WME_BA_BMP_SIZE >> 3);
 541
 542        if (isaggr && txok) {
 543                if (ts->ts_flags & ATH9K_TX_BA) {
 544                        seq_st = ts->ts_seqnum;
 545                        memcpy(ba, &ts->ba_low, WME_BA_BMP_SIZE >> 3);
 546                } else {
 547                        /*
 548                         * AR5416 can become deaf/mute when BA
 549                         * issue happens. Chip needs to be reset.
 550                         * But AP code may have sychronization issues
 551                         * when perform internal reset in this routine.
 552                         * Only enable reset in STA mode for now.
 553                         */
 554                        if (sc->sc_ah->opmode == NL80211_IFTYPE_STATION)
 555                                needreset = 1;
 556                }
 557        }
 558
 559        __skb_queue_head_init(&bf_pending);
 560
 561        ath_tx_count_frames(sc, bf, ts, txok, &nframes, &nbad);
 562        while (bf) {
 563                u16 seqno = bf->bf_state.seqno;
 564
 565                txfail = txpending = sendbar = 0;
 566                bf_next = bf->bf_next;
 567
 568                skb = bf->bf_mpdu;
 569                tx_info = IEEE80211_SKB_CB(skb);
 570                fi = get_frame_info(skb);
 571
 572                if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno) ||
 573                    !tid->active) {
 574                        /*
 575                         * Outside of the current BlockAck window,
 576                         * maybe part of a previous session
 577                         */
 578                        txfail = 1;
 579                } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
 580                        /* transmit completion, subframe is
 581                         * acked by block ack */
 582                        acked_cnt++;
 583                } else if (!isaggr && txok) {
 584                        /* transmit completion */
 585                        acked_cnt++;
 586                } else if (flush) {
 587                        txpending = 1;
 588                } else if (fi->retries < ATH_MAX_SW_RETRIES) {
 589                        if (txok || !an->sleeping)
 590                                ath_tx_set_retry(sc, txq, bf->bf_mpdu,
 591                                                 retries);
 592
 593                        txpending = 1;
 594                } else {
 595                        txfail = 1;
 596                        txfail_cnt++;
 597                        bar_index = max_t(int, bar_index,
 598                                ATH_BA_INDEX(seq_first, seqno));
 599                }
 600
 601                /*
 602                 * Make sure the last desc is reclaimed if it
 603                 * not a holding desc.
 604                 */
 605                INIT_LIST_HEAD(&bf_head);
 606                if (bf_next != NULL || !bf_last->bf_state.stale)
 607                        list_move_tail(&bf->list, &bf_head);
 608
 609                if (!txpending) {
 610                        /*
 611                         * complete the acked-ones/xretried ones; update
 612                         * block-ack window
 613                         */
 614                        ath_tx_update_baw(sc, tid, seqno);
 615
 616                        if (rc_update && (acked_cnt == 1 || txfail_cnt == 1)) {
 617                                memcpy(tx_info->control.rates, rates, sizeof(rates));
 618                                ath_tx_rc_status(sc, bf, ts, nframes, nbad, txok);
 619                                rc_update = false;
 620                                if (bf == bf->bf_lastbf)
 621                                        ath_dynack_sample_tx_ts(sc->sc_ah,
 622                                                                bf->bf_mpdu,
 623                                                                ts);
 624                        }
 625
 626                        ath_tx_complete_buf(sc, bf, txq, &bf_head, sta, ts,
 627                                !txfail);
 628                } else {
 629                        if (tx_info->flags & IEEE80211_TX_STATUS_EOSP) {
 630                                tx_info->flags &= ~IEEE80211_TX_STATUS_EOSP;
 631                                ieee80211_sta_eosp(sta);
 632                        }
 633                        /* retry the un-acked ones */
 634                        if (bf->bf_next == NULL && bf_last->bf_state.stale) {
 635                                struct ath_buf *tbf;
 636
 637                                tbf = ath_clone_txbuf(sc, bf_last);
 638                                /*
 639                                 * Update tx baw and complete the
 640                                 * frame with failed status if we
 641                                 * run out of tx buf.
 642                                 */
 643                                if (!tbf) {
 644                                        ath_tx_update_baw(sc, tid, seqno);
 645
 646                                        ath_tx_complete_buf(sc, bf, txq,
 647                                                            &bf_head, NULL, ts,
 648                                                            0);
 649                                        bar_index = max_t(int, bar_index,
 650                                                ATH_BA_INDEX(seq_first, seqno));
 651                                        break;
 652                                }
 653
 654                                fi->bf = tbf;
 655                        }
 656
 657                        /*
 658                         * Put this buffer to the temporary pending
 659                         * queue to retain ordering
 660                         */
 661                        __skb_queue_tail(&bf_pending, skb);
 662                }
 663
 664                bf = bf_next;
 665        }
 666
 667        /* prepend un-acked frames to the beginning of the pending frame queue */
 668        if (!skb_queue_empty(&bf_pending)) {
 669                if (an->sleeping)
 670                        ieee80211_sta_set_buffered(sta, tid->tidno, true);
 671
 672                skb_queue_splice_tail(&bf_pending, &tid->retry_q);
 673                if (!an->sleeping) {
 674                        ath_tx_queue_tid(sc, tid);
 675
 676                        if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
 677                                tid->clear_ps_filter = true;
 678                }
 679        }
 680
 681        if (bar_index >= 0) {
 682                u16 bar_seq = ATH_BA_INDEX2SEQ(seq_first, bar_index);
 683
 684                if (BAW_WITHIN(tid->seq_start, tid->baw_size, bar_seq))
 685                        tid->bar_index = ATH_BA_INDEX(tid->seq_start, bar_seq);
 686
 687                ath_txq_unlock(sc, txq);
 688                ath_send_bar(tid, ATH_BA_INDEX2SEQ(seq_first, bar_index + 1));
 689                ath_txq_lock(sc, txq);
 690        }
 691
 692        if (needreset)
 693                ath9k_queue_reset(sc, RESET_TYPE_TX_ERROR);
 694}
 695
 696static bool bf_is_ampdu_not_probing(struct ath_buf *bf)
 697{
 698    struct ieee80211_tx_info *info = IEEE80211_SKB_CB(bf->bf_mpdu);
 699    return bf_isampdu(bf) && !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
 700}
 701
 702static void ath_tx_count_airtime(struct ath_softc *sc, struct ath_node *an,
 703                                 struct ath_atx_tid *tid, struct ath_buf *bf,
 704                                 struct ath_tx_status *ts)
 705{
 706        struct ath_txq *txq = tid->txq;
 707        u32 airtime = 0;
 708        int i;
 709
 710        airtime += ts->duration * (ts->ts_longretry + 1);
 711        for(i = 0; i < ts->ts_rateindex; i++) {
 712                int rate_dur = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc, i);
 713                airtime += rate_dur * bf->rates[i].count;
 714        }
 715
 716        if (sc->airtime_flags & AIRTIME_USE_TX) {
 717                int q = txq->mac80211_qnum;
 718                struct ath_acq *acq = &sc->cur_chan->acq[q];
 719
 720                spin_lock_bh(&acq->lock);
 721                an->airtime_deficit[q] -= airtime;
 722                if (an->airtime_deficit[q] <= 0)
 723                        __ath_tx_queue_tid(sc, tid);
 724                spin_unlock_bh(&acq->lock);
 725        }
 726        ath_debug_airtime(sc, an, 0, airtime);
 727}
 728
 729static void ath_tx_process_buffer(struct ath_softc *sc, struct ath_txq *txq,
 730                                  struct ath_tx_status *ts, struct ath_buf *bf,
 731                                  struct list_head *bf_head)
 732{
 733        struct ieee80211_hw *hw = sc->hw;
 734        struct ieee80211_tx_info *info;
 735        struct ieee80211_sta *sta;
 736        struct ieee80211_hdr *hdr;
 737        struct ath_atx_tid *tid = NULL;
 738        bool txok, flush;
 739
 740        txok = !(ts->ts_status & ATH9K_TXERR_MASK);
 741        flush = !!(ts->ts_status & ATH9K_TX_FLUSH);
 742        txq->axq_tx_inprogress = false;
 743
 744        txq->axq_depth--;
 745        if (bf_is_ampdu_not_probing(bf))
 746                txq->axq_ampdu_depth--;
 747
 748        ts->duration = ath9k_hw_get_duration(sc->sc_ah, bf->bf_desc,
 749                                             ts->ts_rateindex);
 750
 751        hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
 752        sta = ieee80211_find_sta_by_ifaddr(hw, hdr->addr1, hdr->addr2);
 753        if (sta) {
 754                struct ath_node *an = (struct ath_node *)sta->drv_priv;
 755                tid = ath_get_skb_tid(sc, an, bf->bf_mpdu);
 756                ath_tx_count_airtime(sc, an, tid, bf, ts);
 757                if (ts->ts_status & (ATH9K_TXERR_FILT | ATH9K_TXERR_XRETRY))
 758                        tid->clear_ps_filter = true;
 759        }
 760
 761        if (!bf_isampdu(bf)) {
 762                if (!flush) {
 763                        info = IEEE80211_SKB_CB(bf->bf_mpdu);
 764                        memcpy(info->control.rates, bf->rates,
 765                               sizeof(info->control.rates));
 766                        ath_tx_rc_status(sc, bf, ts, 1, txok ? 0 : 1, txok);
 767                        ath_dynack_sample_tx_ts(sc->sc_ah, bf->bf_mpdu, ts);
 768                }
 769                ath_tx_complete_buf(sc, bf, txq, bf_head, sta, ts, txok);
 770        } else
 771                ath_tx_complete_aggr(sc, txq, bf, bf_head, sta, tid, ts, txok);
 772
 773        if (!flush)
 774                ath_txq_schedule(sc, txq);
 775}
 776
 777static bool ath_lookup_legacy(struct ath_buf *bf)
 778{
 779        struct sk_buff *skb;
 780        struct ieee80211_tx_info *tx_info;
 781        struct ieee80211_tx_rate *rates;
 782        int i;
 783
 784        skb = bf->bf_mpdu;
 785        tx_info = IEEE80211_SKB_CB(skb);
 786        rates = tx_info->control.rates;
 787
 788        for (i = 0; i < 4; i++) {
 789                if (!rates[i].count || rates[i].idx < 0)
 790                        break;
 791
 792                if (!(rates[i].flags & IEEE80211_TX_RC_MCS))
 793                        return true;
 794        }
 795
 796        return false;
 797}
 798
 799static u32 ath_lookup_rate(struct ath_softc *sc, struct ath_buf *bf,
 800                           struct ath_atx_tid *tid)
 801{
 802        struct sk_buff *skb;
 803        struct ieee80211_tx_info *tx_info;
 804        struct ieee80211_tx_rate *rates;
 805        u32 max_4ms_framelen, frmlen;
 806        u16 aggr_limit, bt_aggr_limit, legacy = 0;
 807        int q = tid->txq->mac80211_qnum;
 808        int i;
 809
 810        skb = bf->bf_mpdu;
 811        tx_info = IEEE80211_SKB_CB(skb);
 812        rates = bf->rates;
 813
 814        /*
 815         * Find the lowest frame length among the rate series that will have a
 816         * 4ms (or TXOP limited) transmit duration.
 817         */
 818        max_4ms_framelen = ATH_AMPDU_LIMIT_MAX;
 819
 820        for (i = 0; i < 4; i++) {
 821                int modeidx;
 822
 823                if (!rates[i].count)
 824                        continue;
 825
 826                if (!(rates[i].flags & IEEE80211_TX_RC_MCS)) {
 827                        legacy = 1;
 828                        break;
 829                }
 830
 831                if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
 832                        modeidx = MCS_HT40;
 833                else
 834                        modeidx = MCS_HT20;
 835
 836                if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
 837                        modeidx++;
 838
 839                frmlen = sc->tx.max_aggr_framelen[q][modeidx][rates[i].idx];
 840                max_4ms_framelen = min(max_4ms_framelen, frmlen);
 841        }
 842
 843        /*
 844         * limit aggregate size by the minimum rate if rate selected is
 845         * not a probe rate, if rate selected is a probe rate then
 846         * avoid aggregation of this packet.
 847         */
 848        if (tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE || legacy)
 849                return 0;
 850
 851        aggr_limit = min(max_4ms_framelen, (u32)ATH_AMPDU_LIMIT_MAX);
 852
 853        /*
 854         * Override the default aggregation limit for BTCOEX.
 855         */
 856        bt_aggr_limit = ath9k_btcoex_aggr_limit(sc, max_4ms_framelen);
 857        if (bt_aggr_limit)
 858                aggr_limit = bt_aggr_limit;
 859
 860        if (tid->an->maxampdu)
 861                aggr_limit = min(aggr_limit, tid->an->maxampdu);
 862
 863        return aggr_limit;
 864}
 865
 866/*
 867 * Returns the number of delimiters to be added to
 868 * meet the minimum required mpdudensity.
 869 */
 870static int ath_compute_num_delims(struct ath_softc *sc, struct ath_atx_tid *tid,
 871                                  struct ath_buf *bf, u16 frmlen,
 872                                  bool first_subfrm)
 873{
 874#define FIRST_DESC_NDELIMS 60
 875        u32 nsymbits, nsymbols;
 876        u16 minlen;
 877        u8 flags, rix;
 878        int width, streams, half_gi, ndelim, mindelim;
 879        struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
 880
 881        /* Select standard number of delimiters based on frame length alone */
 882        ndelim = ATH_AGGR_GET_NDELIM(frmlen);
 883
 884        /*
 885         * If encryption enabled, hardware requires some more padding between
 886         * subframes.
 887         * TODO - this could be improved to be dependent on the rate.
 888         *      The hardware can keep up at lower rates, but not higher rates
 889         */
 890        if ((fi->keyix != ATH9K_TXKEYIX_INVALID) &&
 891            !(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA))
 892                ndelim += ATH_AGGR_ENCRYPTDELIM;
 893
 894        /*
 895         * Add delimiter when using RTS/CTS with aggregation
 896         * and non enterprise AR9003 card
 897         */
 898        if (first_subfrm && !AR_SREV_9580_10_OR_LATER(sc->sc_ah) &&
 899            (sc->sc_ah->ent_mode & AR_ENT_OTP_MIN_PKT_SIZE_DISABLE))
 900                ndelim = max(ndelim, FIRST_DESC_NDELIMS);
 901
 902        /*
 903         * Convert desired mpdu density from microeconds to bytes based
 904         * on highest rate in rate series (i.e. first rate) to determine
 905         * required minimum length for subframe. Take into account
 906         * whether high rate is 20 or 40Mhz and half or full GI.
 907         *
 908         * If there is no mpdu density restriction, no further calculation
 909         * is needed.
 910         */
 911
 912        if (tid->an->mpdudensity == 0)
 913                return ndelim;
 914
 915        rix = bf->rates[0].idx;
 916        flags = bf->rates[0].flags;
 917        width = (flags & IEEE80211_TX_RC_40_MHZ_WIDTH) ? 1 : 0;
 918        half_gi = (flags & IEEE80211_TX_RC_SHORT_GI) ? 1 : 0;
 919
 920        if (half_gi)
 921                nsymbols = NUM_SYMBOLS_PER_USEC_HALFGI(tid->an->mpdudensity);
 922        else
 923                nsymbols = NUM_SYMBOLS_PER_USEC(tid->an->mpdudensity);
 924
 925        if (nsymbols == 0)
 926                nsymbols = 1;
 927
 928        streams = HT_RC_2_STREAMS(rix);
 929        nsymbits = bits_per_symbol[rix % 8][width] * streams;
 930        minlen = (nsymbols * nsymbits) / BITS_PER_BYTE;
 931
 932        if (frmlen < minlen) {
 933                mindelim = (minlen - frmlen) / ATH_AGGR_DELIM_SZ;
 934                ndelim = max(mindelim, ndelim);
 935        }
 936
 937        return ndelim;
 938}
 939
 940static struct ath_buf *
 941ath_tx_get_tid_subframe(struct ath_softc *sc, struct ath_txq *txq,
 942                        struct ath_atx_tid *tid)
 943{
 944        struct ieee80211_tx_info *tx_info;
 945        struct ath_frame_info *fi;
 946        struct sk_buff *skb, *first_skb = NULL;
 947        struct ath_buf *bf;
 948        u16 seqno;
 949
 950        while (1) {
 951                skb = ath_tid_dequeue(tid);
 952                if (!skb)
 953                        break;
 954
 955                fi = get_frame_info(skb);
 956                bf = fi->bf;
 957                if (!fi->bf)
 958                        bf = ath_tx_setup_buffer(sc, txq, tid, skb);
 959                else
 960                        bf->bf_state.stale = false;
 961
 962                if (!bf) {
 963                        ath_txq_skb_done(sc, txq, skb);
 964                        ieee80211_free_txskb(sc->hw, skb);
 965                        continue;
 966                }
 967
 968                bf->bf_next = NULL;
 969                bf->bf_lastbf = bf;
 970
 971                tx_info = IEEE80211_SKB_CB(skb);
 972                tx_info->flags &= ~IEEE80211_TX_CTL_CLEAR_PS_FILT;
 973
 974                /*
 975                 * No aggregation session is running, but there may be frames
 976                 * from a previous session or a failed attempt in the queue.
 977                 * Send them out as normal data frames
 978                 */
 979                if (!tid->active)
 980                        tx_info->flags &= ~IEEE80211_TX_CTL_AMPDU;
 981
 982                if (!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
 983                        bf->bf_state.bf_type = 0;
 984                        return bf;
 985                }
 986
 987                bf->bf_state.bf_type = BUF_AMPDU | BUF_AGGR;
 988                seqno = bf->bf_state.seqno;
 989
 990                /* do not step over block-ack window */
 991                if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
 992                        __skb_queue_tail(&tid->retry_q, skb);
 993
 994                        /* If there are other skbs in the retry q, they are
 995                         * probably within the BAW, so loop immediately to get
 996                         * one of them. Otherwise the queue can get stuck. */
 997                        if (!skb_queue_is_first(&tid->retry_q, skb) &&
 998                            !WARN_ON(skb == first_skb)) {
 999                                if(!first_skb) /* infinite loop prevention */
1000                                        first_skb = skb;
1001                                continue;
1002                        }
1003                        break;
1004                }
1005
1006                if (tid->bar_index > ATH_BA_INDEX(tid->seq_start, seqno)) {
1007                        struct ath_tx_status ts = {};
1008                        struct list_head bf_head;
1009
1010                        INIT_LIST_HEAD(&bf_head);
1011                        list_add(&bf->list, &bf_head);
1012                        ath_tx_update_baw(sc, tid, seqno);
1013                        ath_tx_complete_buf(sc, bf, txq, &bf_head, NULL, &ts, 0);
1014                        continue;
1015                }
1016
1017                return bf;
1018        }
1019
1020        return NULL;
1021}
1022
1023static int
1024ath_tx_form_aggr(struct ath_softc *sc, struct ath_txq *txq,
1025                 struct ath_atx_tid *tid, struct list_head *bf_q,
1026                 struct ath_buf *bf_first)
1027{
1028#define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
1029        struct ath_buf *bf = bf_first, *bf_prev = NULL;
1030        int nframes = 0, ndelim;
1031        u16 aggr_limit = 0, al = 0, bpad = 0,
1032            al_delta, h_baw = tid->baw_size / 2;
1033        struct ieee80211_tx_info *tx_info;
1034        struct ath_frame_info *fi;
1035        struct sk_buff *skb;
1036
1037
1038        bf = bf_first;
1039        aggr_limit = ath_lookup_rate(sc, bf, tid);
1040
1041        while (bf)
1042        {
1043                skb = bf->bf_mpdu;
1044                fi = get_frame_info(skb);
1045
1046                /* do not exceed aggregation limit */
1047                al_delta = ATH_AGGR_DELIM_SZ + fi->framelen;
1048                if (nframes) {
1049                        if (aggr_limit < al + bpad + al_delta ||
1050                            ath_lookup_legacy(bf) || nframes >= h_baw)
1051                                goto stop;
1052
1053                        tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1054                        if ((tx_info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) ||
1055                            !(tx_info->flags & IEEE80211_TX_CTL_AMPDU))
1056                                goto stop;
1057                }
1058
1059                /* add padding for previous frame to aggregation length */
1060                al += bpad + al_delta;
1061
1062                /*
1063                 * Get the delimiters needed to meet the MPDU
1064                 * density for this node.
1065                 */
1066                ndelim = ath_compute_num_delims(sc, tid, bf_first, fi->framelen,
1067                                                !nframes);
1068                bpad = PADBYTES(al_delta) + (ndelim << 2);
1069
1070                nframes++;
1071                bf->bf_next = NULL;
1072
1073                /* link buffers of this frame to the aggregate */
1074                if (!fi->baw_tracked)
1075                        ath_tx_addto_baw(sc, tid, bf);
1076                bf->bf_state.ndelim = ndelim;
1077
1078                list_add_tail(&bf->list, bf_q);
1079                if (bf_prev)
1080                        bf_prev->bf_next = bf;
1081
1082                bf_prev = bf;
1083
1084                bf = ath_tx_get_tid_subframe(sc, txq, tid);
1085        }
1086        goto finish;
1087stop:
1088        __skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1089finish:
1090        bf = bf_first;
1091        bf->bf_lastbf = bf_prev;
1092
1093        if (bf == bf_prev) {
1094                al = get_frame_info(bf->bf_mpdu)->framelen;
1095                bf->bf_state.bf_type = BUF_AMPDU;
1096        } else {
1097                TX_STAT_INC(txq->axq_qnum, a_aggr);
1098        }
1099
1100        return al;
1101#undef PADBYTES
1102}
1103
1104/*
1105 * rix - rate index
1106 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
1107 * width  - 0 for 20 MHz, 1 for 40 MHz
1108 * half_gi - to use 4us v/s 3.6 us for symbol time
1109 */
1110u32 ath_pkt_duration(struct ath_softc *sc, u8 rix, int pktlen,
1111                     int width, int half_gi, bool shortPreamble)
1112{
1113        u32 nbits, nsymbits, duration, nsymbols;
1114        int streams;
1115
1116        /* find number of symbols: PLCP + data */
1117        streams = HT_RC_2_STREAMS(rix);
1118        nbits = (pktlen << 3) + OFDM_PLCP_BITS;
1119        nsymbits = bits_per_symbol[rix % 8][width] * streams;
1120        nsymbols = (nbits + nsymbits - 1) / nsymbits;
1121
1122        if (!half_gi)
1123                duration = SYMBOL_TIME(nsymbols);
1124        else
1125                duration = SYMBOL_TIME_HALFGI(nsymbols);
1126
1127        /* addup duration for legacy/ht training and signal fields */
1128        duration += L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1129
1130        return duration;
1131}
1132
1133static int ath_max_framelen(int usec, int mcs, bool ht40, bool sgi)
1134{
1135        int streams = HT_RC_2_STREAMS(mcs);
1136        int symbols, bits;
1137        int bytes = 0;
1138
1139        usec -= L_STF + L_LTF + L_SIG + HT_SIG + HT_STF + HT_LTF(streams);
1140        symbols = sgi ? TIME_SYMBOLS_HALFGI(usec) : TIME_SYMBOLS(usec);
1141        bits = symbols * bits_per_symbol[mcs % 8][ht40] * streams;
1142        bits -= OFDM_PLCP_BITS;
1143        bytes = bits / 8;
1144        if (bytes > 65532)
1145                bytes = 65532;
1146
1147        return bytes;
1148}
1149
1150void ath_update_max_aggr_framelen(struct ath_softc *sc, int queue, int txop)
1151{
1152        u16 *cur_ht20, *cur_ht20_sgi, *cur_ht40, *cur_ht40_sgi;
1153        int mcs;
1154
1155        /* 4ms is the default (and maximum) duration */
1156        if (!txop || txop > 4096)
1157                txop = 4096;
1158
1159        cur_ht20 = sc->tx.max_aggr_framelen[queue][MCS_HT20];
1160        cur_ht20_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT20_SGI];
1161        cur_ht40 = sc->tx.max_aggr_framelen[queue][MCS_HT40];
1162        cur_ht40_sgi = sc->tx.max_aggr_framelen[queue][MCS_HT40_SGI];
1163        for (mcs = 0; mcs < 32; mcs++) {
1164                cur_ht20[mcs] = ath_max_framelen(txop, mcs, false, false);
1165                cur_ht20_sgi[mcs] = ath_max_framelen(txop, mcs, false, true);
1166                cur_ht40[mcs] = ath_max_framelen(txop, mcs, true, false);
1167                cur_ht40_sgi[mcs] = ath_max_framelen(txop, mcs, true, true);
1168        }
1169}
1170
1171static u8 ath_get_rate_txpower(struct ath_softc *sc, struct ath_buf *bf,
1172                               u8 rateidx, bool is_40, bool is_cck)
1173{
1174        u8 max_power;
1175        struct sk_buff *skb;
1176        struct ath_frame_info *fi;
1177        struct ieee80211_tx_info *info;
1178        struct ath_hw *ah = sc->sc_ah;
1179
1180        if (sc->tx99_state || !ah->tpc_enabled)
1181                return MAX_RATE_POWER;
1182
1183        skb = bf->bf_mpdu;
1184        fi = get_frame_info(skb);
1185        info = IEEE80211_SKB_CB(skb);
1186
1187        if (!AR_SREV_9300_20_OR_LATER(ah)) {
1188                int txpower = fi->tx_power;
1189
1190                if (is_40) {
1191                        u8 power_ht40delta;
1192                        struct ar5416_eeprom_def *eep = &ah->eeprom.def;
1193                        u16 eeprom_rev = ah->eep_ops->get_eeprom_rev(ah);
1194
1195                        if (eeprom_rev >= AR5416_EEP_MINOR_VER_2) {
1196                                bool is_2ghz;
1197                                struct modal_eep_header *pmodal;
1198
1199                                is_2ghz = info->band == NL80211_BAND_2GHZ;
1200                                pmodal = &eep->modalHeader[is_2ghz];
1201                                power_ht40delta = pmodal->ht40PowerIncForPdadc;
1202                        } else {
1203                                power_ht40delta = 2;
1204                        }
1205                        txpower += power_ht40delta;
1206                }
1207
1208                if (AR_SREV_9287(ah) || AR_SREV_9285(ah) ||
1209                    AR_SREV_9271(ah)) {
1210                        txpower -= 2 * AR9287_PWR_TABLE_OFFSET_DB;
1211                } else if (AR_SREV_9280_20_OR_LATER(ah)) {
1212                        s8 power_offset;
1213
1214                        power_offset = ah->eep_ops->get_eeprom(ah,
1215                                                        EEP_PWR_TABLE_OFFSET);
1216                        txpower -= 2 * power_offset;
1217                }
1218
1219                if (OLC_FOR_AR9280_20_LATER && is_cck)
1220                        txpower -= 2;
1221
1222                txpower = max(txpower, 0);
1223                max_power = min_t(u8, ah->tx_power[rateidx], txpower);
1224
1225                /* XXX: clamp minimum TX power at 1 for AR9160 since if
1226                 * max_power is set to 0, frames are transmitted at max
1227                 * TX power
1228                 */
1229                if (!max_power && !AR_SREV_9280_20_OR_LATER(ah))
1230                        max_power = 1;
1231        } else if (!bf->bf_state.bfs_paprd) {
1232                if (rateidx < 8 && (info->flags & IEEE80211_TX_CTL_STBC))
1233                        max_power = min_t(u8, ah->tx_power_stbc[rateidx],
1234                                          fi->tx_power);
1235                else
1236                        max_power = min_t(u8, ah->tx_power[rateidx],
1237                                          fi->tx_power);
1238        } else {
1239                max_power = ah->paprd_training_power;
1240        }
1241
1242        return max_power;
1243}
1244
1245static void ath_buf_set_rate(struct ath_softc *sc, struct ath_buf *bf,
1246                             struct ath_tx_info *info, int len, bool rts)
1247{
1248        struct ath_hw *ah = sc->sc_ah;
1249        struct ath_common *common = ath9k_hw_common(ah);
1250        struct sk_buff *skb;
1251        struct ieee80211_tx_info *tx_info;
1252        struct ieee80211_tx_rate *rates;
1253        const struct ieee80211_rate *rate;
1254        struct ieee80211_hdr *hdr;
1255        struct ath_frame_info *fi = get_frame_info(bf->bf_mpdu);
1256        u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1257        int i;
1258        u8 rix = 0;
1259
1260        skb = bf->bf_mpdu;
1261        tx_info = IEEE80211_SKB_CB(skb);
1262        rates = bf->rates;
1263        hdr = (struct ieee80211_hdr *)skb->data;
1264
1265        /* set dur_update_en for l-sig computation except for PS-Poll frames */
1266        info->dur_update = !ieee80211_is_pspoll(hdr->frame_control);
1267        info->rtscts_rate = fi->rtscts_rate;
1268
1269        for (i = 0; i < ARRAY_SIZE(bf->rates); i++) {
1270                bool is_40, is_sgi, is_sp, is_cck;
1271                int phy;
1272
1273                if (!rates[i].count || (rates[i].idx < 0))
1274                        continue;
1275
1276                rix = rates[i].idx;
1277                info->rates[i].Tries = rates[i].count;
1278
1279                /*
1280                 * Handle RTS threshold for unaggregated HT frames.
1281                 */
1282                if (bf_isampdu(bf) && !bf_isaggr(bf) &&
1283                    (rates[i].flags & IEEE80211_TX_RC_MCS) &&
1284                    unlikely(rts_thresh != (u32) -1)) {
1285                        if (!rts_thresh || (len > rts_thresh))
1286                                rts = true;
1287                }
1288
1289                if (rts || rates[i].flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1290                        info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1291                        info->flags |= ATH9K_TXDESC_RTSENA;
1292                } else if (rates[i].flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1293                        info->rates[i].RateFlags |= ATH9K_RATESERIES_RTS_CTS;
1294                        info->flags |= ATH9K_TXDESC_CTSENA;
1295                }
1296
1297                if (rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1298                        info->rates[i].RateFlags |= ATH9K_RATESERIES_2040;
1299                if (rates[i].flags & IEEE80211_TX_RC_SHORT_GI)
1300                        info->rates[i].RateFlags |= ATH9K_RATESERIES_HALFGI;
1301
1302                is_sgi = !!(rates[i].flags & IEEE80211_TX_RC_SHORT_GI);
1303                is_40 = !!(rates[i].flags & IEEE80211_TX_RC_40_MHZ_WIDTH);
1304                is_sp = !!(rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE);
1305
1306                if (rates[i].flags & IEEE80211_TX_RC_MCS) {
1307                        /* MCS rates */
1308                        info->rates[i].Rate = rix | 0x80;
1309                        info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1310                                        ah->txchainmask, info->rates[i].Rate);
1311                        info->rates[i].PktDuration = ath_pkt_duration(sc, rix, len,
1312                                 is_40, is_sgi, is_sp);
1313                        if (rix < 8 && (tx_info->flags & IEEE80211_TX_CTL_STBC))
1314                                info->rates[i].RateFlags |= ATH9K_RATESERIES_STBC;
1315
1316                        info->txpower[i] = ath_get_rate_txpower(sc, bf, rix,
1317                                                                is_40, false);
1318                        continue;
1319                }
1320
1321                /* legacy rates */
1322                rate = &common->sbands[tx_info->band].bitrates[rates[i].idx];
1323                if ((tx_info->band == NL80211_BAND_2GHZ) &&
1324                    !(rate->flags & IEEE80211_RATE_ERP_G))
1325                        phy = WLAN_RC_PHY_CCK;
1326                else
1327                        phy = WLAN_RC_PHY_OFDM;
1328
1329                info->rates[i].Rate = rate->hw_value;
1330                if (rate->hw_value_short) {
1331                        if (rates[i].flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
1332                                info->rates[i].Rate |= rate->hw_value_short;
1333                } else {
1334                        is_sp = false;
1335                }
1336
1337                if (bf->bf_state.bfs_paprd)
1338                        info->rates[i].ChSel = ah->txchainmask;
1339                else
1340                        info->rates[i].ChSel = ath_txchainmask_reduction(sc,
1341                                        ah->txchainmask, info->rates[i].Rate);
1342
1343                info->rates[i].PktDuration = ath9k_hw_computetxtime(sc->sc_ah,
1344                        phy, rate->bitrate * 100, len, rix, is_sp);
1345
1346                is_cck = IS_CCK_RATE(info->rates[i].Rate);
1347                info->txpower[i] = ath_get_rate_txpower(sc, bf, rix, false,
1348                                                        is_cck);
1349        }
1350
1351        /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
1352        if (bf_isaggr(bf) && (len > sc->sc_ah->caps.rts_aggr_limit))
1353                info->flags &= ~ATH9K_TXDESC_RTSENA;
1354
1355        /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
1356        if (info->flags & ATH9K_TXDESC_RTSENA)
1357                info->flags &= ~ATH9K_TXDESC_CTSENA;
1358}
1359
1360static enum ath9k_pkt_type get_hw_packet_type(struct sk_buff *skb)
1361{
1362        struct ieee80211_hdr *hdr;
1363        enum ath9k_pkt_type htype;
1364        __le16 fc;
1365
1366        hdr = (struct ieee80211_hdr *)skb->data;
1367        fc = hdr->frame_control;
1368
1369        if (ieee80211_is_beacon(fc))
1370                htype = ATH9K_PKT_TYPE_BEACON;
1371        else if (ieee80211_is_probe_resp(fc))
1372                htype = ATH9K_PKT_TYPE_PROBE_RESP;
1373        else if (ieee80211_is_atim(fc))
1374                htype = ATH9K_PKT_TYPE_ATIM;
1375        else if (ieee80211_is_pspoll(fc))
1376                htype = ATH9K_PKT_TYPE_PSPOLL;
1377        else
1378                htype = ATH9K_PKT_TYPE_NORMAL;
1379
1380        return htype;
1381}
1382
1383static void ath_tx_fill_desc(struct ath_softc *sc, struct ath_buf *bf,
1384                             struct ath_txq *txq, int len)
1385{
1386        struct ath_hw *ah = sc->sc_ah;
1387        struct ath_buf *bf_first = NULL;
1388        struct ath_tx_info info;
1389        u32 rts_thresh = sc->hw->wiphy->rts_threshold;
1390        bool rts = false;
1391
1392        memset(&info, 0, sizeof(info));
1393        info.is_first = true;
1394        info.is_last = true;
1395        info.qcu = txq->axq_qnum;
1396
1397        while (bf) {
1398                struct sk_buff *skb = bf->bf_mpdu;
1399                struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
1400                struct ath_frame_info *fi = get_frame_info(skb);
1401                bool aggr = !!(bf->bf_state.bf_type & BUF_AGGR);
1402
1403                info.type = get_hw_packet_type(skb);
1404                if (bf->bf_next)
1405                        info.link = bf->bf_next->bf_daddr;
1406                else
1407                        info.link = (sc->tx99_state) ? bf->bf_daddr : 0;
1408
1409                if (!bf_first) {
1410                        bf_first = bf;
1411
1412                        if (!sc->tx99_state)
1413                                info.flags = ATH9K_TXDESC_INTREQ;
1414                        if ((tx_info->flags & IEEE80211_TX_CTL_CLEAR_PS_FILT) ||
1415                            txq == sc->tx.uapsdq)
1416                                info.flags |= ATH9K_TXDESC_CLRDMASK;
1417
1418                        if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
1419                                info.flags |= ATH9K_TXDESC_NOACK;
1420                        if (tx_info->flags & IEEE80211_TX_CTL_LDPC)
1421                                info.flags |= ATH9K_TXDESC_LDPC;
1422
1423                        if (bf->bf_state.bfs_paprd)
1424                                info.flags |= (u32) bf->bf_state.bfs_paprd <<
1425                                              ATH9K_TXDESC_PAPRD_S;
1426
1427                        /*
1428                         * mac80211 doesn't handle RTS threshold for HT because
1429                         * the decision has to be taken based on AMPDU length
1430                         * and aggregation is done entirely inside ath9k.
1431                         * Set the RTS/CTS flag for the first subframe based
1432                         * on the threshold.
1433                         */
1434                        if (aggr && (bf == bf_first) &&
1435                            unlikely(rts_thresh != (u32) -1)) {
1436                                /*
1437                                 * "len" is the size of the entire AMPDU.
1438                                 */
1439                                if (!rts_thresh || (len > rts_thresh))
1440                                        rts = true;
1441                        }
1442
1443                        if (!aggr)
1444                                len = fi->framelen;
1445
1446                        ath_buf_set_rate(sc, bf, &info, len, rts);
1447                }
1448
1449                info.buf_addr[0] = bf->bf_buf_addr;
1450                info.buf_len[0] = skb->len;
1451                info.pkt_len = fi->framelen;
1452                info.keyix = fi->keyix;
1453                info.keytype = fi->keytype;
1454
1455                if (aggr) {
1456                        if (bf == bf_first)
1457                                info.aggr = AGGR_BUF_FIRST;
1458                        else if (bf == bf_first->bf_lastbf)
1459                                info.aggr = AGGR_BUF_LAST;
1460                        else
1461                                info.aggr = AGGR_BUF_MIDDLE;
1462
1463                        info.ndelim = bf->bf_state.ndelim;
1464                        info.aggr_len = len;
1465                }
1466
1467                if (bf == bf_first->bf_lastbf)
1468                        bf_first = NULL;
1469
1470                ath9k_hw_set_txdesc(ah, bf->bf_desc, &info);
1471                bf = bf->bf_next;
1472        }
1473}
1474
1475static void
1476ath_tx_form_burst(struct ath_softc *sc, struct ath_txq *txq,
1477                  struct ath_atx_tid *tid, struct list_head *bf_q,
1478                  struct ath_buf *bf_first)
1479{
1480        struct ath_buf *bf = bf_first, *bf_prev = NULL;
1481        int nframes = 0;
1482
1483        do {
1484                struct ieee80211_tx_info *tx_info;
1485
1486                nframes++;
1487                list_add_tail(&bf->list, bf_q);
1488                if (bf_prev)
1489                        bf_prev->bf_next = bf;
1490                bf_prev = bf;
1491
1492                if (nframes >= 2)
1493                        break;
1494
1495                bf = ath_tx_get_tid_subframe(sc, txq, tid);
1496                if (!bf)
1497                        break;
1498
1499                tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1500                if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
1501                        __skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1502                        break;
1503                }
1504
1505                ath_set_rates(tid->an->vif, tid->an->sta, bf);
1506        } while (1);
1507}
1508
1509static bool ath_tx_sched_aggr(struct ath_softc *sc, struct ath_txq *txq,
1510                              struct ath_atx_tid *tid)
1511{
1512        struct ath_buf *bf;
1513        struct ieee80211_tx_info *tx_info;
1514        struct list_head bf_q;
1515        int aggr_len = 0;
1516        bool aggr;
1517
1518        if (!ath_tid_has_buffered(tid))
1519                return false;
1520
1521        INIT_LIST_HEAD(&bf_q);
1522
1523        bf = ath_tx_get_tid_subframe(sc, txq, tid);
1524        if (!bf)
1525                return false;
1526
1527        tx_info = IEEE80211_SKB_CB(bf->bf_mpdu);
1528        aggr = !!(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
1529        if ((aggr && txq->axq_ampdu_depth >= ATH_AGGR_MIN_QDEPTH) ||
1530            (!aggr && txq->axq_depth >= ATH_NON_AGGR_MIN_QDEPTH)) {
1531                __skb_queue_tail(&tid->retry_q, bf->bf_mpdu);
1532                return false;
1533        }
1534
1535        ath_set_rates(tid->an->vif, tid->an->sta, bf);
1536        if (aggr)
1537                aggr_len = ath_tx_form_aggr(sc, txq, tid, &bf_q, bf);
1538        else
1539                ath_tx_form_burst(sc, txq, tid, &bf_q, bf);
1540
1541        if (list_empty(&bf_q))
1542                return false;
1543
1544        if (tid->clear_ps_filter || tid->an->no_ps_filter) {
1545                tid->clear_ps_filter = false;
1546                tx_info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
1547        }
1548
1549        ath_tx_fill_desc(sc, bf, txq, aggr_len);
1550        ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1551        return true;
1552}
1553
1554int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
1555                      u16 tid, u16 *ssn)
1556{
1557        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1558        struct ath_atx_tid *txtid;
1559        struct ath_txq *txq;
1560        struct ath_node *an;
1561        u8 density;
1562
1563        ath_dbg(common, XMIT, "%s called\n", __func__);
1564
1565        an = (struct ath_node *)sta->drv_priv;
1566        txtid = ATH_AN_2_TID(an, tid);
1567        txq = txtid->txq;
1568
1569        ath_txq_lock(sc, txq);
1570
1571        /* update ampdu factor/density, they may have changed. This may happen
1572         * in HT IBSS when a beacon with HT-info is received after the station
1573         * has already been added.
1574         */
1575        if (sta->ht_cap.ht_supported) {
1576                an->maxampdu = (1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
1577                                      sta->ht_cap.ampdu_factor)) - 1;
1578                density = ath9k_parse_mpdudensity(sta->ht_cap.ampdu_density);
1579                an->mpdudensity = density;
1580        }
1581
1582        txtid->active = true;
1583        *ssn = txtid->seq_start = txtid->seq_next;
1584        txtid->bar_index = -1;
1585
1586        memset(txtid->tx_buf, 0, sizeof(txtid->tx_buf));
1587        txtid->baw_head = txtid->baw_tail = 0;
1588
1589        ath_txq_unlock_complete(sc, txq);
1590
1591        return 0;
1592}
1593
1594void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
1595{
1596        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1597        struct ath_node *an = (struct ath_node *)sta->drv_priv;
1598        struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
1599        struct ath_txq *txq = txtid->txq;
1600
1601        ath_dbg(common, XMIT, "%s called\n", __func__);
1602
1603        ath_txq_lock(sc, txq);
1604        txtid->active = false;
1605        ath_tx_flush_tid(sc, txtid);
1606        ath_txq_unlock_complete(sc, txq);
1607}
1608
1609void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
1610                       struct ath_node *an)
1611{
1612        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1613        struct ath_atx_tid *tid;
1614        struct ath_txq *txq;
1615        int tidno;
1616
1617        ath_dbg(common, XMIT, "%s called\n", __func__);
1618
1619        for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
1620                tid = ath_node_to_tid(an, tidno);
1621                txq = tid->txq;
1622
1623                ath_txq_lock(sc, txq);
1624
1625                if (list_empty(&tid->list)) {
1626                        ath_txq_unlock(sc, txq);
1627                        continue;
1628                }
1629
1630                if (!skb_queue_empty(&tid->retry_q))
1631                        ieee80211_sta_set_buffered(sta, tid->tidno, true);
1632
1633                list_del_init(&tid->list);
1634
1635                ath_txq_unlock(sc, txq);
1636        }
1637}
1638
1639void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
1640{
1641        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1642        struct ath_atx_tid *tid;
1643        struct ath_txq *txq;
1644        int tidno;
1645
1646        ath_dbg(common, XMIT, "%s called\n", __func__);
1647
1648        for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
1649                tid = ath_node_to_tid(an, tidno);
1650                txq = tid->txq;
1651
1652                ath_txq_lock(sc, txq);
1653                tid->clear_ps_filter = true;
1654                if (ath_tid_has_buffered(tid)) {
1655                        ath_tx_queue_tid(sc, tid);
1656                        ath_txq_schedule(sc, txq);
1657                }
1658                ath_txq_unlock_complete(sc, txq);
1659        }
1660}
1661
1662void ath9k_release_buffered_frames(struct ieee80211_hw *hw,
1663                                   struct ieee80211_sta *sta,
1664                                   u16 tids, int nframes,
1665                                   enum ieee80211_frame_release_type reason,
1666                                   bool more_data)
1667{
1668        struct ath_softc *sc = hw->priv;
1669        struct ath_node *an = (struct ath_node *)sta->drv_priv;
1670        struct ath_txq *txq = sc->tx.uapsdq;
1671        struct ieee80211_tx_info *info;
1672        struct list_head bf_q;
1673        struct ath_buf *bf_tail = NULL, *bf;
1674        int sent = 0;
1675        int i;
1676
1677        INIT_LIST_HEAD(&bf_q);
1678        for (i = 0; tids && nframes; i++, tids >>= 1) {
1679                struct ath_atx_tid *tid;
1680
1681                if (!(tids & 1))
1682                        continue;
1683
1684                tid = ATH_AN_2_TID(an, i);
1685
1686                ath_txq_lock(sc, tid->txq);
1687                while (nframes > 0) {
1688                        bf = ath_tx_get_tid_subframe(sc, sc->tx.uapsdq, tid);
1689                        if (!bf)
1690                                break;
1691
1692                        list_add_tail(&bf->list, &bf_q);
1693                        ath_set_rates(tid->an->vif, tid->an->sta, bf);
1694                        if (bf_isampdu(bf)) {
1695                                ath_tx_addto_baw(sc, tid, bf);
1696                                bf->bf_state.bf_type &= ~BUF_AGGR;
1697                        }
1698                        if (bf_tail)
1699                                bf_tail->bf_next = bf;
1700
1701                        bf_tail = bf;
1702                        nframes--;
1703                        sent++;
1704                        TX_STAT_INC(txq->axq_qnum, a_queued_hw);
1705
1706                        if (an->sta && skb_queue_empty(&tid->retry_q))
1707                                ieee80211_sta_set_buffered(an->sta, i, false);
1708                }
1709                ath_txq_unlock_complete(sc, tid->txq);
1710        }
1711
1712        if (list_empty(&bf_q))
1713                return;
1714
1715        info = IEEE80211_SKB_CB(bf_tail->bf_mpdu);
1716        info->flags |= IEEE80211_TX_STATUS_EOSP;
1717
1718        bf = list_first_entry(&bf_q, struct ath_buf, list);
1719        ath_txq_lock(sc, txq);
1720        ath_tx_fill_desc(sc, bf, txq, 0);
1721        ath_tx_txqaddbuf(sc, txq, &bf_q, false);
1722        ath_txq_unlock(sc, txq);
1723}
1724
1725/********************/
1726/* Queue Management */
1727/********************/
1728
1729struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
1730{
1731        struct ath_hw *ah = sc->sc_ah;
1732        struct ath9k_tx_queue_info qi;
1733        static const int subtype_txq_to_hwq[] = {
1734                [IEEE80211_AC_BE] = ATH_TXQ_AC_BE,
1735                [IEEE80211_AC_BK] = ATH_TXQ_AC_BK,
1736                [IEEE80211_AC_VI] = ATH_TXQ_AC_VI,
1737                [IEEE80211_AC_VO] = ATH_TXQ_AC_VO,
1738        };
1739        int axq_qnum, i;
1740
1741        memset(&qi, 0, sizeof(qi));
1742        qi.tqi_subtype = subtype_txq_to_hwq[subtype];
1743        qi.tqi_aifs = ATH9K_TXQ_USEDEFAULT;
1744        qi.tqi_cwmin = ATH9K_TXQ_USEDEFAULT;
1745        qi.tqi_cwmax = ATH9K_TXQ_USEDEFAULT;
1746        qi.tqi_physCompBuf = 0;
1747
1748        /*
1749         * Enable interrupts only for EOL and DESC conditions.
1750         * We mark tx descriptors to receive a DESC interrupt
1751         * when a tx queue gets deep; otherwise waiting for the
1752         * EOL to reap descriptors.  Note that this is done to
1753         * reduce interrupt load and this only defers reaping
1754         * descriptors, never transmitting frames.  Aside from
1755         * reducing interrupts this also permits more concurrency.
1756         * The only potential downside is if the tx queue backs
1757         * up in which case the top half of the kernel may backup
1758         * due to a lack of tx descriptors.
1759         *
1760         * The UAPSD queue is an exception, since we take a desc-
1761         * based intr on the EOSP frames.
1762         */
1763        if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1764                qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
1765        } else {
1766                if (qtype == ATH9K_TX_QUEUE_UAPSD)
1767                        qi.tqi_qflags = TXQ_FLAG_TXDESCINT_ENABLE;
1768                else
1769                        qi.tqi_qflags = TXQ_FLAG_TXEOLINT_ENABLE |
1770                                        TXQ_FLAG_TXDESCINT_ENABLE;
1771        }
1772        axq_qnum = ath9k_hw_setuptxqueue(ah, qtype, &qi);
1773        if (axq_qnum == -1) {
1774                /*
1775                 * NB: don't print a message, this happens
1776                 * normally on parts with too few tx queues
1777                 */
1778                return NULL;
1779        }
1780        if (!ATH_TXQ_SETUP(sc, axq_qnum)) {
1781                struct ath_txq *txq = &sc->tx.txq[axq_qnum];
1782
1783                txq->axq_qnum = axq_qnum;
1784                txq->mac80211_qnum = -1;
1785                txq->axq_link = NULL;
1786                __skb_queue_head_init(&txq->complete_q);
1787                INIT_LIST_HEAD(&txq->axq_q);
1788                spin_lock_init(&txq->axq_lock);
1789                txq->axq_depth = 0;
1790                txq->axq_ampdu_depth = 0;
1791                txq->axq_tx_inprogress = false;
1792                sc->tx.txqsetup |= 1<<axq_qnum;
1793
1794                txq->txq_headidx = txq->txq_tailidx = 0;
1795                for (i = 0; i < ATH_TXFIFO_DEPTH; i++)
1796                        INIT_LIST_HEAD(&txq->txq_fifo[i]);
1797        }
1798        return &sc->tx.txq[axq_qnum];
1799}
1800
1801int ath_txq_update(struct ath_softc *sc, int qnum,
1802                   struct ath9k_tx_queue_info *qinfo)
1803{
1804        struct ath_hw *ah = sc->sc_ah;
1805        int error = 0;
1806        struct ath9k_tx_queue_info qi;
1807
1808        BUG_ON(sc->tx.txq[qnum].axq_qnum != qnum);
1809
1810        ath9k_hw_get_txq_props(ah, qnum, &qi);
1811        qi.tqi_aifs = qinfo->tqi_aifs;
1812        qi.tqi_cwmin = qinfo->tqi_cwmin;
1813        qi.tqi_cwmax = qinfo->tqi_cwmax;
1814        qi.tqi_burstTime = qinfo->tqi_burstTime;
1815        qi.tqi_readyTime = qinfo->tqi_readyTime;
1816
1817        if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
1818                ath_err(ath9k_hw_common(sc->sc_ah),
1819                        "Unable to update hardware queue %u!\n", qnum);
1820                error = -EIO;
1821        } else {
1822                ath9k_hw_resettxqueue(ah, qnum);
1823        }
1824
1825        return error;
1826}
1827
1828int ath_cabq_update(struct ath_softc *sc)
1829{
1830        struct ath9k_tx_queue_info qi;
1831        struct ath_beacon_config *cur_conf = &sc->cur_chan->beacon;
1832        int qnum = sc->beacon.cabq->axq_qnum;
1833
1834        ath9k_hw_get_txq_props(sc->sc_ah, qnum, &qi);
1835
1836        qi.tqi_readyTime = (TU_TO_USEC(cur_conf->beacon_interval) *
1837                            ATH_CABQ_READY_TIME) / 100;
1838        ath_txq_update(sc, qnum, &qi);
1839
1840        return 0;
1841}
1842
1843static void ath_drain_txq_list(struct ath_softc *sc, struct ath_txq *txq,
1844                               struct list_head *list)
1845{
1846        struct ath_buf *bf, *lastbf;
1847        struct list_head bf_head;
1848        struct ath_tx_status ts;
1849
1850        memset(&ts, 0, sizeof(ts));
1851        ts.ts_status = ATH9K_TX_FLUSH;
1852        INIT_LIST_HEAD(&bf_head);
1853
1854        while (!list_empty(list)) {
1855                bf = list_first_entry(list, struct ath_buf, list);
1856
1857                if (bf->bf_state.stale) {
1858                        list_del(&bf->list);
1859
1860                        ath_tx_return_buffer(sc, bf);
1861                        continue;
1862                }
1863
1864                lastbf = bf->bf_lastbf;
1865                list_cut_position(&bf_head, list, &lastbf->list);
1866                ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
1867        }
1868}
1869
1870/*
1871 * Drain a given TX queue (could be Beacon or Data)
1872 *
1873 * This assumes output has been stopped and
1874 * we do not need to block ath_tx_tasklet.
1875 */
1876void ath_draintxq(struct ath_softc *sc, struct ath_txq *txq)
1877{
1878        rcu_read_lock();
1879        ath_txq_lock(sc, txq);
1880
1881        if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
1882                int idx = txq->txq_tailidx;
1883
1884                while (!list_empty(&txq->txq_fifo[idx])) {
1885                        ath_drain_txq_list(sc, txq, &txq->txq_fifo[idx]);
1886
1887                        INCR(idx, ATH_TXFIFO_DEPTH);
1888                }
1889                txq->txq_tailidx = idx;
1890        }
1891
1892        txq->axq_link = NULL;
1893        txq->axq_tx_inprogress = false;
1894        ath_drain_txq_list(sc, txq, &txq->axq_q);
1895
1896        ath_txq_unlock_complete(sc, txq);
1897        rcu_read_unlock();
1898}
1899
1900bool ath_drain_all_txq(struct ath_softc *sc)
1901{
1902        struct ath_hw *ah = sc->sc_ah;
1903        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1904        struct ath_txq *txq;
1905        int i;
1906        u32 npend = 0;
1907
1908        if (test_bit(ATH_OP_INVALID, &common->op_flags))
1909                return true;
1910
1911        ath9k_hw_abort_tx_dma(ah);
1912
1913        /* Check if any queue remains active */
1914        for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1915                if (!ATH_TXQ_SETUP(sc, i))
1916                        continue;
1917
1918                if (!sc->tx.txq[i].axq_depth)
1919                        continue;
1920
1921                if (ath9k_hw_numtxpending(ah, sc->tx.txq[i].axq_qnum))
1922                        npend |= BIT(i);
1923        }
1924
1925        if (npend) {
1926                RESET_STAT_INC(sc, RESET_TX_DMA_ERROR);
1927                ath_dbg(common, RESET,
1928                        "Failed to stop TX DMA, queues=0x%03x!\n", npend);
1929        }
1930
1931        for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
1932                if (!ATH_TXQ_SETUP(sc, i))
1933                        continue;
1934
1935                txq = &sc->tx.txq[i];
1936                ath_draintxq(sc, txq);
1937        }
1938
1939        return !npend;
1940}
1941
1942void ath_tx_cleanupq(struct ath_softc *sc, struct ath_txq *txq)
1943{
1944        ath9k_hw_releasetxqueue(sc->sc_ah, txq->axq_qnum);
1945        sc->tx.txqsetup &= ~(1<<txq->axq_qnum);
1946}
1947
1948/* For each acq entry, for each tid, try to schedule packets
1949 * for transmit until ampdu_depth has reached min Q depth.
1950 */
1951void ath_txq_schedule(struct ath_softc *sc, struct ath_txq *txq)
1952{
1953        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
1954        struct ath_atx_tid *tid;
1955        struct list_head *tid_list;
1956        struct ath_acq *acq;
1957        bool active = AIRTIME_ACTIVE(sc->airtime_flags);
1958
1959        if (txq->mac80211_qnum < 0)
1960                return;
1961
1962        if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
1963                return;
1964
1965        spin_lock_bh(&sc->chan_lock);
1966        rcu_read_lock();
1967        acq = &sc->cur_chan->acq[txq->mac80211_qnum];
1968
1969        if (sc->cur_chan->stopped)
1970                goto out;
1971
1972begin:
1973        tid_list = &acq->acq_new;
1974        if (list_empty(tid_list)) {
1975                tid_list = &acq->acq_old;
1976                if (list_empty(tid_list))
1977                        goto out;
1978        }
1979        tid = list_first_entry(tid_list, struct ath_atx_tid, list);
1980
1981        if (active && tid->an->airtime_deficit[txq->mac80211_qnum] <= 0) {
1982                spin_lock_bh(&acq->lock);
1983                tid->an->airtime_deficit[txq->mac80211_qnum] += ATH_AIRTIME_QUANTUM;
1984                list_move_tail(&tid->list, &acq->acq_old);
1985                spin_unlock_bh(&acq->lock);
1986                goto begin;
1987        }
1988
1989        if (!ath_tid_has_buffered(tid)) {
1990                spin_lock_bh(&acq->lock);
1991                if ((tid_list == &acq->acq_new) && !list_empty(&acq->acq_old))
1992                        list_move_tail(&tid->list, &acq->acq_old);
1993                else {
1994                        list_del_init(&tid->list);
1995                }
1996                spin_unlock_bh(&acq->lock);
1997                goto begin;
1998        }
1999
2000
2001        /*
2002         * If we succeed in scheduling something, immediately restart to make
2003         * sure we keep the HW busy.
2004         */
2005        if(ath_tx_sched_aggr(sc, txq, tid)) {
2006                if (!active) {
2007                        spin_lock_bh(&acq->lock);
2008                        list_move_tail(&tid->list, &acq->acq_old);
2009                        spin_unlock_bh(&acq->lock);
2010                }
2011                goto begin;
2012        }
2013
2014out:
2015        rcu_read_unlock();
2016        spin_unlock_bh(&sc->chan_lock);
2017}
2018
2019void ath_txq_schedule_all(struct ath_softc *sc)
2020{
2021        struct ath_txq *txq;
2022        int i;
2023
2024        for (i = 0; i < IEEE80211_NUM_ACS; i++) {
2025                txq = sc->tx.txq_map[i];
2026
2027                spin_lock_bh(&txq->axq_lock);
2028                ath_txq_schedule(sc, txq);
2029                spin_unlock_bh(&txq->axq_lock);
2030        }
2031}
2032
2033/***********/
2034/* TX, DMA */
2035/***********/
2036
2037/*
2038 * Insert a chain of ath_buf (descriptors) on a txq and
2039 * assume the descriptors are already chained together by caller.
2040 */
2041static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
2042                             struct list_head *head, bool internal)
2043{
2044        struct ath_hw *ah = sc->sc_ah;
2045        struct ath_common *common = ath9k_hw_common(ah);
2046        struct ath_buf *bf, *bf_last;
2047        bool puttxbuf = false;
2048        bool edma;
2049
2050        /*
2051         * Insert the frame on the outbound list and
2052         * pass it on to the hardware.
2053         */
2054
2055        if (list_empty(head))
2056                return;
2057
2058        edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
2059        bf = list_first_entry(head, struct ath_buf, list);
2060        bf_last = list_entry(head->prev, struct ath_buf, list);
2061
2062        ath_dbg(common, QUEUE, "qnum: %d, txq depth: %d\n",
2063                txq->axq_qnum, txq->axq_depth);
2064
2065        if (edma && list_empty(&txq->txq_fifo[txq->txq_headidx])) {
2066                list_splice_tail_init(head, &txq->txq_fifo[txq->txq_headidx]);
2067                INCR(txq->txq_headidx, ATH_TXFIFO_DEPTH);
2068                puttxbuf = true;
2069        } else {
2070                list_splice_tail_init(head, &txq->axq_q);
2071
2072                if (txq->axq_link) {
2073                        ath9k_hw_set_desc_link(ah, txq->axq_link, bf->bf_daddr);
2074                        ath_dbg(common, XMIT, "link[%u] (%p)=%llx (%p)\n",
2075                                txq->axq_qnum, txq->axq_link,
2076                                ito64(bf->bf_daddr), bf->bf_desc);
2077                } else if (!edma)
2078                        puttxbuf = true;
2079
2080                txq->axq_link = bf_last->bf_desc;
2081        }
2082
2083        if (puttxbuf) {
2084                TX_STAT_INC(txq->axq_qnum, puttxbuf);
2085                ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
2086                ath_dbg(common, XMIT, "TXDP[%u] = %llx (%p)\n",
2087                        txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
2088        }
2089
2090        if (!edma || sc->tx99_state) {
2091                TX_STAT_INC(txq->axq_qnum, txstart);
2092                ath9k_hw_txstart(ah, txq->axq_qnum);
2093        }
2094
2095        if (!internal) {
2096                while (bf) {
2097                        txq->axq_depth++;
2098                        if (bf_is_ampdu_not_probing(bf))
2099                                txq->axq_ampdu_depth++;
2100
2101                        bf_last = bf->bf_lastbf;
2102                        bf = bf_last->bf_next;
2103                        bf_last->bf_next = NULL;
2104                }
2105        }
2106}
2107
2108static void ath_tx_send_normal(struct ath_softc *sc, struct ath_txq *txq,
2109                               struct ath_atx_tid *tid, struct sk_buff *skb)
2110{
2111        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2112        struct ath_frame_info *fi = get_frame_info(skb);
2113        struct list_head bf_head;
2114        struct ath_buf *bf = fi->bf;
2115
2116        INIT_LIST_HEAD(&bf_head);
2117        list_add_tail(&bf->list, &bf_head);
2118        bf->bf_state.bf_type = 0;
2119        if (tid && (tx_info->flags & IEEE80211_TX_CTL_AMPDU)) {
2120                bf->bf_state.bf_type = BUF_AMPDU;
2121                ath_tx_addto_baw(sc, tid, bf);
2122        }
2123
2124        bf->bf_next = NULL;
2125        bf->bf_lastbf = bf;
2126        ath_tx_fill_desc(sc, bf, txq, fi->framelen);
2127        ath_tx_txqaddbuf(sc, txq, &bf_head, false);
2128        TX_STAT_INC(txq->axq_qnum, queued);
2129}
2130
2131static void setup_frame_info(struct ieee80211_hw *hw,
2132                             struct ieee80211_sta *sta,
2133                             struct sk_buff *skb,
2134                             int framelen)
2135{
2136        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2137        struct ieee80211_key_conf *hw_key = tx_info->control.hw_key;
2138        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2139        const struct ieee80211_rate *rate;
2140        struct ath_frame_info *fi = get_frame_info(skb);
2141        struct ath_node *an = NULL;
2142        enum ath9k_key_type keytype;
2143        bool short_preamble = false;
2144        u8 txpower;
2145
2146        /*
2147         * We check if Short Preamble is needed for the CTS rate by
2148         * checking the BSS's global flag.
2149         * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
2150         */
2151        if (tx_info->control.vif &&
2152            tx_info->control.vif->bss_conf.use_short_preamble)
2153                short_preamble = true;
2154
2155        rate = ieee80211_get_rts_cts_rate(hw, tx_info);
2156        keytype = ath9k_cmn_get_hw_crypto_keytype(skb);
2157
2158        if (sta)
2159                an = (struct ath_node *) sta->drv_priv;
2160
2161        if (tx_info->control.vif) {
2162                struct ieee80211_vif *vif = tx_info->control.vif;
2163
2164                txpower = 2 * vif->bss_conf.txpower;
2165        } else {
2166                struct ath_softc *sc = hw->priv;
2167
2168                txpower = sc->cur_chan->cur_txpower;
2169        }
2170
2171        memset(fi, 0, sizeof(*fi));
2172        fi->txq = -1;
2173        if (hw_key)
2174                fi->keyix = hw_key->hw_key_idx;
2175        else if (an && ieee80211_is_data(hdr->frame_control) && an->ps_key > 0)
2176                fi->keyix = an->ps_key;
2177        else
2178                fi->keyix = ATH9K_TXKEYIX_INVALID;
2179        fi->keytype = keytype;
2180        fi->framelen = framelen;
2181        fi->tx_power = txpower;
2182
2183        if (!rate)
2184                return;
2185        fi->rtscts_rate = rate->hw_value;
2186        if (short_preamble)
2187                fi->rtscts_rate |= rate->hw_value_short;
2188}
2189
2190u8 ath_txchainmask_reduction(struct ath_softc *sc, u8 chainmask, u32 rate)
2191{
2192        struct ath_hw *ah = sc->sc_ah;
2193        struct ath9k_channel *curchan = ah->curchan;
2194
2195        if ((ah->caps.hw_caps & ATH9K_HW_CAP_APM) && IS_CHAN_5GHZ(curchan) &&
2196            (chainmask == 0x7) && (rate < 0x90))
2197                return 0x3;
2198        else if (AR_SREV_9462(ah) && ath9k_hw_btcoex_is_enabled(ah) &&
2199                 IS_CCK_RATE(rate))
2200                return 0x2;
2201        else
2202                return chainmask;
2203}
2204
2205/*
2206 * Assign a descriptor (and sequence number if necessary,
2207 * and map buffer for DMA. Frees skb on error
2208 */
2209static struct ath_buf *ath_tx_setup_buffer(struct ath_softc *sc,
2210                                           struct ath_txq *txq,
2211                                           struct ath_atx_tid *tid,
2212                                           struct sk_buff *skb)
2213{
2214        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2215        struct ath_frame_info *fi = get_frame_info(skb);
2216        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2217        struct ath_buf *bf;
2218        int fragno;
2219        u16 seqno;
2220
2221        bf = ath_tx_get_buffer(sc);
2222        if (!bf) {
2223                ath_dbg(common, XMIT, "TX buffers are full\n");
2224                return NULL;
2225        }
2226
2227        ATH_TXBUF_RESET(bf);
2228
2229        if (tid && ieee80211_is_data_present(hdr->frame_control)) {
2230                fragno = le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG;
2231                seqno = tid->seq_next;
2232                hdr->seq_ctrl = cpu_to_le16(tid->seq_next << IEEE80211_SEQ_SEQ_SHIFT);
2233
2234                if (fragno)
2235                        hdr->seq_ctrl |= cpu_to_le16(fragno);
2236
2237                if (!ieee80211_has_morefrags(hdr->frame_control))
2238                        INCR(tid->seq_next, IEEE80211_SEQ_MAX);
2239
2240                bf->bf_state.seqno = seqno;
2241        }
2242
2243        bf->bf_mpdu = skb;
2244
2245        bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
2246                                         skb->len, DMA_TO_DEVICE);
2247        if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
2248                bf->bf_mpdu = NULL;
2249                bf->bf_buf_addr = 0;
2250                ath_err(ath9k_hw_common(sc->sc_ah),
2251                        "dma_mapping_error() on TX\n");
2252                ath_tx_return_buffer(sc, bf);
2253                return NULL;
2254        }
2255
2256        fi->bf = bf;
2257
2258        return bf;
2259}
2260
2261void ath_assign_seq(struct ath_common *common, struct sk_buff *skb)
2262{
2263        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2264        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2265        struct ieee80211_vif *vif = info->control.vif;
2266        struct ath_vif *avp;
2267
2268        if (!(info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ))
2269                return;
2270
2271        if (!vif)
2272                return;
2273
2274        avp = (struct ath_vif *)vif->drv_priv;
2275
2276        if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
2277                avp->seq_no += 0x10;
2278
2279        hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
2280        hdr->seq_ctrl |= cpu_to_le16(avp->seq_no);
2281}
2282
2283static int ath_tx_prepare(struct ieee80211_hw *hw, struct sk_buff *skb,
2284                          struct ath_tx_control *txctl)
2285{
2286        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2287        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2288        struct ieee80211_sta *sta = txctl->sta;
2289        struct ieee80211_vif *vif = info->control.vif;
2290        struct ath_vif *avp;
2291        struct ath_softc *sc = hw->priv;
2292        int frmlen = skb->len + FCS_LEN;
2293        int padpos, padsize;
2294
2295        /* NOTE:  sta can be NULL according to net/mac80211.h */
2296        if (sta)
2297                txctl->an = (struct ath_node *)sta->drv_priv;
2298        else if (vif && ieee80211_is_data(hdr->frame_control)) {
2299                avp = (void *)vif->drv_priv;
2300                txctl->an = &avp->mcast_node;
2301        }
2302
2303        if (info->control.hw_key)
2304                frmlen += info->control.hw_key->icv_len;
2305
2306        ath_assign_seq(ath9k_hw_common(sc->sc_ah), skb);
2307
2308        if ((vif && vif->type != NL80211_IFTYPE_AP &&
2309                    vif->type != NL80211_IFTYPE_AP_VLAN) ||
2310            !ieee80211_is_data(hdr->frame_control))
2311                info->flags |= IEEE80211_TX_CTL_CLEAR_PS_FILT;
2312
2313        /* Add the padding after the header if this is not already done */
2314        padpos = ieee80211_hdrlen(hdr->frame_control);
2315        padsize = padpos & 3;
2316        if (padsize && skb->len > padpos) {
2317                if (skb_headroom(skb) < padsize)
2318                        return -ENOMEM;
2319
2320                skb_push(skb, padsize);
2321                memmove(skb->data, skb->data + padsize, padpos);
2322        }
2323
2324        setup_frame_info(hw, sta, skb, frmlen);
2325        return 0;
2326}
2327
2328
2329/* Upon failure caller should free skb */
2330int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
2331                 struct ath_tx_control *txctl)
2332{
2333        struct ieee80211_hdr *hdr;
2334        struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2335        struct ieee80211_sta *sta = txctl->sta;
2336        struct ieee80211_vif *vif = info->control.vif;
2337        struct ath_frame_info *fi = get_frame_info(skb);
2338        struct ath_vif *avp = NULL;
2339        struct ath_softc *sc = hw->priv;
2340        struct ath_txq *txq = txctl->txq;
2341        struct ath_atx_tid *tid = NULL;
2342        struct ath_node *an = NULL;
2343        struct ath_buf *bf;
2344        bool ps_resp;
2345        int q, ret;
2346
2347        if (vif)
2348                avp = (void *)vif->drv_priv;
2349
2350        ps_resp = !!(info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE);
2351
2352        ret = ath_tx_prepare(hw, skb, txctl);
2353        if (ret)
2354            return ret;
2355
2356        hdr = (struct ieee80211_hdr *) skb->data;
2357        /*
2358         * At this point, the vif, hw_key and sta pointers in the tx control
2359         * info are no longer valid (overwritten by the ath_frame_info data.
2360         */
2361
2362        q = skb_get_queue_mapping(skb);
2363
2364        if (ps_resp)
2365                txq = sc->tx.uapsdq;
2366
2367        if (txctl->sta) {
2368                an = (struct ath_node *) sta->drv_priv;
2369                tid = ath_get_skb_tid(sc, an, skb);
2370        }
2371
2372        ath_txq_lock(sc, txq);
2373        if (txq == sc->tx.txq_map[q]) {
2374                fi->txq = q;
2375                ++txq->pending_frames;
2376        }
2377
2378        bf = ath_tx_setup_buffer(sc, txq, tid, skb);
2379        if (!bf) {
2380                ath_txq_skb_done(sc, txq, skb);
2381                if (txctl->paprd)
2382                        dev_kfree_skb_any(skb);
2383                else
2384                        ieee80211_free_txskb(sc->hw, skb);
2385                goto out;
2386        }
2387
2388        bf->bf_state.bfs_paprd = txctl->paprd;
2389
2390        if (txctl->paprd)
2391                bf->bf_state.bfs_paprd_timestamp = jiffies;
2392
2393        ath_set_rates(vif, sta, bf);
2394        ath_tx_send_normal(sc, txq, tid, skb);
2395
2396out:
2397        ath_txq_unlock(sc, txq);
2398
2399        return 0;
2400}
2401
2402void ath_tx_cabq(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2403                 struct sk_buff *skb)
2404{
2405        struct ath_softc *sc = hw->priv;
2406        struct ath_tx_control txctl = {
2407                .txq = sc->beacon.cabq
2408        };
2409        struct ath_tx_info info = {};
2410        struct ieee80211_hdr *hdr;
2411        struct ath_buf *bf_tail = NULL;
2412        struct ath_buf *bf;
2413        LIST_HEAD(bf_q);
2414        int duration = 0;
2415        int max_duration;
2416
2417        max_duration =
2418                sc->cur_chan->beacon.beacon_interval * 1000 *
2419                sc->cur_chan->beacon.dtim_period / ATH_BCBUF;
2420
2421        do {
2422                struct ath_frame_info *fi = get_frame_info(skb);
2423
2424                if (ath_tx_prepare(hw, skb, &txctl))
2425                        break;
2426
2427                bf = ath_tx_setup_buffer(sc, txctl.txq, NULL, skb);
2428                if (!bf)
2429                        break;
2430
2431                bf->bf_lastbf = bf;
2432                ath_set_rates(vif, NULL, bf);
2433                ath_buf_set_rate(sc, bf, &info, fi->framelen, false);
2434                duration += info.rates[0].PktDuration;
2435                if (bf_tail)
2436                        bf_tail->bf_next = bf;
2437
2438                list_add_tail(&bf->list, &bf_q);
2439                bf_tail = bf;
2440                skb = NULL;
2441
2442                if (duration > max_duration)
2443                        break;
2444
2445                skb = ieee80211_get_buffered_bc(hw, vif);
2446        } while(skb);
2447
2448        if (skb)
2449                ieee80211_free_txskb(hw, skb);
2450
2451        if (list_empty(&bf_q))
2452                return;
2453
2454        bf = list_first_entry(&bf_q, struct ath_buf, list);
2455        hdr = (struct ieee80211_hdr *) bf->bf_mpdu->data;
2456
2457        if (hdr->frame_control & cpu_to_le16(IEEE80211_FCTL_MOREDATA)) {
2458                hdr->frame_control &= ~cpu_to_le16(IEEE80211_FCTL_MOREDATA);
2459                dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
2460                        sizeof(*hdr), DMA_TO_DEVICE);
2461        }
2462
2463        ath_txq_lock(sc, txctl.txq);
2464        ath_tx_fill_desc(sc, bf, txctl.txq, 0);
2465        ath_tx_txqaddbuf(sc, txctl.txq, &bf_q, false);
2466        TX_STAT_INC(txctl.txq->axq_qnum, queued);
2467        ath_txq_unlock(sc, txctl.txq);
2468}
2469
2470/*****************/
2471/* TX Completion */
2472/*****************/
2473
2474static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
2475                            int tx_flags, struct ath_txq *txq,
2476                            struct ieee80211_sta *sta)
2477{
2478        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2479        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2480        struct ieee80211_hdr * hdr = (struct ieee80211_hdr *)skb->data;
2481        int padpos, padsize;
2482        unsigned long flags;
2483
2484        ath_dbg(common, XMIT, "TX complete: skb: %p\n", skb);
2485
2486        if (sc->sc_ah->caldata)
2487                set_bit(PAPRD_PACKET_SENT, &sc->sc_ah->caldata->cal_flags);
2488
2489        if (!(tx_flags & ATH_TX_ERROR)) {
2490                if (tx_info->flags & IEEE80211_TX_CTL_NO_ACK)
2491                        tx_info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
2492                else
2493                        tx_info->flags |= IEEE80211_TX_STAT_ACK;
2494        }
2495
2496        if (tx_info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS) {
2497                padpos = ieee80211_hdrlen(hdr->frame_control);
2498                padsize = padpos & 3;
2499                if (padsize && skb->len>padpos+padsize) {
2500                        /*
2501                         * Remove MAC header padding before giving the frame back to
2502                         * mac80211.
2503                         */
2504                        memmove(skb->data + padsize, skb->data, padpos);
2505                        skb_pull(skb, padsize);
2506                }
2507        }
2508
2509        spin_lock_irqsave(&sc->sc_pm_lock, flags);
2510        if ((sc->ps_flags & PS_WAIT_FOR_TX_ACK) && !txq->axq_depth) {
2511                sc->ps_flags &= ~PS_WAIT_FOR_TX_ACK;
2512                ath_dbg(common, PS,
2513                        "Going back to sleep after having received TX status (0x%lx)\n",
2514                        sc->ps_flags & (PS_WAIT_FOR_BEACON |
2515                                        PS_WAIT_FOR_CAB |
2516                                        PS_WAIT_FOR_PSPOLL_DATA |
2517                                        PS_WAIT_FOR_TX_ACK));
2518        }
2519        spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
2520
2521        ath_txq_skb_done(sc, txq, skb);
2522        tx_info->status.status_driver_data[0] = sta;
2523        __skb_queue_tail(&txq->complete_q, skb);
2524}
2525
2526static void ath_tx_complete_buf(struct ath_softc *sc, struct ath_buf *bf,
2527                                struct ath_txq *txq, struct list_head *bf_q,
2528                                struct ieee80211_sta *sta,
2529                                struct ath_tx_status *ts, int txok)
2530{
2531        struct sk_buff *skb = bf->bf_mpdu;
2532        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2533        unsigned long flags;
2534        int tx_flags = 0;
2535
2536        if (!txok)
2537                tx_flags |= ATH_TX_ERROR;
2538
2539        if (ts->ts_status & ATH9K_TXERR_FILT)
2540                tx_info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
2541
2542        dma_unmap_single(sc->dev, bf->bf_buf_addr, skb->len, DMA_TO_DEVICE);
2543        bf->bf_buf_addr = 0;
2544        if (sc->tx99_state)
2545                goto skip_tx_complete;
2546
2547        if (bf->bf_state.bfs_paprd) {
2548                if (time_after(jiffies,
2549                                bf->bf_state.bfs_paprd_timestamp +
2550                                msecs_to_jiffies(ATH_PAPRD_TIMEOUT)))
2551                        dev_kfree_skb_any(skb);
2552                else
2553                        complete(&sc->paprd_complete);
2554        } else {
2555                ath_debug_stat_tx(sc, bf, ts, txq, tx_flags);
2556                ath_tx_complete(sc, skb, tx_flags, txq, sta);
2557        }
2558skip_tx_complete:
2559        /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2560         * accidentally reference it later.
2561         */
2562        bf->bf_mpdu = NULL;
2563
2564        /*
2565         * Return the list of ath_buf of this mpdu to free queue
2566         */
2567        spin_lock_irqsave(&sc->tx.txbuflock, flags);
2568        list_splice_tail_init(bf_q, &sc->tx.txbuf);
2569        spin_unlock_irqrestore(&sc->tx.txbuflock, flags);
2570}
2571
2572static void ath_tx_rc_status(struct ath_softc *sc, struct ath_buf *bf,
2573                             struct ath_tx_status *ts, int nframes, int nbad,
2574                             int txok)
2575{
2576        struct sk_buff *skb = bf->bf_mpdu;
2577        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2578        struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
2579        struct ieee80211_hw *hw = sc->hw;
2580        struct ath_hw *ah = sc->sc_ah;
2581        u8 i, tx_rateindex;
2582
2583        if (txok)
2584                tx_info->status.ack_signal = ts->ts_rssi;
2585
2586        tx_rateindex = ts->ts_rateindex;
2587        WARN_ON(tx_rateindex >= hw->max_rates);
2588
2589        if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
2590                tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
2591
2592                BUG_ON(nbad > nframes);
2593        }
2594        tx_info->status.ampdu_len = nframes;
2595        tx_info->status.ampdu_ack_len = nframes - nbad;
2596
2597        if ((ts->ts_status & ATH9K_TXERR_FILT) == 0 &&
2598            (tx_info->flags & IEEE80211_TX_CTL_NO_ACK) == 0) {
2599                /*
2600                 * If an underrun error is seen assume it as an excessive
2601                 * retry only if max frame trigger level has been reached
2602                 * (2 KB for single stream, and 4 KB for dual stream).
2603                 * Adjust the long retry as if the frame was tried
2604                 * hw->max_rate_tries times to affect how rate control updates
2605                 * PER for the failed rate.
2606                 * In case of congestion on the bus penalizing this type of
2607                 * underruns should help hardware actually transmit new frames
2608                 * successfully by eventually preferring slower rates.
2609                 * This itself should also alleviate congestion on the bus.
2610                 */
2611                if (unlikely(ts->ts_flags & (ATH9K_TX_DATA_UNDERRUN |
2612                                             ATH9K_TX_DELIM_UNDERRUN)) &&
2613                    ieee80211_is_data(hdr->frame_control) &&
2614                    ah->tx_trig_level >= sc->sc_ah->config.max_txtrig_level)
2615                        tx_info->status.rates[tx_rateindex].count =
2616                                hw->max_rate_tries;
2617        }
2618
2619        for (i = tx_rateindex + 1; i < hw->max_rates; i++) {
2620                tx_info->status.rates[i].count = 0;
2621                tx_info->status.rates[i].idx = -1;
2622        }
2623
2624        tx_info->status.rates[tx_rateindex].count = ts->ts_longretry + 1;
2625}
2626
2627static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
2628{
2629        struct ath_hw *ah = sc->sc_ah;
2630        struct ath_common *common = ath9k_hw_common(ah);
2631        struct ath_buf *bf, *lastbf, *bf_held = NULL;
2632        struct list_head bf_head;
2633        struct ath_desc *ds;
2634        struct ath_tx_status ts;
2635        int status;
2636
2637        ath_dbg(common, QUEUE, "tx queue %d (%x), link %p\n",
2638                txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
2639                txq->axq_link);
2640
2641        ath_txq_lock(sc, txq);
2642        for (;;) {
2643                if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2644                        break;
2645
2646                if (list_empty(&txq->axq_q)) {
2647                        txq->axq_link = NULL;
2648                        ath_txq_schedule(sc, txq);
2649                        break;
2650                }
2651                bf = list_first_entry(&txq->axq_q, struct ath_buf, list);
2652
2653                /*
2654                 * There is a race condition that a BH gets scheduled
2655                 * after sw writes TxE and before hw re-load the last
2656                 * descriptor to get the newly chained one.
2657                 * Software must keep the last DONE descriptor as a
2658                 * holding descriptor - software does so by marking
2659                 * it with the STALE flag.
2660                 */
2661                bf_held = NULL;
2662                if (bf->bf_state.stale) {
2663                        bf_held = bf;
2664                        if (list_is_last(&bf_held->list, &txq->axq_q))
2665                                break;
2666
2667                        bf = list_entry(bf_held->list.next, struct ath_buf,
2668                                        list);
2669                }
2670
2671                lastbf = bf->bf_lastbf;
2672                ds = lastbf->bf_desc;
2673
2674                memset(&ts, 0, sizeof(ts));
2675                status = ath9k_hw_txprocdesc(ah, ds, &ts);
2676                if (status == -EINPROGRESS)
2677                        break;
2678
2679                TX_STAT_INC(txq->axq_qnum, txprocdesc);
2680
2681                /*
2682                 * Remove ath_buf's of the same transmit unit from txq,
2683                 * however leave the last descriptor back as the holding
2684                 * descriptor for hw.
2685                 */
2686                lastbf->bf_state.stale = true;
2687                INIT_LIST_HEAD(&bf_head);
2688                if (!list_is_singular(&lastbf->list))
2689                        list_cut_position(&bf_head,
2690                                &txq->axq_q, lastbf->list.prev);
2691
2692                if (bf_held) {
2693                        list_del(&bf_held->list);
2694                        ath_tx_return_buffer(sc, bf_held);
2695                }
2696
2697                ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2698        }
2699        ath_txq_unlock_complete(sc, txq);
2700}
2701
2702void ath_tx_tasklet(struct ath_softc *sc)
2703{
2704        struct ath_hw *ah = sc->sc_ah;
2705        u32 qcumask = ((1 << ATH9K_NUM_TX_QUEUES) - 1) & ah->intr_txqs;
2706        int i;
2707
2708        rcu_read_lock();
2709        for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
2710                if (ATH_TXQ_SETUP(sc, i) && (qcumask & (1 << i)))
2711                        ath_tx_processq(sc, &sc->tx.txq[i]);
2712        }
2713        rcu_read_unlock();
2714}
2715
2716void ath_tx_edma_tasklet(struct ath_softc *sc)
2717{
2718        struct ath_tx_status ts;
2719        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2720        struct ath_hw *ah = sc->sc_ah;
2721        struct ath_txq *txq;
2722        struct ath_buf *bf, *lastbf;
2723        struct list_head bf_head;
2724        struct list_head *fifo_list;
2725        int status;
2726
2727        rcu_read_lock();
2728        for (;;) {
2729                if (test_bit(ATH_OP_HW_RESET, &common->op_flags))
2730                        break;
2731
2732                status = ath9k_hw_txprocdesc(ah, NULL, (void *)&ts);
2733                if (status == -EINPROGRESS)
2734                        break;
2735                if (status == -EIO) {
2736                        ath_dbg(common, XMIT, "Error processing tx status\n");
2737                        break;
2738                }
2739
2740                /* Process beacon completions separately */
2741                if (ts.qid == sc->beacon.beaconq) {
2742                        sc->beacon.tx_processed = true;
2743                        sc->beacon.tx_last = !(ts.ts_status & ATH9K_TXERR_MASK);
2744
2745                        if (ath9k_is_chanctx_enabled()) {
2746                                ath_chanctx_event(sc, NULL,
2747                                                  ATH_CHANCTX_EVENT_BEACON_SENT);
2748                        }
2749
2750                        ath9k_csa_update(sc);
2751                        continue;
2752                }
2753
2754                txq = &sc->tx.txq[ts.qid];
2755
2756                ath_txq_lock(sc, txq);
2757
2758                TX_STAT_INC(txq->axq_qnum, txprocdesc);
2759
2760                fifo_list = &txq->txq_fifo[txq->txq_tailidx];
2761                if (list_empty(fifo_list)) {
2762                        ath_txq_unlock(sc, txq);
2763                        break;
2764                }
2765
2766                bf = list_first_entry(fifo_list, struct ath_buf, list);
2767                if (bf->bf_state.stale) {
2768                        list_del(&bf->list);
2769                        ath_tx_return_buffer(sc, bf);
2770                        bf = list_first_entry(fifo_list, struct ath_buf, list);
2771                }
2772
2773                lastbf = bf->bf_lastbf;
2774
2775                INIT_LIST_HEAD(&bf_head);
2776                if (list_is_last(&lastbf->list, fifo_list)) {
2777                        list_splice_tail_init(fifo_list, &bf_head);
2778                        INCR(txq->txq_tailidx, ATH_TXFIFO_DEPTH);
2779
2780                        if (!list_empty(&txq->axq_q)) {
2781                                struct list_head bf_q;
2782
2783                                INIT_LIST_HEAD(&bf_q);
2784                                txq->axq_link = NULL;
2785                                list_splice_tail_init(&txq->axq_q, &bf_q);
2786                                ath_tx_txqaddbuf(sc, txq, &bf_q, true);
2787                        }
2788                } else {
2789                        lastbf->bf_state.stale = true;
2790                        if (bf != lastbf)
2791                                list_cut_position(&bf_head, fifo_list,
2792                                                  lastbf->list.prev);
2793                }
2794
2795                ath_tx_process_buffer(sc, txq, &ts, bf, &bf_head);
2796                ath_txq_unlock_complete(sc, txq);
2797        }
2798        rcu_read_unlock();
2799}
2800
2801/*****************/
2802/* Init, Cleanup */
2803/*****************/
2804
2805static int ath_txstatus_setup(struct ath_softc *sc, int size)
2806{
2807        struct ath_descdma *dd = &sc->txsdma;
2808        u8 txs_len = sc->sc_ah->caps.txs_len;
2809
2810        dd->dd_desc_len = size * txs_len;
2811        dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
2812                                          &dd->dd_desc_paddr, GFP_KERNEL);
2813        if (!dd->dd_desc)
2814                return -ENOMEM;
2815
2816        return 0;
2817}
2818
2819static int ath_tx_edma_init(struct ath_softc *sc)
2820{
2821        int err;
2822
2823        err = ath_txstatus_setup(sc, ATH_TXSTATUS_RING_SIZE);
2824        if (!err)
2825                ath9k_hw_setup_statusring(sc->sc_ah, sc->txsdma.dd_desc,
2826                                          sc->txsdma.dd_desc_paddr,
2827                                          ATH_TXSTATUS_RING_SIZE);
2828
2829        return err;
2830}
2831
2832int ath_tx_init(struct ath_softc *sc, int nbufs)
2833{
2834        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2835        int error = 0;
2836
2837        spin_lock_init(&sc->tx.txbuflock);
2838
2839        error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2840                                  "tx", nbufs, 1, 1);
2841        if (error != 0) {
2842                ath_err(common,
2843                        "Failed to allocate tx descriptors: %d\n", error);
2844                return error;
2845        }
2846
2847        error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2848                                  "beacon", ATH_BCBUF, 1, 1);
2849        if (error != 0) {
2850                ath_err(common,
2851                        "Failed to allocate beacon descriptors: %d\n", error);
2852                return error;
2853        }
2854
2855        if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
2856                error = ath_tx_edma_init(sc);
2857
2858        return error;
2859}
2860
2861void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
2862{
2863        struct ath_atx_tid *tid;
2864        int tidno, acno;
2865
2866        for (acno = 0; acno < IEEE80211_NUM_ACS; acno++)
2867                an->airtime_deficit[acno] = ATH_AIRTIME_QUANTUM;
2868
2869        for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
2870                tid = ath_node_to_tid(an, tidno);
2871                tid->an        = an;
2872                tid->tidno     = tidno;
2873                tid->seq_start = tid->seq_next = 0;
2874                tid->baw_size  = WME_MAX_BA;
2875                tid->baw_head  = tid->baw_tail = 0;
2876                tid->active        = false;
2877                tid->clear_ps_filter = true;
2878                tid->has_queued  = false;
2879                __skb_queue_head_init(&tid->retry_q);
2880                INIT_LIST_HEAD(&tid->list);
2881                acno = TID_TO_WME_AC(tidno);
2882                tid->txq = sc->tx.txq_map[acno];
2883
2884                if (!an->sta)
2885                        break; /* just one multicast ath_atx_tid */
2886        }
2887}
2888
2889void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
2890{
2891        struct ath_atx_tid *tid;
2892        struct ath_txq *txq;
2893        int tidno;
2894
2895        for (tidno = 0; tidno < IEEE80211_NUM_TIDS; tidno++) {
2896                tid = ath_node_to_tid(an, tidno);
2897                txq = tid->txq;
2898
2899                ath_txq_lock(sc, txq);
2900
2901                if (!list_empty(&tid->list))
2902                        list_del_init(&tid->list);
2903
2904                ath_tid_drain(sc, txq, tid);
2905                tid->active = false;
2906
2907                ath_txq_unlock(sc, txq);
2908
2909                if (!an->sta)
2910                        break; /* just one multicast ath_atx_tid */
2911        }
2912}
2913
2914#ifdef CONFIG_ATH9K_TX99
2915
2916int ath9k_tx99_send(struct ath_softc *sc, struct sk_buff *skb,
2917                    struct ath_tx_control *txctl)
2918{
2919        struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
2920        struct ath_frame_info *fi = get_frame_info(skb);
2921        struct ath_common *common = ath9k_hw_common(sc->sc_ah);
2922        struct ath_buf *bf;
2923        int padpos, padsize;
2924
2925        padpos = ieee80211_hdrlen(hdr->frame_control);
2926        padsize = padpos & 3;
2927
2928        if (padsize && skb->len > padpos) {
2929                if (skb_headroom(skb) < padsize) {
2930                        ath_dbg(common, XMIT,
2931                                "tx99 padding failed\n");
2932                        return -EINVAL;
2933                }
2934
2935                skb_push(skb, padsize);
2936                memmove(skb->data, skb->data + padsize, padpos);
2937        }
2938
2939        fi->keyix = ATH9K_TXKEYIX_INVALID;
2940        fi->framelen = skb->len + FCS_LEN;
2941        fi->keytype = ATH9K_KEY_TYPE_CLEAR;
2942
2943        bf = ath_tx_setup_buffer(sc, txctl->txq, NULL, skb);
2944        if (!bf) {
2945                ath_dbg(common, XMIT, "tx99 buffer setup failed\n");
2946                return -EINVAL;
2947        }
2948
2949        ath_set_rates(sc->tx99_vif, NULL, bf);
2950
2951        ath9k_hw_set_desc_link(sc->sc_ah, bf->bf_desc, bf->bf_daddr);
2952        ath9k_hw_tx99_start(sc->sc_ah, txctl->txq->axq_qnum);
2953
2954        ath_tx_send_normal(sc, txctl->txq, NULL, skb);
2955
2956        return 0;
2957}
2958
2959#endif /* CONFIG_ATH9K_TX99 */
2960