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26#ifndef __il_core_h__
27#define __il_core_h__
28
29#include <linux/interrupt.h>
30#include <linux/pci.h>
31#include <linux/kernel.h>
32#include <linux/leds.h>
33#include <linux/wait.h>
34#include <linux/io.h>
35#include <net/mac80211.h>
36#include <net/ieee80211_radiotap.h>
37
38#include "commands.h"
39#include "csr.h"
40#include "prph.h"
41
42struct il_host_cmd;
43struct il_cmd;
44struct il_tx_queue;
45
46#define IL_ERR(f, a...) dev_err(&il->pci_dev->dev, f, ## a)
47#define IL_WARN(f, a...) dev_warn(&il->pci_dev->dev, f, ## a)
48#define IL_WARN_ONCE(f, a...) dev_warn_once(&il->pci_dev->dev, f, ## a)
49#define IL_INFO(f, a...) dev_info(&il->pci_dev->dev, f, ## a)
50
51#define RX_QUEUE_SIZE 256
52#define RX_QUEUE_MASK 255
53#define RX_QUEUE_SIZE_LOG 8
54
55
56
57
58#define RX_FREE_BUFFERS 64
59#define RX_LOW_WATERMARK 8
60
61#define U32_PAD(n) ((4-(n))&0x3)
62
63
64#define CT_KILL_THRESHOLD_LEGACY 110
65
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75
76
77#define IL_NOISE_MEAS_NOT_AVAILABLE (-127)
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86
87#define DEFAULT_RTS_THRESHOLD 2347U
88#define MIN_RTS_THRESHOLD 0U
89#define MAX_RTS_THRESHOLD 2347U
90#define MAX_MSDU_SIZE 2304U
91#define MAX_MPDU_SIZE 2346U
92#define DEFAULT_BEACON_INTERVAL 100U
93#define DEFAULT_SHORT_RETRY_LIMIT 7U
94#define DEFAULT_LONG_RETRY_LIMIT 4U
95
96struct il_rx_buf {
97 dma_addr_t page_dma;
98 struct page *page;
99 struct list_head list;
100};
101
102#define rxb_addr(r) page_address(r->page)
103
104
105struct il_device_cmd;
106
107struct il_cmd_meta {
108
109 struct il_host_cmd *source;
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117 void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
118 struct il_rx_pkt *pkt);
119
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121
122 u32 flags;
123
124 DEFINE_DMA_UNMAP_ADDR(mapping);
125 DEFINE_DMA_UNMAP_LEN(len);
126};
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132
133struct il_queue {
134 int n_bd;
135 int write_ptr;
136 int read_ptr;
137
138 dma_addr_t dma_addr;
139 int n_win;
140 u32 id;
141 int low_mark;
142
143 int high_mark;
144
145};
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161
162#define TFD_TX_CMD_SLOTS 256
163#define TFD_CMD_SLOTS 32
164
165struct il_tx_queue {
166 struct il_queue q;
167 void *tfds;
168 struct il_device_cmd **cmd;
169 struct il_cmd_meta *meta;
170 struct sk_buff **skbs;
171 unsigned long time_stamp;
172 u8 need_update;
173 u8 sched_retry;
174 u8 active;
175 u8 swq_id;
176};
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185
186#define IL_EEPROM_ACCESS_TIMEOUT 5000
187
188#define IL_EEPROM_SEM_TIMEOUT 10
189#define IL_EEPROM_SEM_RETRY_LIMIT 1000
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206
207#define IL_NUM_TX_CALIB_GROUPS 5
208enum {
209 EEPROM_CHANNEL_VALID = (1 << 0),
210 EEPROM_CHANNEL_IBSS = (1 << 1),
211
212 EEPROM_CHANNEL_ACTIVE = (1 << 3),
213 EEPROM_CHANNEL_RADAR = (1 << 4),
214 EEPROM_CHANNEL_WIDE = (1 << 5),
215
216 EEPROM_CHANNEL_DFS = (1 << 7),
217};
218
219
220
221#define EEPROM_SKU_CAP_SW_RF_KILL_ENABLE (1 << 0)
222#define EEPROM_SKU_CAP_HW_RF_KILL_ENABLE (1 << 1)
223
224
225
226struct il_eeprom_channel {
227 u8 flags;
228 s8 max_power_avg;
229} __packed;
230
231
232#define EEPROM_3945_EEPROM_VERSION (0x2f)
233
234
235#define EEPROM_TX_POWER_TX_CHAINS (2)
236
237
238#define EEPROM_TX_POWER_BANDS (8)
239
240
241
242#define EEPROM_TX_POWER_MEASUREMENTS (3)
243
244
245
246#define EEPROM_4965_TX_POWER_VERSION (5)
247#define EEPROM_4965_EEPROM_VERSION (0x2f)
248#define EEPROM_4965_CALIB_VERSION_OFFSET (2*0xB6)
249#define EEPROM_4965_CALIB_TXPOWER_OFFSET (2*0xE8)
250#define EEPROM_4965_BOARD_REVISION (2*0x4F)
251#define EEPROM_4965_BOARD_PBA (2*0x56+1)
252
253
254extern const u8 il_eeprom_band_1[14];
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270struct il_eeprom_calib_measure {
271 u8 temperature;
272 u8 gain_idx;
273 u8 actual_pow;
274 s8 pa_det;
275} __packed;
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285struct il_eeprom_calib_ch_info {
286 u8 ch_num;
287 struct il_eeprom_calib_measure
288 measurements[EEPROM_TX_POWER_TX_CHAINS]
289 [EEPROM_TX_POWER_MEASUREMENTS];
290} __packed;
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301
302struct il_eeprom_calib_subband_info {
303 u8 ch_from;
304 u8 ch_to;
305 struct il_eeprom_calib_ch_info ch1;
306 struct il_eeprom_calib_ch_info ch2;
307} __packed;
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329struct il_eeprom_calib_info {
330 u8 saturation_power24;
331 u8 saturation_power52;
332 __le16 voltage;
333 struct il_eeprom_calib_subband_info band_info[EEPROM_TX_POWER_BANDS];
334} __packed;
335
336
337#define EEPROM_DEVICE_ID (2*0x08)
338#define EEPROM_MAC_ADDRESS (2*0x15)
339#define EEPROM_BOARD_REVISION (2*0x35)
340#define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1)
341#define EEPROM_VERSION (2*0x44)
342#define EEPROM_SKU_CAP (2*0x45)
343#define EEPROM_OEM_MODE (2*0x46)
344#define EEPROM_WOWLAN_MODE (2*0x47)
345#define EEPROM_RADIO_CONFIG (2*0x48)
346#define EEPROM_NUM_MAC_ADDRESS (2*0x4C)
347
348
349#define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3)
350#define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3)
351#define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3)
352#define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3)
353#define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF)
354#define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF)
355
356#define EEPROM_3945_RF_CFG_TYPE_MAX 0x0
357#define EEPROM_4965_RF_CFG_TYPE_MAX 0x1
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370
371#define EEPROM_REGULATORY_SKU_ID (2*0x60)
372#define EEPROM_REGULATORY_BAND_1 (2*0x62)
373#define EEPROM_REGULATORY_BAND_1_CHANNELS (2*0x63)
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380#define EEPROM_REGULATORY_BAND_2 (2*0x71)
381#define EEPROM_REGULATORY_BAND_2_CHANNELS (2*0x72)
382
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387#define EEPROM_REGULATORY_BAND_3 (2*0x7F)
388#define EEPROM_REGULATORY_BAND_3_CHANNELS (2*0x80)
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394#define EEPROM_REGULATORY_BAND_4 (2*0x8C)
395#define EEPROM_REGULATORY_BAND_4_CHANNELS (2*0x8D)
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401#define EEPROM_REGULATORY_BAND_5 (2*0x98)
402#define EEPROM_REGULATORY_BAND_5_CHANNELS (2*0x99)
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419#define EEPROM_4965_REGULATORY_BAND_24_HT40_CHANNELS (2*0xA0)
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425#define EEPROM_4965_REGULATORY_BAND_52_HT40_CHANNELS (2*0xA8)
426
427#define EEPROM_REGULATORY_BAND_NO_HT40 (0)
428
429int il_eeprom_init(struct il_priv *il);
430void il_eeprom_free(struct il_priv *il);
431const u8 *il_eeprom_query_addr(const struct il_priv *il, size_t offset);
432u16 il_eeprom_query16(const struct il_priv *il, size_t offset);
433int il_init_channel_map(struct il_priv *il);
434void il_free_channel_map(struct il_priv *il);
435const struct il_channel_info *il_get_channel_info(const struct il_priv *il,
436 enum nl80211_band band,
437 u16 channel);
438
439#define IL_NUM_SCAN_RATES (2)
440
441struct il4965_channel_tgd_info {
442 u8 type;
443 s8 max_power;
444};
445
446struct il4965_channel_tgh_info {
447 s64 last_radar_time;
448};
449
450#define IL4965_MAX_RATE (33)
451
452struct il3945_clip_group {
453
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455 const s8 clip_powers[IL_MAX_RATES];
456};
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465struct il3945_channel_power_info {
466 struct il3945_tx_power tpc;
467 s8 power_table_idx;
468 s8 base_power_idx;
469 s8 requested_power;
470};
471
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474struct il3945_scan_power_info {
475 struct il3945_tx_power tpc;
476 s8 power_table_idx;
477 s8 requested_power;
478};
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485struct il_channel_info {
486 struct il4965_channel_tgd_info tgd;
487 struct il4965_channel_tgh_info tgh;
488 struct il_eeprom_channel eeprom;
489 struct il_eeprom_channel ht40_eeprom;
490
491
492 u8 channel;
493 u8 flags;
494 s8 max_power_avg;
495 s8 curr_txpow;
496 s8 min_power;
497 s8 scan_power;
498
499 u8 group_idx;
500 u8 band_idx;
501 enum nl80211_band band;
502
503
504 s8 ht40_max_power_avg;
505 u8 ht40_flags;
506 u8 ht40_extension_channel;
507
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510
511 struct il3945_channel_power_info power_info[IL4965_MAX_RATE];
512
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514 struct il3945_scan_power_info scan_pwr_info[IL_NUM_SCAN_RATES];
515};
516
517#define IL_TX_FIFO_BK 0
518#define IL_TX_FIFO_BE 1
519#define IL_TX_FIFO_VI 2
520#define IL_TX_FIFO_VO 3
521#define IL_TX_FIFO_UNUSED -1
522
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525
526#define IL_MIN_NUM_QUEUES 10
527
528#define IL_DEFAULT_CMD_QUEUE_NUM 4
529
530#define IEEE80211_DATA_LEN 2304
531#define IEEE80211_4ADDR_LEN 30
532#define IEEE80211_HLEN (IEEE80211_4ADDR_LEN)
533#define IEEE80211_FRAME_LEN (IEEE80211_DATA_LEN + IEEE80211_HLEN)
534
535struct il_frame {
536 union {
537 struct ieee80211_hdr frame;
538 struct il_tx_beacon_cmd beacon;
539 u8 raw[IEEE80211_FRAME_LEN];
540 u8 cmd[360];
541 } u;
542 struct list_head list;
543};
544
545enum {
546 CMD_SYNC = 0,
547 CMD_SIZE_NORMAL = 0,
548 CMD_NO_SKB = 0,
549 CMD_SIZE_HUGE = (1 << 0),
550 CMD_ASYNC = (1 << 1),
551 CMD_WANT_SKB = (1 << 2),
552 CMD_MAPPED = (1 << 3),
553};
554
555#define DEF_CMD_PAYLOAD_SIZE 320
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564struct il_device_cmd {
565 struct il_cmd_header hdr;
566 union {
567 u32 flags;
568 u8 val8;
569 u16 val16;
570 u32 val32;
571 struct il_tx_cmd tx;
572 u8 payload[DEF_CMD_PAYLOAD_SIZE];
573 } __packed cmd;
574} __packed;
575
576#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct il_device_cmd))
577
578struct il_host_cmd {
579 const void *data;
580 unsigned long reply_page;
581 void (*callback) (struct il_priv *il, struct il_device_cmd *cmd,
582 struct il_rx_pkt *pkt);
583 u32 flags;
584 u16 len;
585 u8 id;
586};
587
588#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
589#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
590#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
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607struct il_rx_queue {
608 __le32 *bd;
609 dma_addr_t bd_dma;
610 struct il_rx_buf pool[RX_QUEUE_SIZE + RX_FREE_BUFFERS];
611 struct il_rx_buf *queue[RX_QUEUE_SIZE];
612 u32 read;
613 u32 write;
614 u32 free_count;
615 u32 write_actual;
616 struct list_head rx_free;
617 struct list_head rx_used;
618 int need_update;
619 struct il_rb_status *rb_stts;
620 dma_addr_t rb_stts_dma;
621 spinlock_t lock;
622};
623
624#define IL_SUPPORTED_RATES_IE_LEN 8
625
626#define MAX_TID_COUNT 9
627
628#define IL_INVALID_RATE 0xFF
629#define IL_INVALID_VALUE -1
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645struct il_ht_agg {
646 u16 txq_id;
647 u16 frame_count;
648 u16 wait_for_ba;
649 u16 start_idx;
650 u64 bitmap;
651 u32 rate_n_flags;
652#define IL_AGG_OFF 0
653#define IL_AGG_ON 1
654#define IL_EMPTYING_HW_QUEUE_ADDBA 2
655#define IL_EMPTYING_HW_QUEUE_DELBA 3
656 u8 state;
657};
658
659struct il_tid_data {
660 u16 seq_number;
661 u16 tfds_in_queue;
662 struct il_ht_agg agg;
663};
664
665struct il_hw_key {
666 u32 cipher;
667 int keylen;
668 u8 keyidx;
669 u8 key[32];
670};
671
672union il_ht_rate_supp {
673 u16 rates;
674 struct {
675 u8 siso_rate;
676 u8 mimo_rate;
677 };
678};
679
680#define CFG_HT_RX_AMPDU_FACTOR_8K (0x0)
681#define CFG_HT_RX_AMPDU_FACTOR_16K (0x1)
682#define CFG_HT_RX_AMPDU_FACTOR_32K (0x2)
683#define CFG_HT_RX_AMPDU_FACTOR_64K (0x3)
684#define CFG_HT_RX_AMPDU_FACTOR_DEF CFG_HT_RX_AMPDU_FACTOR_64K
685#define CFG_HT_RX_AMPDU_FACTOR_MAX CFG_HT_RX_AMPDU_FACTOR_64K
686#define CFG_HT_RX_AMPDU_FACTOR_MIN CFG_HT_RX_AMPDU_FACTOR_8K
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695#define CFG_HT_MPDU_DENSITY_2USEC (0x4)
696#define CFG_HT_MPDU_DENSITY_4USEC (0x5)
697#define CFG_HT_MPDU_DENSITY_8USEC (0x6)
698#define CFG_HT_MPDU_DENSITY_16USEC (0x7)
699#define CFG_HT_MPDU_DENSITY_DEF CFG_HT_MPDU_DENSITY_4USEC
700#define CFG_HT_MPDU_DENSITY_MAX CFG_HT_MPDU_DENSITY_16USEC
701#define CFG_HT_MPDU_DENSITY_MIN (0x1)
702
703struct il_ht_config {
704 bool single_chain_sufficient;
705 enum ieee80211_smps_mode smps;
706};
707
708
709struct il_qos_info {
710 int qos_active;
711 struct il_qosparam_cmd def_qos_parm;
712};
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719
720struct il_station_entry {
721 struct il_addsta_cmd sta;
722 struct il_tid_data tid[MAX_TID_COUNT];
723 u8 used;
724 struct il_hw_key keyinfo;
725 struct il_link_quality_cmd *lq;
726};
727
728struct il_station_priv_common {
729 u8 sta_id;
730};
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738struct il_vif_priv {
739 u8 ibss_bssid_sta_id;
740};
741
742
743struct fw_desc {
744 void *v_addr;
745 dma_addr_t p_addr;
746 u32 len;
747};
748
749
750struct il_ucode_header {
751 __le32 ver;
752 struct {
753 __le32 inst_size;
754 __le32 data_size;
755 __le32 init_size;
756 __le32 init_data_size;
757 __le32 boot_size;
758 u8 data[0];
759 } v1;
760};
761
762struct il4965_ibss_seq {
763 u8 mac[ETH_ALEN];
764 u16 seq_num;
765 u16 frag_num;
766 unsigned long packet_time;
767 struct list_head list;
768};
769
770struct il_sensitivity_ranges {
771 u16 min_nrg_cck;
772 u16 max_nrg_cck;
773
774 u16 nrg_th_cck;
775 u16 nrg_th_ofdm;
776
777 u16 auto_corr_min_ofdm;
778 u16 auto_corr_min_ofdm_mrc;
779 u16 auto_corr_min_ofdm_x1;
780 u16 auto_corr_min_ofdm_mrc_x1;
781
782 u16 auto_corr_max_ofdm;
783 u16 auto_corr_max_ofdm_mrc;
784 u16 auto_corr_max_ofdm_x1;
785 u16 auto_corr_max_ofdm_mrc_x1;
786
787 u16 auto_corr_max_cck;
788 u16 auto_corr_max_cck_mrc;
789 u16 auto_corr_min_cck;
790 u16 auto_corr_min_cck_mrc;
791
792 u16 barker_corr_th_min;
793 u16 barker_corr_th_min_mrc;
794 u16 nrg_th_cca;
795};
796
797#define KELVIN_TO_CELSIUS(x) ((x)-273)
798#define CELSIUS_TO_KELVIN(x) ((x)+273)
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822struct il_hw_params {
823 u8 bcast_id;
824 u8 max_txq_num;
825 u8 dma_chnl_num;
826 u16 scd_bc_tbls_size;
827 u32 tfd_size;
828 u8 tx_chains_num;
829 u8 rx_chains_num;
830 u8 valid_tx_ant;
831 u8 valid_rx_ant;
832 u16 max_rxq_size;
833 u16 max_rxq_log;
834 u32 rx_page_order;
835 u32 rx_wrt_ptr_reg;
836 u8 max_stations;
837 u8 ht40_channel;
838 u8 max_beacon_itrvl;
839 u32 max_inst_size;
840 u32 max_data_size;
841 u32 max_bsm_size;
842 u32 ct_kill_threshold;
843 u16 beacon_time_tsf_bits;
844 const struct il_sensitivity_ranges *sens;
845};
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862void il4965_update_chain_flags(struct il_priv *il);
863extern const u8 il_bcast_addr[ETH_ALEN];
864int il_queue_space(const struct il_queue *q);
865static inline int
866il_queue_used(const struct il_queue *q, int i)
867{
868 return q->write_ptr >= q->read_ptr ? (i >= q->read_ptr &&
869 i < q->write_ptr) : !(i <
870 q->read_ptr
871 && i >=
872 q->
873 write_ptr);
874}
875
876static inline u8
877il_get_cmd_idx(struct il_queue *q, u32 idx, int is_huge)
878{
879
880
881
882
883
884 if (is_huge)
885 return q->n_win;
886
887
888 return idx & (q->n_win - 1);
889}
890
891struct il_dma_ptr {
892 dma_addr_t dma;
893 void *addr;
894 size_t size;
895};
896
897#define IL_OPERATION_MODE_AUTO 0
898#define IL_OPERATION_MODE_HT_ONLY 1
899#define IL_OPERATION_MODE_MIXED 2
900#define IL_OPERATION_MODE_20MHZ 3
901
902#define IL_TX_CRC_SIZE 4
903#define IL_TX_DELIMITER_SIZE 4
904
905#define TX_POWER_IL_ILLEGAL_VOLTAGE -10000
906
907
908#define INITIALIZATION_VALUE 0xFFFF
909#define IL4965_CAL_NUM_BEACONS 20
910#define IL_CAL_NUM_BEACONS 16
911#define MAXIMUM_ALLOWED_PATHLOSS 15
912
913#define CHAIN_NOISE_MAX_DELTA_GAIN_CODE 3
914
915#define MAX_FA_OFDM 50
916#define MIN_FA_OFDM 5
917#define MAX_FA_CCK 50
918#define MIN_FA_CCK 5
919
920#define AUTO_CORR_STEP_OFDM 1
921
922#define AUTO_CORR_STEP_CCK 3
923#define AUTO_CORR_MAX_TH_CCK 160
924
925#define NRG_DIFF 2
926#define NRG_STEP_CCK 2
927#define NRG_MARGIN 8
928#define MAX_NUMBER_CCK_NO_FA 100
929
930#define AUTO_CORR_CCK_MIN_VAL_DEF (125)
931
932#define CHAIN_A 0
933#define CHAIN_B 1
934#define CHAIN_C 2
935#define CHAIN_NOISE_DELTA_GAIN_INIT_VAL 4
936#define ALL_BAND_FILTER 0xFF00
937#define IN_BAND_FILTER 0xFF
938#define MIN_AVERAGE_NOISE_MAX_VALUE 0xFFFFFFFF
939
940#define NRG_NUM_PREV_STAT_L 20
941#define NUM_RX_CHAINS 3
942
943enum il4965_false_alarm_state {
944 IL_FA_TOO_MANY = 0,
945 IL_FA_TOO_FEW = 1,
946 IL_FA_GOOD_RANGE = 2,
947};
948
949enum il4965_chain_noise_state {
950 IL_CHAIN_NOISE_ALIVE = 0,
951 IL_CHAIN_NOISE_ACCUMULATE,
952 IL_CHAIN_NOISE_CALIBRATED,
953 IL_CHAIN_NOISE_DONE,
954};
955
956enum ucode_type {
957 UCODE_NONE = 0,
958 UCODE_INIT,
959 UCODE_RT
960};
961
962
963struct il_sensitivity_data {
964 u32 auto_corr_ofdm;
965 u32 auto_corr_ofdm_mrc;
966 u32 auto_corr_ofdm_x1;
967 u32 auto_corr_ofdm_mrc_x1;
968 u32 auto_corr_cck;
969 u32 auto_corr_cck_mrc;
970
971 u32 last_bad_plcp_cnt_ofdm;
972 u32 last_fa_cnt_ofdm;
973 u32 last_bad_plcp_cnt_cck;
974 u32 last_fa_cnt_cck;
975
976 u32 nrg_curr_state;
977 u32 nrg_prev_state;
978 u32 nrg_value[10];
979 u8 nrg_silence_rssi[NRG_NUM_PREV_STAT_L];
980 u32 nrg_silence_ref;
981 u32 nrg_energy_idx;
982 u32 nrg_silence_idx;
983 u32 nrg_th_cck;
984 s32 nrg_auto_corr_silence_diff;
985 u32 num_in_cck_no_fa;
986 u32 nrg_th_ofdm;
987
988 u16 barker_corr_th_min;
989 u16 barker_corr_th_min_mrc;
990 u16 nrg_th_cca;
991};
992
993
994struct il_chain_noise_data {
995 u32 active_chains;
996 u32 chain_noise_a;
997 u32 chain_noise_b;
998 u32 chain_noise_c;
999 u32 chain_signal_a;
1000 u32 chain_signal_b;
1001 u32 chain_signal_c;
1002 u16 beacon_count;
1003 u8 disconn_array[NUM_RX_CHAINS];
1004 u8 delta_gain_code[NUM_RX_CHAINS];
1005 u8 radio_write;
1006 u8 state;
1007};
1008
1009#define EEPROM_SEM_TIMEOUT 10
1010#define EEPROM_SEM_RETRY_LIMIT 1000
1011
1012#define IL_TRAFFIC_ENTRIES (256)
1013#define IL_TRAFFIC_ENTRY_SIZE (64)
1014
1015enum {
1016 MEASUREMENT_READY = (1 << 0),
1017 MEASUREMENT_ACTIVE = (1 << 1),
1018};
1019
1020
1021struct isr_stats {
1022 u32 hw;
1023 u32 sw;
1024 u32 err_code;
1025 u32 sch;
1026 u32 alive;
1027 u32 rfkill;
1028 u32 ctkill;
1029 u32 wakeup;
1030 u32 rx;
1031 u32 handlers[IL_CN_MAX];
1032 u32 tx;
1033 u32 unhandled;
1034};
1035
1036
1037enum il_mgmt_stats {
1038 MANAGEMENT_ASSOC_REQ = 0,
1039 MANAGEMENT_ASSOC_RESP,
1040 MANAGEMENT_REASSOC_REQ,
1041 MANAGEMENT_REASSOC_RESP,
1042 MANAGEMENT_PROBE_REQ,
1043 MANAGEMENT_PROBE_RESP,
1044 MANAGEMENT_BEACON,
1045 MANAGEMENT_ATIM,
1046 MANAGEMENT_DISASSOC,
1047 MANAGEMENT_AUTH,
1048 MANAGEMENT_DEAUTH,
1049 MANAGEMENT_ACTION,
1050 MANAGEMENT_MAX,
1051};
1052
1053enum il_ctrl_stats {
1054 CONTROL_BACK_REQ = 0,
1055 CONTROL_BACK,
1056 CONTROL_PSPOLL,
1057 CONTROL_RTS,
1058 CONTROL_CTS,
1059 CONTROL_ACK,
1060 CONTROL_CFEND,
1061 CONTROL_CFENDACK,
1062 CONTROL_MAX,
1063};
1064
1065struct traffic_stats {
1066#ifdef CONFIG_IWLEGACY_DEBUGFS
1067 u32 mgmt[MANAGEMENT_MAX];
1068 u32 ctrl[CONTROL_MAX];
1069 u32 data_cnt;
1070 u64 data_bytes;
1071#endif
1072};
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082#define IL_HOST_INT_TIMEOUT_MAX (0xFF)
1083#define IL_HOST_INT_TIMEOUT_DEF (0x40)
1084#define IL_HOST_INT_TIMEOUT_MIN (0x0)
1085#define IL_HOST_INT_CALIB_TIMEOUT_MAX (0xFF)
1086#define IL_HOST_INT_CALIB_TIMEOUT_DEF (0x10)
1087#define IL_HOST_INT_CALIB_TIMEOUT_MIN (0x0)
1088
1089#define IL_DELAY_NEXT_FORCE_FW_RELOAD (HZ*5)
1090
1091
1092#define IL_DEF_WD_TIMEOUT (2000)
1093#define IL_LONG_WD_TIMEOUT (10000)
1094#define IL_MAX_WD_TIMEOUT (120000)
1095
1096struct il_force_reset {
1097 int reset_request_count;
1098 int reset_success_count;
1099 int reset_reject_count;
1100 unsigned long reset_duration;
1101 unsigned long last_force_reset_jiffies;
1102};
1103
1104
1105
1106
1107
1108
1109
1110#define IL3945_EXT_BEACON_TIME_POS 24
1111
1112
1113
1114
1115
1116#define IL4965_EXT_BEACON_TIME_POS 22
1117
1118struct il_rxon_context {
1119 struct ieee80211_vif *vif;
1120};
1121
1122struct il_power_mgr {
1123 struct il_powertable_cmd sleep_cmd;
1124 struct il_powertable_cmd sleep_cmd_next;
1125 int debug_sleep_level_override;
1126 bool pci_pm;
1127 bool ps_disabled;
1128};
1129
1130struct il_priv {
1131 struct ieee80211_hw *hw;
1132 struct ieee80211_channel *ieee_channels;
1133 struct ieee80211_rate *ieee_rates;
1134
1135 struct il_cfg *cfg;
1136 const struct il_ops *ops;
1137#ifdef CONFIG_IWLEGACY_DEBUGFS
1138 const struct il_debugfs_ops *debugfs_ops;
1139#endif
1140
1141
1142 struct list_head free_frames;
1143 int frames_count;
1144
1145 enum nl80211_band band;
1146 int alloc_rxb_page;
1147
1148 void (*handlers[IL_CN_MAX]) (struct il_priv *il,
1149 struct il_rx_buf *rxb);
1150
1151 struct ieee80211_supported_band bands[NUM_NL80211_BANDS];
1152
1153
1154 struct il_spectrum_notification measure_report;
1155 u8 measurement_status;
1156
1157
1158 u32 ucode_beacon_time;
1159 int missed_beacon_threshold;
1160
1161
1162 u32 ibss_manager;
1163
1164
1165 struct il_force_reset force_reset;
1166
1167
1168
1169 struct il_channel_info *channel_info;
1170 u8 channel_count;
1171
1172
1173 s32 temperature;
1174 s32 last_temperature;
1175
1176
1177 unsigned long scan_start;
1178 unsigned long scan_start_tsf;
1179 void *scan_cmd;
1180 enum nl80211_band scan_band;
1181 struct cfg80211_scan_request *scan_request;
1182 struct ieee80211_vif *scan_vif;
1183 u8 scan_tx_ant[NUM_NL80211_BANDS];
1184 u8 mgmt_tx_ant;
1185
1186
1187 spinlock_t lock;
1188 spinlock_t hcmd_lock;
1189 spinlock_t reg_lock;
1190 struct mutex mutex;
1191
1192
1193 struct pci_dev *pci_dev;
1194
1195
1196 void __iomem *hw_base;
1197 u32 hw_rev;
1198 u32 hw_wa_rev;
1199 u8 rev_id;
1200
1201
1202 u8 cmd_queue;
1203
1204
1205 u8 sta_key_max_num;
1206
1207
1208 struct mac_address addresses[1];
1209
1210
1211 int fw_idx;
1212 u32 ucode_ver;
1213
1214 struct fw_desc ucode_code;
1215 struct fw_desc ucode_data;
1216 struct fw_desc ucode_data_backup;
1217 struct fw_desc ucode_init;
1218 struct fw_desc ucode_init_data;
1219 struct fw_desc ucode_boot;
1220 enum ucode_type ucode_type;
1221 u8 ucode_write_complete;
1222 char firmware_name[25];
1223
1224 struct ieee80211_vif *vif;
1225
1226 struct il_qos_info qos_data;
1227
1228 struct {
1229 bool enabled;
1230 bool is_40mhz;
1231 bool non_gf_sta_present;
1232 u8 protection;
1233 u8 extension_chan_offset;
1234 } ht;
1235
1236
1237
1238
1239
1240
1241
1242 const struct il_rxon_cmd active;
1243 struct il_rxon_cmd staging;
1244
1245 struct il_rxon_time_cmd timing;
1246
1247 __le16 switch_channel;
1248
1249
1250
1251 struct il_init_alive_resp card_alive_init;
1252 struct il_alive_resp card_alive;
1253
1254 u16 active_rate;
1255
1256 u8 start_calib;
1257 struct il_sensitivity_data sensitivity_data;
1258 struct il_chain_noise_data chain_noise_data;
1259 __le16 sensitivity_tbl[HD_TBL_SIZE];
1260
1261 struct il_ht_config current_ht_config;
1262
1263
1264 u8 retry_rate;
1265
1266 wait_queue_head_t wait_command_queue;
1267
1268 int activity_timer_active;
1269
1270
1271 struct il_rx_queue rxq;
1272 struct il_tx_queue *txq;
1273 unsigned long txq_ctx_active_msk;
1274 struct il_dma_ptr kw;
1275 struct il_dma_ptr scd_bc_tbls;
1276
1277 u32 scd_base_addr;
1278
1279 unsigned long status;
1280
1281
1282 struct traffic_stats tx_stats;
1283 struct traffic_stats rx_stats;
1284
1285
1286 struct isr_stats isr_stats;
1287
1288 struct il_power_mgr power_data;
1289
1290
1291 u8 bssid[ETH_ALEN];
1292
1293
1294
1295
1296 spinlock_t sta_lock;
1297 int num_stations;
1298 struct il_station_entry stations[IL_STATION_COUNT];
1299 unsigned long ucode_key_table;
1300
1301
1302#define IL_MAX_HW_QUEUES 32
1303 unsigned long queue_stopped[BITS_TO_LONGS(IL_MAX_HW_QUEUES)];
1304#define IL_STOP_REASON_PASSIVE 0
1305 unsigned long stop_reason;
1306
1307 atomic_t queue_stop_count[4];
1308
1309
1310 u8 is_open;
1311
1312 u8 mac80211_registered;
1313
1314
1315 u8 *eeprom;
1316 struct il_eeprom_calib_info *calib_info;
1317
1318 enum nl80211_iftype iw_mode;
1319
1320
1321 u64 timestamp;
1322
1323 union {
1324#if IS_ENABLED(CONFIG_IWL3945)
1325 struct {
1326 void *shared_virt;
1327 dma_addr_t shared_phys;
1328
1329 struct delayed_work thermal_periodic;
1330 struct delayed_work rfkill_poll;
1331
1332 struct il3945_notif_stats stats;
1333#ifdef CONFIG_IWLEGACY_DEBUGFS
1334 struct il3945_notif_stats accum_stats;
1335 struct il3945_notif_stats delta_stats;
1336 struct il3945_notif_stats max_delta;
1337#endif
1338
1339 u32 sta_supp_rates;
1340 int last_rx_rssi;
1341
1342
1343 u32 last_beacon_time;
1344 u64 last_tsf;
1345
1346
1347
1348
1349
1350
1351 const struct il3945_clip_group clip_groups[5];
1352
1353 } _3945;
1354#endif
1355#if IS_ENABLED(CONFIG_IWL4965)
1356 struct {
1357 struct il_rx_phy_res last_phy_res;
1358 bool last_phy_res_valid;
1359 u32 ampdu_ref;
1360
1361 struct completion firmware_loading_complete;
1362
1363
1364
1365
1366
1367
1368 u8 phy_calib_chain_noise_reset_cmd;
1369 u8 phy_calib_chain_noise_gain_cmd;
1370
1371 u8 key_mapping_keys;
1372 struct il_wep_key wep_keys[WEP_KEYS_MAX];
1373
1374 struct il_notif_stats stats;
1375#ifdef CONFIG_IWLEGACY_DEBUGFS
1376 struct il_notif_stats accum_stats;
1377 struct il_notif_stats delta_stats;
1378 struct il_notif_stats max_delta;
1379#endif
1380
1381 } _4965;
1382#endif
1383 };
1384
1385 struct il_hw_params hw_params;
1386
1387 u32 inta_mask;
1388
1389 struct workqueue_struct *workqueue;
1390
1391 struct work_struct restart;
1392 struct work_struct scan_completed;
1393 struct work_struct rx_replenish;
1394 struct work_struct abort_scan;
1395
1396 bool beacon_enabled;
1397 struct sk_buff *beacon_skb;
1398
1399 struct work_struct tx_flush;
1400
1401 struct tasklet_struct irq_tasklet;
1402
1403 struct delayed_work init_alive_start;
1404 struct delayed_work alive_start;
1405 struct delayed_work scan_check;
1406
1407
1408 s8 tx_power_user_lmt;
1409 s8 tx_power_device_lmt;
1410 s8 tx_power_next;
1411
1412#ifdef CONFIG_IWLEGACY_DEBUG
1413
1414 u32 debug_level;
1415
1416#endif
1417#ifdef CONFIG_IWLEGACY_DEBUGFS
1418
1419 u16 tx_traffic_idx;
1420 u16 rx_traffic_idx;
1421 u8 *tx_traffic;
1422 u8 *rx_traffic;
1423 struct dentry *debugfs_dir;
1424 u32 dbgfs_sram_offset, dbgfs_sram_len;
1425 bool disable_ht40;
1426#endif
1427
1428 struct work_struct txpower_work;
1429 bool disable_sens_cal;
1430 bool disable_chain_noise_cal;
1431 bool disable_tx_power_cal;
1432 struct work_struct run_time_calib_work;
1433 struct timer_list stats_periodic;
1434 struct timer_list watchdog;
1435 bool hw_ready;
1436
1437 struct led_classdev led;
1438 unsigned long blink_on, blink_off;
1439 bool led_registered;
1440};
1441
1442static inline void
1443il_txq_ctx_activate(struct il_priv *il, int txq_id)
1444{
1445 set_bit(txq_id, &il->txq_ctx_active_msk);
1446}
1447
1448static inline void
1449il_txq_ctx_deactivate(struct il_priv *il, int txq_id)
1450{
1451 clear_bit(txq_id, &il->txq_ctx_active_msk);
1452}
1453
1454static inline int
1455il_is_associated(struct il_priv *il)
1456{
1457 return (il->active.filter_flags & RXON_FILTER_ASSOC_MSK) ? 1 : 0;
1458}
1459
1460static inline int
1461il_is_any_associated(struct il_priv *il)
1462{
1463 return il_is_associated(il);
1464}
1465
1466static inline int
1467il_is_channel_valid(const struct il_channel_info *ch_info)
1468{
1469 if (ch_info == NULL)
1470 return 0;
1471 return (ch_info->flags & EEPROM_CHANNEL_VALID) ? 1 : 0;
1472}
1473
1474static inline int
1475il_is_channel_radar(const struct il_channel_info *ch_info)
1476{
1477 return (ch_info->flags & EEPROM_CHANNEL_RADAR) ? 1 : 0;
1478}
1479
1480static inline u8
1481il_is_channel_a_band(const struct il_channel_info *ch_info)
1482{
1483 return ch_info->band == NL80211_BAND_5GHZ;
1484}
1485
1486static inline int
1487il_is_channel_passive(const struct il_channel_info *ch)
1488{
1489 return (!(ch->flags & EEPROM_CHANNEL_ACTIVE)) ? 1 : 0;
1490}
1491
1492static inline int
1493il_is_channel_ibss(const struct il_channel_info *ch)
1494{
1495 return (ch->flags & EEPROM_CHANNEL_IBSS) ? 1 : 0;
1496}
1497
1498static inline void
1499__il_free_pages(struct il_priv *il, struct page *page)
1500{
1501 __free_pages(page, il->hw_params.rx_page_order);
1502 il->alloc_rxb_page--;
1503}
1504
1505static inline void
1506il_free_pages(struct il_priv *il, unsigned long page)
1507{
1508 free_pages(page, il->hw_params.rx_page_order);
1509 il->alloc_rxb_page--;
1510}
1511
1512#define IWLWIFI_VERSION "in-tree:"
1513#define DRV_COPYRIGHT "Copyright(c) 2003-2011 Intel Corporation"
1514#define DRV_AUTHOR "<ilw@linux.intel.com>"
1515
1516#define IL_PCI_DEVICE(dev, subdev, cfg) \
1517 .vendor = PCI_VENDOR_ID_INTEL, .device = (dev), \
1518 .subvendor = PCI_ANY_ID, .subdevice = (subdev), \
1519 .driver_data = (kernel_ulong_t)&(cfg)
1520
1521#define TIME_UNIT 1024
1522
1523#define IL_SKU_G 0x1
1524#define IL_SKU_A 0x2
1525#define IL_SKU_N 0x8
1526
1527#define IL_CMD(x) case x: return #x
1528
1529
1530#define IL_RX_BUF_SIZE_3K (3 * 1000)
1531#define IL_RX_BUF_SIZE_4K (4 * 1024)
1532#define IL_RX_BUF_SIZE_8K (8 * 1024)
1533
1534#ifdef CONFIG_IWLEGACY_DEBUGFS
1535struct il_debugfs_ops {
1536 ssize_t(*rx_stats_read) (struct file *file, char __user *user_buf,
1537 size_t count, loff_t *ppos);
1538 ssize_t(*tx_stats_read) (struct file *file, char __user *user_buf,
1539 size_t count, loff_t *ppos);
1540 ssize_t(*general_stats_read) (struct file *file,
1541 char __user *user_buf, size_t count,
1542 loff_t *ppos);
1543};
1544#endif
1545
1546struct il_ops {
1547
1548 void (*txq_update_byte_cnt_tbl) (struct il_priv *il,
1549 struct il_tx_queue *txq,
1550 u16 byte_cnt);
1551 int (*txq_attach_buf_to_tfd) (struct il_priv *il,
1552 struct il_tx_queue *txq, dma_addr_t addr,
1553 u16 len, u8 reset, u8 pad);
1554 void (*txq_free_tfd) (struct il_priv *il, struct il_tx_queue *txq);
1555 int (*txq_init) (struct il_priv *il, struct il_tx_queue *txq);
1556
1557 void (*init_alive_start) (struct il_priv *il);
1558
1559 int (*is_valid_rtc_data_addr) (u32 addr);
1560
1561 int (*load_ucode) (struct il_priv *il);
1562
1563 void (*dump_nic_error_log) (struct il_priv *il);
1564 int (*dump_fh) (struct il_priv *il, char **buf, bool display);
1565 int (*set_channel_switch) (struct il_priv *il,
1566 struct ieee80211_channel_switch *ch_switch);
1567
1568 int (*apm_init) (struct il_priv *il);
1569
1570
1571 int (*send_tx_power) (struct il_priv *il);
1572 void (*update_chain_flags) (struct il_priv *il);
1573
1574
1575 int (*eeprom_acquire_semaphore) (struct il_priv *il);
1576 void (*eeprom_release_semaphore) (struct il_priv *il);
1577
1578 int (*rxon_assoc) (struct il_priv *il);
1579 int (*commit_rxon) (struct il_priv *il);
1580 void (*set_rxon_chain) (struct il_priv *il);
1581
1582 u16(*get_hcmd_size) (u8 cmd_id, u16 len);
1583 u16(*build_addsta_hcmd) (const struct il_addsta_cmd *cmd, u8 *data);
1584
1585 int (*request_scan) (struct il_priv *il, struct ieee80211_vif *vif);
1586 void (*post_scan) (struct il_priv *il);
1587 void (*post_associate) (struct il_priv *il);
1588 void (*config_ap) (struct il_priv *il);
1589
1590 int (*update_bcast_stations) (struct il_priv *il);
1591 int (*manage_ibss_station) (struct il_priv *il,
1592 struct ieee80211_vif *vif, bool add);
1593
1594 int (*send_led_cmd) (struct il_priv *il, struct il_led_cmd *led_cmd);
1595};
1596
1597struct il_mod_params {
1598 int sw_crypto;
1599 int disable_hw_scan;
1600 int num_of_queues;
1601 int disable_11n;
1602 int amsdu_size_8K;
1603 int antenna;
1604 int restart_fw;
1605};
1606
1607#define IL_LED_SOLID 11
1608#define IL_DEF_LED_INTRVL cpu_to_le32(1000)
1609
1610#define IL_LED_ACTIVITY (0<<1)
1611#define IL_LED_LINK (1<<1)
1612
1613
1614
1615
1616
1617
1618
1619
1620
1621enum il_led_mode {
1622 IL_LED_DEFAULT,
1623 IL_LED_RF_STATE,
1624 IL_LED_BLINK,
1625};
1626
1627void il_leds_init(struct il_priv *il);
1628void il_leds_exit(struct il_priv *il);
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638
1639
1640
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650
1651
1652
1653
1654
1655
1656
1657
1658
1659
1660
1661struct il_cfg {
1662
1663 const char *name;
1664 const char *fw_name_pre;
1665 const unsigned int ucode_api_max;
1666 const unsigned int ucode_api_min;
1667 u8 valid_tx_ant;
1668 u8 valid_rx_ant;
1669 unsigned int sku;
1670 u16 eeprom_ver;
1671 u16 eeprom_calib_ver;
1672
1673 const struct il_mod_params *mod_params;
1674
1675 struct il_base_params *base_params;
1676
1677 u8 scan_rx_antennas[NUM_NL80211_BANDS];
1678 enum il_led_mode led_mode;
1679
1680 int eeprom_size;
1681 int num_of_queues;
1682 int num_of_ampdu_queues;
1683
1684 u32 pll_cfg_val;
1685 bool set_l0s;
1686 bool use_bsm;
1687
1688 u16 led_compensation;
1689 int chain_noise_num_beacons;
1690 unsigned int wd_timeout;
1691 bool temperature_kelvin;
1692 const bool ucode_tracing;
1693 const bool sensitivity_calib_by_driver;
1694 const bool chain_noise_calib_by_driver;
1695
1696 const u32 regulatory_bands[7];
1697};
1698
1699
1700
1701
1702
1703int il_mac_conf_tx(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1704 u16 queue, const struct ieee80211_tx_queue_params *params);
1705int il_mac_tx_last_beacon(struct ieee80211_hw *hw);
1706
1707void il_set_rxon_hwcrypto(struct il_priv *il, int hw_decrypt);
1708int il_check_rxon_cmd(struct il_priv *il);
1709int il_full_rxon_required(struct il_priv *il);
1710int il_set_rxon_channel(struct il_priv *il, struct ieee80211_channel *ch);
1711void il_set_flags_for_band(struct il_priv *il, enum nl80211_band band,
1712 struct ieee80211_vif *vif);
1713u8 il_get_single_channel_number(struct il_priv *il, enum nl80211_band band);
1714void il_set_rxon_ht(struct il_priv *il, struct il_ht_config *ht_conf);
1715bool il_is_ht40_tx_allowed(struct il_priv *il,
1716 struct ieee80211_sta_ht_cap *ht_cap);
1717void il_connection_init_rx_config(struct il_priv *il);
1718void il_set_rate(struct il_priv *il);
1719int il_set_decrypted_flag(struct il_priv *il, struct ieee80211_hdr *hdr,
1720 u32 decrypt_res, struct ieee80211_rx_status *stats);
1721void il_irq_handle_error(struct il_priv *il);
1722int il_mac_add_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
1723void il_mac_remove_interface(struct ieee80211_hw *hw,
1724 struct ieee80211_vif *vif);
1725int il_mac_change_interface(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1726 enum nl80211_iftype newtype, bool newp2p);
1727void il_mac_flush(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1728 u32 queues, bool drop);
1729int il_alloc_txq_mem(struct il_priv *il);
1730void il_free_txq_mem(struct il_priv *il);
1731
1732#ifdef CONFIG_IWLEGACY_DEBUGFS
1733void il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len);
1734#else
1735static inline void
1736il_update_stats(struct il_priv *il, bool is_tx, __le16 fc, u16 len)
1737{
1738}
1739#endif
1740
1741
1742
1743
1744void il_hdl_pm_sleep(struct il_priv *il, struct il_rx_buf *rxb);
1745void il_hdl_pm_debug_stats(struct il_priv *il, struct il_rx_buf *rxb);
1746void il_hdl_error(struct il_priv *il, struct il_rx_buf *rxb);
1747void il_hdl_csa(struct il_priv *il, struct il_rx_buf *rxb);
1748
1749
1750
1751
1752void il_cmd_queue_unmap(struct il_priv *il);
1753void il_cmd_queue_free(struct il_priv *il);
1754int il_rx_queue_alloc(struct il_priv *il);
1755void il_rx_queue_update_write_ptr(struct il_priv *il, struct il_rx_queue *q);
1756int il_rx_queue_space(const struct il_rx_queue *q);
1757void il_tx_cmd_complete(struct il_priv *il, struct il_rx_buf *rxb);
1758
1759void il_hdl_spectrum_measurement(struct il_priv *il, struct il_rx_buf *rxb);
1760void il_recover_from_stats(struct il_priv *il, struct il_rx_pkt *pkt);
1761void il_chswitch_done(struct il_priv *il, bool is_success);
1762
1763
1764
1765
1766void il_txq_update_write_ptr(struct il_priv *il, struct il_tx_queue *txq);
1767int il_tx_queue_init(struct il_priv *il, u32 txq_id);
1768void il_tx_queue_reset(struct il_priv *il, u32 txq_id);
1769void il_tx_queue_unmap(struct il_priv *il, int txq_id);
1770void il_tx_queue_free(struct il_priv *il, int txq_id);
1771void il_setup_watchdog(struct il_priv *il);
1772
1773
1774
1775int il_set_tx_power(struct il_priv *il, s8 tx_power, bool force);
1776
1777
1778
1779
1780
1781u8 il_get_lowest_plcp(struct il_priv *il);
1782
1783
1784
1785
1786void il_init_scan_params(struct il_priv *il);
1787int il_scan_cancel(struct il_priv *il);
1788int il_scan_cancel_timeout(struct il_priv *il, unsigned long ms);
1789void il_force_scan_end(struct il_priv *il);
1790int il_mac_hw_scan(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1791 struct ieee80211_scan_request *hw_req);
1792void il_internal_short_hw_scan(struct il_priv *il);
1793int il_force_reset(struct il_priv *il, bool external);
1794u16 il_fill_probe_req(struct il_priv *il, struct ieee80211_mgmt *frame,
1795 const u8 *ta, const u8 *ie, int ie_len, int left);
1796void il_setup_rx_scan_handlers(struct il_priv *il);
1797u16 il_get_active_dwell_time(struct il_priv *il, enum nl80211_band band,
1798 u8 n_probes);
1799u16 il_get_passive_dwell_time(struct il_priv *il, enum nl80211_band band,
1800 struct ieee80211_vif *vif);
1801void il_setup_scan_deferred_work(struct il_priv *il);
1802void il_cancel_scan_deferred_work(struct il_priv *il);
1803
1804
1805
1806
1807
1808
1809
1810#define IL_ACTIVE_QUIET_TIME cpu_to_le16(10)
1811#define IL_PLCP_QUIET_THRESH cpu_to_le16(1)
1812
1813#define IL_SCAN_CHECK_WATCHDOG (HZ * 7)
1814
1815
1816
1817
1818
1819const char *il_get_cmd_string(u8 cmd);
1820int __must_check il_send_cmd_sync(struct il_priv *il, struct il_host_cmd *cmd);
1821int il_send_cmd(struct il_priv *il, struct il_host_cmd *cmd);
1822int __must_check il_send_cmd_pdu(struct il_priv *il, u8 id, u16 len,
1823 const void *data);
1824int il_send_cmd_pdu_async(struct il_priv *il, u8 id, u16 len, const void *data,
1825 void (*callback) (struct il_priv *il,
1826 struct il_device_cmd *cmd,
1827 struct il_rx_pkt *pkt));
1828
1829int il_enqueue_hcmd(struct il_priv *il, struct il_host_cmd *cmd);
1830
1831
1832
1833
1834
1835void il_bg_watchdog(unsigned long data);
1836u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);
1837__le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
1838 u32 beacon_interval);
1839
1840#ifdef CONFIG_PM_SLEEP
1841extern const struct dev_pm_ops il_pm_ops;
1842
1843#define IL_LEGACY_PM_OPS (&il_pm_ops)
1844
1845#else
1846
1847#define IL_LEGACY_PM_OPS NULL
1848
1849#endif
1850
1851
1852
1853
1854void il4965_dump_nic_error_log(struct il_priv *il);
1855#ifdef CONFIG_IWLEGACY_DEBUG
1856void il_print_rx_config_cmd(struct il_priv *il);
1857#else
1858static inline void
1859il_print_rx_config_cmd(struct il_priv *il)
1860{
1861}
1862#endif
1863
1864void il_clear_isr_stats(struct il_priv *il);
1865
1866
1867
1868
1869int il_init_geos(struct il_priv *il);
1870void il_free_geos(struct il_priv *il);
1871
1872
1873
1874#define S_HCMD_ACTIVE 0
1875
1876#define S_INT_ENABLED 2
1877#define S_RFKILL 3
1878#define S_CT_KILL 4
1879#define S_INIT 5
1880#define S_ALIVE 6
1881#define S_READY 7
1882#define S_TEMPERATURE 8
1883#define S_GEO_CONFIGURED 9
1884#define S_EXIT_PENDING 10
1885#define S_STATS 12
1886#define S_SCANNING 13
1887#define S_SCAN_ABORTING 14
1888#define S_SCAN_HW 15
1889#define S_POWER_PMI 16
1890#define S_FW_ERROR 17
1891#define S_CHANNEL_SWITCH_PENDING 18
1892
1893static inline int
1894il_is_ready(struct il_priv *il)
1895{
1896
1897
1898 return test_bit(S_READY, &il->status) &&
1899 test_bit(S_GEO_CONFIGURED, &il->status) &&
1900 !test_bit(S_EXIT_PENDING, &il->status);
1901}
1902
1903static inline int
1904il_is_alive(struct il_priv *il)
1905{
1906 return test_bit(S_ALIVE, &il->status);
1907}
1908
1909static inline int
1910il_is_init(struct il_priv *il)
1911{
1912 return test_bit(S_INIT, &il->status);
1913}
1914
1915static inline int
1916il_is_rfkill(struct il_priv *il)
1917{
1918 return test_bit(S_RFKILL, &il->status);
1919}
1920
1921static inline int
1922il_is_ctkill(struct il_priv *il)
1923{
1924 return test_bit(S_CT_KILL, &il->status);
1925}
1926
1927static inline int
1928il_is_ready_rf(struct il_priv *il)
1929{
1930
1931 if (il_is_rfkill(il))
1932 return 0;
1933
1934 return il_is_ready(il);
1935}
1936
1937void il_send_bt_config(struct il_priv *il);
1938int il_send_stats_request(struct il_priv *il, u8 flags, bool clear);
1939void il_apm_stop(struct il_priv *il);
1940void _il_apm_stop(struct il_priv *il);
1941
1942int il_apm_init(struct il_priv *il);
1943
1944int il_send_rxon_timing(struct il_priv *il);
1945
1946static inline int
1947il_send_rxon_assoc(struct il_priv *il)
1948{
1949 return il->ops->rxon_assoc(il);
1950}
1951
1952static inline int
1953il_commit_rxon(struct il_priv *il)
1954{
1955 return il->ops->commit_rxon(il);
1956}
1957
1958static inline const struct ieee80211_supported_band *
1959il_get_hw_mode(struct il_priv *il, enum nl80211_band band)
1960{
1961 return il->hw->wiphy->bands[band];
1962}
1963
1964
1965int il_mac_config(struct ieee80211_hw *hw, u32 changed);
1966void il_mac_reset_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
1967void il_mac_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
1968 struct ieee80211_bss_conf *bss_conf, u32 changes);
1969void il_tx_cmd_protection(struct il_priv *il, struct ieee80211_tx_info *info,
1970 __le16 fc, __le32 *tx_flags);
1971
1972irqreturn_t il_isr(int irq, void *data);
1973
1974void il_set_bit(struct il_priv *p, u32 r, u32 m);
1975void il_clear_bit(struct il_priv *p, u32 r, u32 m);
1976bool _il_grab_nic_access(struct il_priv *il);
1977int _il_poll_bit(struct il_priv *il, u32 addr, u32 bits, u32 mask, int timeout);
1978int il_poll_bit(struct il_priv *il, u32 addr, u32 mask, int timeout);
1979u32 il_rd_prph(struct il_priv *il, u32 reg);
1980void il_wr_prph(struct il_priv *il, u32 addr, u32 val);
1981u32 il_read_targ_mem(struct il_priv *il, u32 addr);
1982void il_write_targ_mem(struct il_priv *il, u32 addr, u32 val);
1983
1984static inline bool il_need_reclaim(struct il_priv *il, struct il_rx_pkt *pkt)
1985{
1986
1987
1988
1989
1990
1991
1992 return !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
1993 pkt->hdr.cmd != N_STATS && pkt->hdr.cmd != C_TX &&
1994 pkt->hdr.cmd != N_RX_PHY && pkt->hdr.cmd != N_RX &&
1995 pkt->hdr.cmd != N_RX_MPDU && pkt->hdr.cmd != N_COMPRESSED_BA;
1996}
1997
1998static inline void
1999_il_write8(struct il_priv *il, u32 ofs, u8 val)
2000{
2001 writeb(val, il->hw_base + ofs);
2002}
2003#define il_write8(il, ofs, val) _il_write8(il, ofs, val)
2004
2005static inline void
2006_il_wr(struct il_priv *il, u32 ofs, u32 val)
2007{
2008 writel(val, il->hw_base + ofs);
2009}
2010
2011static inline u32
2012_il_rd(struct il_priv *il, u32 ofs)
2013{
2014 return readl(il->hw_base + ofs);
2015}
2016
2017static inline void
2018_il_clear_bit(struct il_priv *il, u32 reg, u32 mask)
2019{
2020 _il_wr(il, reg, _il_rd(il, reg) & ~mask);
2021}
2022
2023static inline void
2024_il_set_bit(struct il_priv *il, u32 reg, u32 mask)
2025{
2026 _il_wr(il, reg, _il_rd(il, reg) | mask);
2027}
2028
2029static inline void
2030_il_release_nic_access(struct il_priv *il)
2031{
2032 _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
2033
2034
2035
2036
2037
2038
2039 mmiowb();
2040}
2041
2042static inline u32
2043il_rd(struct il_priv *il, u32 reg)
2044{
2045 u32 value;
2046 unsigned long reg_flags;
2047
2048 spin_lock_irqsave(&il->reg_lock, reg_flags);
2049 _il_grab_nic_access(il);
2050 value = _il_rd(il, reg);
2051 _il_release_nic_access(il);
2052 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2053 return value;
2054}
2055
2056static inline void
2057il_wr(struct il_priv *il, u32 reg, u32 value)
2058{
2059 unsigned long reg_flags;
2060
2061 spin_lock_irqsave(&il->reg_lock, reg_flags);
2062 if (likely(_il_grab_nic_access(il))) {
2063 _il_wr(il, reg, value);
2064 _il_release_nic_access(il);
2065 }
2066 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2067}
2068
2069static inline u32
2070_il_rd_prph(struct il_priv *il, u32 reg)
2071{
2072 _il_wr(il, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
2073 return _il_rd(il, HBUS_TARG_PRPH_RDAT);
2074}
2075
2076static inline void
2077_il_wr_prph(struct il_priv *il, u32 addr, u32 val)
2078{
2079 _il_wr(il, HBUS_TARG_PRPH_WADDR, ((addr & 0x0000FFFF) | (3 << 24)));
2080 _il_wr(il, HBUS_TARG_PRPH_WDAT, val);
2081}
2082
2083static inline void
2084il_set_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2085{
2086 unsigned long reg_flags;
2087
2088 spin_lock_irqsave(&il->reg_lock, reg_flags);
2089 if (likely(_il_grab_nic_access(il))) {
2090 _il_wr_prph(il, reg, (_il_rd_prph(il, reg) | mask));
2091 _il_release_nic_access(il);
2092 }
2093 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2094}
2095
2096static inline void
2097il_set_bits_mask_prph(struct il_priv *il, u32 reg, u32 bits, u32 mask)
2098{
2099 unsigned long reg_flags;
2100
2101 spin_lock_irqsave(&il->reg_lock, reg_flags);
2102 if (likely(_il_grab_nic_access(il))) {
2103 _il_wr_prph(il, reg, ((_il_rd_prph(il, reg) & mask) | bits));
2104 _il_release_nic_access(il);
2105 }
2106 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2107}
2108
2109static inline void
2110il_clear_bits_prph(struct il_priv *il, u32 reg, u32 mask)
2111{
2112 unsigned long reg_flags;
2113 u32 val;
2114
2115 spin_lock_irqsave(&il->reg_lock, reg_flags);
2116 if (likely(_il_grab_nic_access(il))) {
2117 val = _il_rd_prph(il, reg);
2118 _il_wr_prph(il, reg, (val & ~mask));
2119 _il_release_nic_access(il);
2120 }
2121 spin_unlock_irqrestore(&il->reg_lock, reg_flags);
2122}
2123
2124#define HW_KEY_DYNAMIC 0
2125#define HW_KEY_DEFAULT 1
2126
2127#define IL_STA_DRIVER_ACTIVE BIT(0)
2128#define IL_STA_UCODE_ACTIVE BIT(1)
2129#define IL_STA_UCODE_INPROGRESS BIT(2)
2130
2131#define IL_STA_LOCAL BIT(3)
2132
2133#define IL_STA_BCAST BIT(4)
2134
2135void il_restore_stations(struct il_priv *il);
2136void il_clear_ucode_stations(struct il_priv *il);
2137void il_dealloc_bcast_stations(struct il_priv *il);
2138int il_get_free_ucode_key_idx(struct il_priv *il);
2139int il_send_add_sta(struct il_priv *il, struct il_addsta_cmd *sta, u8 flags);
2140int il_add_station_common(struct il_priv *il, const u8 *addr, bool is_ap,
2141 struct ieee80211_sta *sta, u8 *sta_id_r);
2142int il_remove_station(struct il_priv *il, const u8 sta_id, const u8 * addr);
2143int il_mac_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
2144 struct ieee80211_sta *sta);
2145
2146u8 il_prep_station(struct il_priv *il, const u8 *addr, bool is_ap,
2147 struct ieee80211_sta *sta);
2148
2149int il_send_lq_cmd(struct il_priv *il, struct il_link_quality_cmd *lq,
2150 u8 flags, bool init);
2151
2152
2153
2154
2155
2156
2157
2158
2159
2160
2161static inline void
2162il_clear_driver_stations(struct il_priv *il)
2163{
2164 unsigned long flags;
2165
2166 spin_lock_irqsave(&il->sta_lock, flags);
2167 memset(il->stations, 0, sizeof(il->stations));
2168 il->num_stations = 0;
2169 il->ucode_key_table = 0;
2170 spin_unlock_irqrestore(&il->sta_lock, flags);
2171}
2172
2173static inline int
2174il_sta_id(struct ieee80211_sta *sta)
2175{
2176 if (WARN_ON(!sta))
2177 return IL_INVALID_STATION;
2178
2179 return ((struct il_station_priv_common *)sta->drv_priv)->sta_id;
2180}
2181
2182
2183
2184
2185
2186
2187
2188
2189
2190
2191
2192
2193static inline int
2194il_sta_id_or_broadcast(struct il_priv *il, struct ieee80211_sta *sta)
2195{
2196 int sta_id;
2197
2198 if (!sta)
2199 return il->hw_params.bcast_id;
2200
2201 sta_id = il_sta_id(sta);
2202
2203
2204
2205
2206
2207 WARN_ON(sta_id == IL_INVALID_STATION);
2208
2209 return sta_id;
2210}
2211
2212
2213
2214
2215
2216
2217static inline int
2218il_queue_inc_wrap(int idx, int n_bd)
2219{
2220 return ++idx & (n_bd - 1);
2221}
2222
2223
2224
2225
2226
2227
2228static inline int
2229il_queue_dec_wrap(int idx, int n_bd)
2230{
2231 return --idx & (n_bd - 1);
2232}
2233
2234
2235static inline void
2236il_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
2237{
2238 if (desc->v_addr)
2239 dma_free_coherent(&pci_dev->dev, desc->len, desc->v_addr,
2240 desc->p_addr);
2241 desc->v_addr = NULL;
2242 desc->len = 0;
2243}
2244
2245static inline int
2246il_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
2247{
2248 if (!desc->len) {
2249 desc->v_addr = NULL;
2250 return -EINVAL;
2251 }
2252
2253 desc->v_addr = dma_alloc_coherent(&pci_dev->dev, desc->len,
2254 &desc->p_addr, GFP_KERNEL);
2255 return (desc->v_addr != NULL) ? 0 : -ENOMEM;
2256}
2257
2258
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268
2269static inline void
2270il_set_swq_id(struct il_tx_queue *txq, u8 ac, u8 hwq)
2271{
2272 BUG_ON(ac > 3);
2273 BUG_ON(hwq > 31);
2274
2275 txq->swq_id = (hwq << 2) | ac;
2276}
2277
2278static inline void
2279_il_wake_queue(struct il_priv *il, u8 ac)
2280{
2281 if (atomic_dec_return(&il->queue_stop_count[ac]) <= 0)
2282 ieee80211_wake_queue(il->hw, ac);
2283}
2284
2285static inline void
2286_il_stop_queue(struct il_priv *il, u8 ac)
2287{
2288 if (atomic_inc_return(&il->queue_stop_count[ac]) > 0)
2289 ieee80211_stop_queue(il->hw, ac);
2290}
2291static inline void
2292il_wake_queue(struct il_priv *il, struct il_tx_queue *txq)
2293{
2294 u8 queue = txq->swq_id;
2295 u8 ac = queue & 3;
2296 u8 hwq = (queue >> 2) & 0x1f;
2297
2298 if (test_and_clear_bit(hwq, il->queue_stopped))
2299 _il_wake_queue(il, ac);
2300}
2301
2302static inline void
2303il_stop_queue(struct il_priv *il, struct il_tx_queue *txq)
2304{
2305 u8 queue = txq->swq_id;
2306 u8 ac = queue & 3;
2307 u8 hwq = (queue >> 2) & 0x1f;
2308
2309 if (!test_and_set_bit(hwq, il->queue_stopped))
2310 _il_stop_queue(il, ac);
2311}
2312
2313static inline void
2314il_wake_queues_by_reason(struct il_priv *il, int reason)
2315{
2316 u8 ac;
2317
2318 if (test_and_clear_bit(reason, &il->stop_reason))
2319 for (ac = 0; ac < 4; ac++)
2320 _il_wake_queue(il, ac);
2321}
2322
2323static inline void
2324il_stop_queues_by_reason(struct il_priv *il, int reason)
2325{
2326 u8 ac;
2327
2328 if (!test_and_set_bit(reason, &il->stop_reason))
2329 for (ac = 0; ac < 4; ac++)
2330 _il_stop_queue(il, ac);
2331}
2332
2333#ifdef ieee80211_stop_queue
2334#undef ieee80211_stop_queue
2335#endif
2336
2337#define ieee80211_stop_queue DO_NOT_USE_ieee80211_stop_queue
2338
2339#ifdef ieee80211_wake_queue
2340#undef ieee80211_wake_queue
2341#endif
2342
2343#define ieee80211_wake_queue DO_NOT_USE_ieee80211_wake_queue
2344
2345static inline void
2346il_disable_interrupts(struct il_priv *il)
2347{
2348 clear_bit(S_INT_ENABLED, &il->status);
2349
2350
2351 _il_wr(il, CSR_INT_MASK, 0x00000000);
2352
2353
2354
2355 _il_wr(il, CSR_INT, 0xffffffff);
2356 _il_wr(il, CSR_FH_INT_STATUS, 0xffffffff);
2357}
2358
2359static inline void
2360il_enable_rfkill_int(struct il_priv *il)
2361{
2362 _il_wr(il, CSR_INT_MASK, CSR_INT_BIT_RF_KILL);
2363}
2364
2365static inline void
2366il_enable_interrupts(struct il_priv *il)
2367{
2368 set_bit(S_INT_ENABLED, &il->status);
2369 _il_wr(il, CSR_INT_MASK, il->inta_mask);
2370}
2371
2372
2373
2374
2375
2376
2377static inline u32
2378il_beacon_time_mask_low(struct il_priv *il, u16 tsf_bits)
2379{
2380 return (1 << tsf_bits) - 1;
2381}
2382
2383
2384
2385
2386
2387
2388static inline u32
2389il_beacon_time_mask_high(struct il_priv *il, u16 tsf_bits)
2390{
2391 return ((1 << (32 - tsf_bits)) - 1) << tsf_bits;
2392}
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402
2403
2404struct il_rb_status {
2405 __le16 closed_rb_num;
2406 __le16 closed_fr_num;
2407 __le16 finished_rb_num;
2408 __le16 finished_fr_nam;
2409 __le32 __unused;
2410} __packed;
2411
2412#define TFD_QUEUE_SIZE_MAX 256
2413#define TFD_QUEUE_SIZE_BC_DUP 64
2414#define TFD_QUEUE_BC_SIZE (TFD_QUEUE_SIZE_MAX + TFD_QUEUE_SIZE_BC_DUP)
2415#define IL_TX_DMA_MASK DMA_BIT_MASK(36)
2416#define IL_NUM_OF_TBS 20
2417
2418static inline u8
2419il_get_dma_hi_addr(dma_addr_t addr)
2420{
2421 return (sizeof(addr) > sizeof(u32) ? (addr >> 16) >> 16 : 0) & 0xF;
2422}
2423
2424
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434struct il_tfd_tb {
2435 __le32 lo;
2436 __le16 hi_n_len;
2437} __packed;
2438
2439
2440
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459
2460
2461
2462
2463
2464
2465
2466
2467struct il_tfd {
2468 u8 __reserved1[3];
2469 u8 num_tbs;
2470 struct il_tfd_tb tbs[IL_NUM_OF_TBS];
2471 __le32 __pad;
2472} __packed;
2473
2474#define PCI_CFG_RETRY_TIMEOUT 0x041
2475
2476struct il_rate_info {
2477 u8 plcp;
2478 u8 plcp_siso;
2479 u8 plcp_mimo2;
2480 u8 ieee;
2481 u8 prev_ieee;
2482 u8 next_ieee;
2483 u8 prev_rs;
2484 u8 next_rs;
2485 u8 prev_rs_tgg;
2486 u8 next_rs_tgg;
2487};
2488
2489struct il3945_rate_info {
2490 u8 plcp;
2491 u8 ieee;
2492 u8 prev_ieee;
2493 u8 next_ieee;
2494 u8 prev_rs;
2495 u8 next_rs;
2496 u8 prev_rs_tgg;
2497 u8 next_rs_tgg;
2498 u8 table_rs_idx;
2499 u8 prev_table_rs;
2500};
2501
2502
2503
2504
2505
2506enum {
2507 RATE_1M_IDX = 0,
2508 RATE_2M_IDX,
2509 RATE_5M_IDX,
2510 RATE_11M_IDX,
2511 RATE_6M_IDX,
2512 RATE_9M_IDX,
2513 RATE_12M_IDX,
2514 RATE_18M_IDX,
2515 RATE_24M_IDX,
2516 RATE_36M_IDX,
2517 RATE_48M_IDX,
2518 RATE_54M_IDX,
2519 RATE_60M_IDX,
2520 RATE_COUNT,
2521 RATE_COUNT_LEGACY = RATE_COUNT - 1,
2522 RATE_COUNT_3945 = RATE_COUNT - 1,
2523 RATE_INVM_IDX = RATE_COUNT,
2524 RATE_INVALID = RATE_COUNT,
2525};
2526
2527enum {
2528 RATE_6M_IDX_TBL = 0,
2529 RATE_9M_IDX_TBL,
2530 RATE_12M_IDX_TBL,
2531 RATE_18M_IDX_TBL,
2532 RATE_24M_IDX_TBL,
2533 RATE_36M_IDX_TBL,
2534 RATE_48M_IDX_TBL,
2535 RATE_54M_IDX_TBL,
2536 RATE_1M_IDX_TBL,
2537 RATE_2M_IDX_TBL,
2538 RATE_5M_IDX_TBL,
2539 RATE_11M_IDX_TBL,
2540 RATE_INVM_IDX_TBL = RATE_INVM_IDX - 1,
2541};
2542
2543enum {
2544 IL_FIRST_OFDM_RATE = RATE_6M_IDX,
2545 IL39_LAST_OFDM_RATE = RATE_54M_IDX,
2546 IL_LAST_OFDM_RATE = RATE_60M_IDX,
2547 IL_FIRST_CCK_RATE = RATE_1M_IDX,
2548 IL_LAST_CCK_RATE = RATE_11M_IDX,
2549};
2550
2551
2552#define RATE_6M_MASK (1 << RATE_6M_IDX)
2553#define RATE_9M_MASK (1 << RATE_9M_IDX)
2554#define RATE_12M_MASK (1 << RATE_12M_IDX)
2555#define RATE_18M_MASK (1 << RATE_18M_IDX)
2556#define RATE_24M_MASK (1 << RATE_24M_IDX)
2557#define RATE_36M_MASK (1 << RATE_36M_IDX)
2558#define RATE_48M_MASK (1 << RATE_48M_IDX)
2559#define RATE_54M_MASK (1 << RATE_54M_IDX)
2560#define RATE_60M_MASK (1 << RATE_60M_IDX)
2561#define RATE_1M_MASK (1 << RATE_1M_IDX)
2562#define RATE_2M_MASK (1 << RATE_2M_IDX)
2563#define RATE_5M_MASK (1 << RATE_5M_IDX)
2564#define RATE_11M_MASK (1 << RATE_11M_IDX)
2565
2566
2567enum {
2568 RATE_6M_PLCP = 13,
2569 RATE_9M_PLCP = 15,
2570 RATE_12M_PLCP = 5,
2571 RATE_18M_PLCP = 7,
2572 RATE_24M_PLCP = 9,
2573 RATE_36M_PLCP = 11,
2574 RATE_48M_PLCP = 1,
2575 RATE_54M_PLCP = 3,
2576 RATE_60M_PLCP = 3,
2577 RATE_1M_PLCP = 10,
2578 RATE_2M_PLCP = 20,
2579 RATE_5M_PLCP = 55,
2580 RATE_11M_PLCP = 110,
2581
2582};
2583
2584
2585enum {
2586 RATE_SISO_6M_PLCP = 0,
2587 RATE_SISO_12M_PLCP = 1,
2588 RATE_SISO_18M_PLCP = 2,
2589 RATE_SISO_24M_PLCP = 3,
2590 RATE_SISO_36M_PLCP = 4,
2591 RATE_SISO_48M_PLCP = 5,
2592 RATE_SISO_54M_PLCP = 6,
2593 RATE_SISO_60M_PLCP = 7,
2594 RATE_MIMO2_6M_PLCP = 0x8,
2595 RATE_MIMO2_12M_PLCP = 0x9,
2596 RATE_MIMO2_18M_PLCP = 0xa,
2597 RATE_MIMO2_24M_PLCP = 0xb,
2598 RATE_MIMO2_36M_PLCP = 0xc,
2599 RATE_MIMO2_48M_PLCP = 0xd,
2600 RATE_MIMO2_54M_PLCP = 0xe,
2601 RATE_MIMO2_60M_PLCP = 0xf,
2602 RATE_SISO_INVM_PLCP,
2603 RATE_MIMO2_INVM_PLCP = RATE_SISO_INVM_PLCP,
2604};
2605
2606
2607enum {
2608 RATE_6M_IEEE = 12,
2609 RATE_9M_IEEE = 18,
2610 RATE_12M_IEEE = 24,
2611 RATE_18M_IEEE = 36,
2612 RATE_24M_IEEE = 48,
2613 RATE_36M_IEEE = 72,
2614 RATE_48M_IEEE = 96,
2615 RATE_54M_IEEE = 108,
2616 RATE_60M_IEEE = 120,
2617 RATE_1M_IEEE = 2,
2618 RATE_2M_IEEE = 4,
2619 RATE_5M_IEEE = 11,
2620 RATE_11M_IEEE = 22,
2621};
2622
2623#define IL_CCK_BASIC_RATES_MASK \
2624 (RATE_1M_MASK | \
2625 RATE_2M_MASK)
2626
2627#define IL_CCK_RATES_MASK \
2628 (IL_CCK_BASIC_RATES_MASK | \
2629 RATE_5M_MASK | \
2630 RATE_11M_MASK)
2631
2632#define IL_OFDM_BASIC_RATES_MASK \
2633 (RATE_6M_MASK | \
2634 RATE_12M_MASK | \
2635 RATE_24M_MASK)
2636
2637#define IL_OFDM_RATES_MASK \
2638 (IL_OFDM_BASIC_RATES_MASK | \
2639 RATE_9M_MASK | \
2640 RATE_18M_MASK | \
2641 RATE_36M_MASK | \
2642 RATE_48M_MASK | \
2643 RATE_54M_MASK)
2644
2645#define IL_BASIC_RATES_MASK \
2646 (IL_OFDM_BASIC_RATES_MASK | \
2647 IL_CCK_BASIC_RATES_MASK)
2648
2649#define RATES_MASK ((1 << RATE_COUNT) - 1)
2650#define RATES_MASK_3945 ((1 << RATE_COUNT_3945) - 1)
2651
2652#define IL_INVALID_VALUE -1
2653
2654#define IL_MIN_RSSI_VAL -100
2655#define IL_MAX_RSSI_VAL 0
2656
2657
2658
2659#define IL_LEGACY_FAILURE_LIMIT 160
2660#define IL_LEGACY_SUCCESS_LIMIT 480
2661#define IL_LEGACY_TBL_COUNT 160
2662
2663#define IL_NONE_LEGACY_FAILURE_LIMIT 400
2664#define IL_NONE_LEGACY_SUCCESS_LIMIT 4500
2665#define IL_NONE_LEGACY_TBL_COUNT 1500
2666
2667
2668#define IL_RS_GOOD_RATIO 12800
2669#define RATE_SCALE_SWITCH 10880
2670#define RATE_HIGH_TH 10880
2671#define RATE_INCREASE_TH 6400
2672#define RATE_DECREASE_TH 1920
2673
2674
2675#define IL_LEGACY_SWITCH_ANTENNA1 0
2676#define IL_LEGACY_SWITCH_ANTENNA2 1
2677#define IL_LEGACY_SWITCH_SISO 2
2678#define IL_LEGACY_SWITCH_MIMO2_AB 3
2679#define IL_LEGACY_SWITCH_MIMO2_AC 4
2680#define IL_LEGACY_SWITCH_MIMO2_BC 5
2681
2682
2683#define IL_SISO_SWITCH_ANTENNA1 0
2684#define IL_SISO_SWITCH_ANTENNA2 1
2685#define IL_SISO_SWITCH_MIMO2_AB 2
2686#define IL_SISO_SWITCH_MIMO2_AC 3
2687#define IL_SISO_SWITCH_MIMO2_BC 4
2688#define IL_SISO_SWITCH_GI 5
2689
2690
2691#define IL_MIMO2_SWITCH_ANTENNA1 0
2692#define IL_MIMO2_SWITCH_ANTENNA2 1
2693#define IL_MIMO2_SWITCH_SISO_A 2
2694#define IL_MIMO2_SWITCH_SISO_B 3
2695#define IL_MIMO2_SWITCH_SISO_C 4
2696#define IL_MIMO2_SWITCH_GI 5
2697
2698#define IL_MAX_SEARCH IL_MIMO2_SWITCH_GI
2699
2700#define IL_ACTION_LIMIT 3
2701
2702#define LQ_SIZE 2
2703
2704
2705#define IL_AGG_TPT_THREHOLD 0
2706#define IL_AGG_LOAD_THRESHOLD 10
2707#define IL_AGG_ALL_TID 0xff
2708#define TID_QUEUE_CELL_SPACING 50
2709#define TID_QUEUE_MAX_SIZE 20
2710#define TID_ROUND_VALUE 5
2711#define TID_MAX_LOAD_COUNT 8
2712
2713#define TID_MAX_TIME_DIFF ((TID_QUEUE_MAX_SIZE - 1) * TID_QUEUE_CELL_SPACING)
2714#define TIME_WRAP_AROUND(x, y) (((y) > (x)) ? (y) - (x) : (0-(x)) + (y))
2715
2716extern const struct il_rate_info il_rates[RATE_COUNT];
2717
2718enum il_table_type {
2719 LQ_NONE,
2720 LQ_G,
2721 LQ_A,
2722 LQ_SISO,
2723 LQ_MIMO2,
2724 LQ_MAX,
2725};
2726
2727#define is_legacy(tbl) ((tbl) == LQ_G || (tbl) == LQ_A)
2728#define is_siso(tbl) ((tbl) == LQ_SISO)
2729#define is_mimo2(tbl) ((tbl) == LQ_MIMO2)
2730#define is_mimo(tbl) (is_mimo2(tbl))
2731#define is_Ht(tbl) (is_siso(tbl) || is_mimo(tbl))
2732#define is_a_band(tbl) ((tbl) == LQ_A)
2733#define is_g_and(tbl) ((tbl) == LQ_G)
2734
2735#define ANT_NONE 0x0
2736#define ANT_A BIT(0)
2737#define ANT_B BIT(1)
2738#define ANT_AB (ANT_A | ANT_B)
2739#define ANT_C BIT(2)
2740#define ANT_AC (ANT_A | ANT_C)
2741#define ANT_BC (ANT_B | ANT_C)
2742#define ANT_ABC (ANT_AB | ANT_C)
2743
2744#define IL_MAX_MCS_DISPLAY_SIZE 12
2745
2746struct il_rate_mcs_info {
2747 char mbps[IL_MAX_MCS_DISPLAY_SIZE];
2748 char mcs[IL_MAX_MCS_DISPLAY_SIZE];
2749};
2750
2751
2752
2753
2754struct il_rate_scale_data {
2755 u64 data;
2756 s32 success_counter;
2757 s32 success_ratio;
2758 s32 counter;
2759 s32 average_tpt;
2760 unsigned long stamp;
2761};
2762
2763
2764
2765
2766
2767
2768
2769struct il_scale_tbl_info {
2770 enum il_table_type lq_type;
2771 u8 ant_type;
2772 u8 is_SGI;
2773 u8 is_ht40;
2774 u8 is_dup;
2775 u8 action;
2776 u8 max_search;
2777 s32 *expected_tpt;
2778 u32 current_rate;
2779 struct il_rate_scale_data win[RATE_COUNT];
2780};
2781
2782struct il_traffic_load {
2783 unsigned long time_stamp;
2784 u32 packet_count[TID_QUEUE_MAX_SIZE];
2785
2786 u32 total;
2787
2788 u8 queue_count;
2789
2790 u8 head;
2791};
2792
2793
2794
2795
2796
2797
2798struct il_lq_sta {
2799 u8 active_tbl;
2800 u8 enable_counter;
2801 u8 stay_in_tbl;
2802 u8 search_better_tbl;
2803 s32 last_tpt;
2804
2805
2806 u32 table_count_limit;
2807 u32 max_failure_limit;
2808 u32 max_success_limit;
2809 u32 table_count;
2810 u32 total_failed;
2811 u32 total_success;
2812 u64 flush_timer;
2813
2814 u8 action_counter;
2815 u8 is_green;
2816 u8 is_dup;
2817 enum nl80211_band band;
2818
2819
2820 u32 supp_rates;
2821 u16 active_legacy_rate;
2822 u16 active_siso_rate;
2823 u16 active_mimo2_rate;
2824 s8 max_rate_idx;
2825 u8 missed_rate_counter;
2826
2827 struct il_link_quality_cmd lq;
2828 struct il_scale_tbl_info lq_info[LQ_SIZE];
2829 struct il_traffic_load load[TID_MAX_LOAD_COUNT];
2830 u8 tx_agg_tid_en;
2831#ifdef CONFIG_MAC80211_DEBUGFS
2832 struct dentry *rs_sta_dbgfs_scale_table_file;
2833 struct dentry *rs_sta_dbgfs_stats_table_file;
2834 struct dentry *rs_sta_dbgfs_rate_scale_data_file;
2835 struct dentry *rs_sta_dbgfs_tx_agg_tid_en_file;
2836 u32 dbg_fixed_rate;
2837#endif
2838 struct il_priv *drv;
2839
2840
2841 int last_txrate_idx;
2842
2843 u32 last_rate_n_flags;
2844
2845 u8 is_agg;
2846};
2847
2848
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858struct il_station_priv {
2859 struct il_station_priv_common common;
2860 struct il_lq_sta lq_sta;
2861 atomic_t pending_frames;
2862 bool client;
2863 bool asleep;
2864};
2865
2866static inline u8
2867il4965_num_of_ant(u8 m)
2868{
2869 return !!(m & ANT_A) + !!(m & ANT_B) + !!(m & ANT_C);
2870}
2871
2872static inline u8
2873il4965_first_antenna(u8 mask)
2874{
2875 if (mask & ANT_A)
2876 return ANT_A;
2877 if (mask & ANT_B)
2878 return ANT_B;
2879 return ANT_C;
2880}
2881
2882
2883
2884
2885
2886
2887
2888void il3945_rate_scale_init(struct ieee80211_hw *hw, s32 sta_id);
2889
2890
2891void il4965_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
2892 u8 sta_id);
2893void il3945_rs_rate_init(struct il_priv *il, struct ieee80211_sta *sta,
2894 u8 sta_id);
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905
2906int il4965_rate_control_register(void);
2907int il3945_rate_control_register(void);
2908
2909
2910
2911
2912
2913
2914
2915void il4965_rate_control_unregister(void);
2916void il3945_rate_control_unregister(void);
2917
2918int il_power_update_mode(struct il_priv *il, bool force);
2919void il_power_initialize(struct il_priv *il);
2920
2921extern u32 il_debug_level;
2922
2923#ifdef CONFIG_IWLEGACY_DEBUG
2924
2925
2926
2927
2928
2929
2930
2931static inline u32
2932il_get_debug_level(struct il_priv *il)
2933{
2934 if (il->debug_level)
2935 return il->debug_level;
2936 else
2937 return il_debug_level;
2938}
2939#else
2940static inline u32
2941il_get_debug_level(struct il_priv *il)
2942{
2943 return il_debug_level;
2944}
2945#endif
2946
2947#define il_print_hex_error(il, p, len) \
2948do { \
2949 print_hex_dump(KERN_ERR, "iwl data: ", \
2950 DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \
2951} while (0)
2952
2953#ifdef CONFIG_IWLEGACY_DEBUG
2954#define IL_DBG(level, fmt, args...) \
2955do { \
2956 if (il_get_debug_level(il) & level) \
2957 dev_err(&il->hw->wiphy->dev, "%c %s " fmt, \
2958 in_interrupt() ? 'I' : 'U', __func__ , ##args); \
2959} while (0)
2960
2961#define il_print_hex_dump(il, level, p, len) \
2962do { \
2963 if (il_get_debug_level(il) & level) \
2964 print_hex_dump(KERN_DEBUG, "iwl data: ", \
2965 DUMP_PREFIX_OFFSET, 16, 1, p, len, 1); \
2966} while (0)
2967
2968#else
2969#define IL_DBG(level, fmt, args...)
2970static inline void
2971il_print_hex_dump(struct il_priv *il, int level, const void *p, u32 len)
2972{
2973}
2974#endif
2975
2976#ifdef CONFIG_IWLEGACY_DEBUGFS
2977int il_dbgfs_register(struct il_priv *il, const char *name);
2978void il_dbgfs_unregister(struct il_priv *il);
2979#else
2980static inline int
2981il_dbgfs_register(struct il_priv *il, const char *name)
2982{
2983 return 0;
2984}
2985
2986static inline void
2987il_dbgfs_unregister(struct il_priv *il)
2988{
2989}
2990#endif
2991
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016#define IL_DL_INFO (1 << 0)
3017#define IL_DL_MAC80211 (1 << 1)
3018#define IL_DL_HCMD (1 << 2)
3019#define IL_DL_STATE (1 << 3)
3020
3021#define IL_DL_MACDUMP (1 << 4)
3022#define IL_DL_HCMD_DUMP (1 << 5)
3023#define IL_DL_EEPROM (1 << 6)
3024#define IL_DL_RADIO (1 << 7)
3025
3026#define IL_DL_POWER (1 << 8)
3027#define IL_DL_TEMP (1 << 9)
3028#define IL_DL_NOTIF (1 << 10)
3029#define IL_DL_SCAN (1 << 11)
3030
3031#define IL_DL_ASSOC (1 << 12)
3032#define IL_DL_DROP (1 << 13)
3033#define IL_DL_TXPOWER (1 << 14)
3034#define IL_DL_AP (1 << 15)
3035
3036#define IL_DL_FW (1 << 16)
3037#define IL_DL_RF_KILL (1 << 17)
3038#define IL_DL_FW_ERRORS (1 << 18)
3039#define IL_DL_LED (1 << 19)
3040
3041#define IL_DL_RATE (1 << 20)
3042#define IL_DL_CALIB (1 << 21)
3043#define IL_DL_WEP (1 << 22)
3044#define IL_DL_TX (1 << 23)
3045
3046#define IL_DL_RX (1 << 24)
3047#define IL_DL_ISR (1 << 25)
3048#define IL_DL_HT (1 << 26)
3049
3050#define IL_DL_11H (1 << 28)
3051#define IL_DL_STATS (1 << 29)
3052#define IL_DL_TX_REPLY (1 << 30)
3053#define IL_DL_QOS (1 << 31)
3054
3055#define D_INFO(f, a...) IL_DBG(IL_DL_INFO, f, ## a)
3056#define D_MAC80211(f, a...) IL_DBG(IL_DL_MAC80211, f, ## a)
3057#define D_MACDUMP(f, a...) IL_DBG(IL_DL_MACDUMP, f, ## a)
3058#define D_TEMP(f, a...) IL_DBG(IL_DL_TEMP, f, ## a)
3059#define D_SCAN(f, a...) IL_DBG(IL_DL_SCAN, f, ## a)
3060#define D_RX(f, a...) IL_DBG(IL_DL_RX, f, ## a)
3061#define D_TX(f, a...) IL_DBG(IL_DL_TX, f, ## a)
3062#define D_ISR(f, a...) IL_DBG(IL_DL_ISR, f, ## a)
3063#define D_LED(f, a...) IL_DBG(IL_DL_LED, f, ## a)
3064#define D_WEP(f, a...) IL_DBG(IL_DL_WEP, f, ## a)
3065#define D_HC(f, a...) IL_DBG(IL_DL_HCMD, f, ## a)
3066#define D_HC_DUMP(f, a...) IL_DBG(IL_DL_HCMD_DUMP, f, ## a)
3067#define D_EEPROM(f, a...) IL_DBG(IL_DL_EEPROM, f, ## a)
3068#define D_CALIB(f, a...) IL_DBG(IL_DL_CALIB, f, ## a)
3069#define D_FW(f, a...) IL_DBG(IL_DL_FW, f, ## a)
3070#define D_RF_KILL(f, a...) IL_DBG(IL_DL_RF_KILL, f, ## a)
3071#define D_DROP(f, a...) IL_DBG(IL_DL_DROP, f, ## a)
3072#define D_AP(f, a...) IL_DBG(IL_DL_AP, f, ## a)
3073#define D_TXPOWER(f, a...) IL_DBG(IL_DL_TXPOWER, f, ## a)
3074#define D_RATE(f, a...) IL_DBG(IL_DL_RATE, f, ## a)
3075#define D_NOTIF(f, a...) IL_DBG(IL_DL_NOTIF, f, ## a)
3076#define D_ASSOC(f, a...) IL_DBG(IL_DL_ASSOC, f, ## a)
3077#define D_HT(f, a...) IL_DBG(IL_DL_HT, f, ## a)
3078#define D_STATS(f, a...) IL_DBG(IL_DL_STATS, f, ## a)
3079#define D_TX_REPLY(f, a...) IL_DBG(IL_DL_TX_REPLY, f, ## a)
3080#define D_QOS(f, a...) IL_DBG(IL_DL_QOS, f, ## a)
3081#define D_RADIO(f, a...) IL_DBG(IL_DL_RADIO, f, ## a)
3082#define D_POWER(f, a...) IL_DBG(IL_DL_POWER, f, ## a)
3083#define D_11H(f, a...) IL_DBG(IL_DL_11H, f, ## a)
3084
3085#endif
3086