1/* 2 * Copyright (C) 2008 Christian Lamparter <chunkeey@web.de> 3 * 4 * This driver is a port from stlc45xx: 5 * Copyright (C) 2008 Nokia Corporation and/or its subsidiary(-ies). 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License 9 * version 2 as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 19 * 02110-1301 USA 20 */ 21 22#ifndef P54SPI_H 23#define P54SPI_H 24 25#include <linux/mutex.h> 26#include <linux/list.h> 27#include <net/mac80211.h> 28 29#include "p54.h" 30 31/* Bit 15 is read/write bit; ON = READ, OFF = WRITE */ 32#define SPI_ADRS_READ_BIT_15 0x8000 33 34#define SPI_ADRS_ARM_INTERRUPTS 0x00 35#define SPI_ADRS_ARM_INT_EN 0x04 36 37#define SPI_ADRS_HOST_INTERRUPTS 0x08 38#define SPI_ADRS_HOST_INT_EN 0x0c 39#define SPI_ADRS_HOST_INT_ACK 0x10 40 41#define SPI_ADRS_GEN_PURP_1 0x14 42#define SPI_ADRS_GEN_PURP_2 0x18 43 44#define SPI_ADRS_DEV_CTRL_STAT 0x26 /* high word */ 45 46#define SPI_ADRS_DMA_DATA 0x28 47 48#define SPI_ADRS_DMA_WRITE_CTRL 0x2c 49#define SPI_ADRS_DMA_WRITE_LEN 0x2e 50#define SPI_ADRS_DMA_WRITE_BASE 0x30 51 52#define SPI_ADRS_DMA_READ_CTRL 0x34 53#define SPI_ADRS_DMA_READ_LEN 0x36 54#define SPI_ADRS_DMA_READ_BASE 0x38 55 56#define SPI_CTRL_STAT_HOST_OVERRIDE 0x8000 57#define SPI_CTRL_STAT_START_HALTED 0x4000 58#define SPI_CTRL_STAT_RAM_BOOT 0x2000 59#define SPI_CTRL_STAT_HOST_RESET 0x1000 60#define SPI_CTRL_STAT_HOST_CPU_EN 0x0800 61 62#define SPI_DMA_WRITE_CTRL_ENABLE 0x0001 63#define SPI_DMA_READ_CTRL_ENABLE 0x0001 64#define HOST_ALLOWED (1 << 7) 65 66#define SPI_TIMEOUT 100 /* msec */ 67 68#define SPI_MAX_TX_PACKETS 32 69 70#define SPI_MAX_PACKET_SIZE 32767 71 72#define SPI_TARGET_INT_WAKEUP 0x00000001 73#define SPI_TARGET_INT_SLEEP 0x00000002 74#define SPI_TARGET_INT_RDDONE 0x00000004 75 76#define SPI_TARGET_INT_CTS 0x00004000 77#define SPI_TARGET_INT_DR 0x00008000 78 79#define SPI_HOST_INT_READY 0x00000001 80#define SPI_HOST_INT_WR_READY 0x00000002 81#define SPI_HOST_INT_SW_UPDATE 0x00000004 82#define SPI_HOST_INT_UPDATE 0x10000000 83 84/* clear to send */ 85#define SPI_HOST_INT_CR 0x00004000 86 87/* data ready */ 88#define SPI_HOST_INT_DR 0x00008000 89 90#define SPI_HOST_INTS_DEFAULT \ 91 (SPI_HOST_INT_READY | SPI_HOST_INT_UPDATE | SPI_HOST_INT_SW_UPDATE) 92 93#define TARGET_BOOT_SLEEP 50 94 95struct p54s_dma_regs { 96 __le16 cmd; 97 __le16 len; 98 __le32 addr; 99} __packed; 100 101struct p54s_tx_info { 102 struct list_head tx_list; 103}; 104 105struct p54s_priv { 106 /* p54_common has to be the first entry */ 107 struct p54_common common; 108 struct ieee80211_hw *hw; 109 struct spi_device *spi; 110 111 struct work_struct work; 112 113 struct mutex mutex; 114 struct completion fw_comp; 115 116 spinlock_t tx_lock; 117 118 /* protected by tx_lock */ 119 struct list_head tx_pending; 120 121 enum fw_state fw_state; 122 const struct firmware *firmware; 123}; 124 125#endif /* P54SPI_H */ 126