LXR linux/drivers/net/wireless/realtek/rtlwifi/pci.h

   1/******************************************************************************
   2 *
   3 * Copyright(c) 2009-2012  Realtek Corporation.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of version 2 of the GNU General Public License as
   7 * published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12 * more details.
  13 *
  14 * The full GNU General Public License is included in this distribution in the
  15 * file called LICENSE.
  16 *
  17 * Contact Information:
  18 * wlanfae <wlanfae@realtek.com>
  19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20 * Hsinchu 300, Taiwan.
  21 *
  22 * Larry Finger <Larry.Finger@lwfinger.net>
  23 *
  24 *****************************************************************************/
  25
  26#ifndef __RTL_PCI_H__
  27#define __RTL_PCI_H__
  28
  29#include <linux/pci.h>
  30/*
  311: MSDU packet queue,
  322: Rx Command Queue
  33*/
  34#define RTL_PCI_RX_MPDU_QUEUE                   0
  35#define RTL_PCI_RX_CMD_QUEUE                    1
  36#define RTL_PCI_MAX_RX_QUEUE                    2
  37
  38#define RTL_PCI_MAX_RX_COUNT                    512/*64*/
  39#define RTL_PCI_MAX_TX_QUEUE_COUNT              9
  40
  41#define RT_TXDESC_NUM                           128
  42#define TX_DESC_NUM_92E                         512
  43#define RT_TXDESC_NUM_BE_QUEUE                  256
  44
  45#define BK_QUEUE                                0
  46#define BE_QUEUE                                1
  47#define VI_QUEUE                                2
  48#define VO_QUEUE                                3
  49#define BEACON_QUEUE                            4
  50#define TXCMD_QUEUE                             5
  51#define MGNT_QUEUE                              6
  52#define HIGH_QUEUE                              7
  53#define HCCA_QUEUE                              8
  54
  55#define RTL_PCI_DEVICE(vend, dev, cfg)  \
  56        .vendor = (vend), \
  57        .device = (dev), \
  58        .subvendor = PCI_ANY_ID, \
  59        .subdevice = PCI_ANY_ID,\
  60        .driver_data = (kernel_ulong_t)&(cfg)
  61
  62#define INTEL_VENDOR_ID                         0x8086
  63#define SIS_VENDOR_ID                           0x1039
  64#define ATI_VENDOR_ID                           0x1002
  65#define ATI_DEVICE_ID                           0x7914
  66#define AMD_VENDOR_ID                           0x1022
  67
  68#define PCI_MAX_BRIDGE_NUMBER                   255
  69#define PCI_MAX_DEVICES                         32
  70#define PCI_MAX_FUNCTION                        8
  71
  72#define PCI_CONF_ADDRESS        0x0CF8  /*PCI Configuration Space Address */
  73#define PCI_CONF_DATA           0x0CFC  /*PCI Configuration Space Data */
  74
  75#define PCI_CLASS_BRIDGE_DEV            0x06
  76#define PCI_SUBCLASS_BR_PCI_TO_PCI      0x04
  77#define PCI_CAPABILITY_ID_PCI_EXPRESS   0x10
  78#define PCI_CAP_ID_EXP                  0x10
  79
  80#define U1DONTCARE                      0xFF
  81#define U2DONTCARE                      0xFFFF
  82#define U4DONTCARE                      0xFFFFFFFF
  83
  84#define RTL_PCI_8192_DID        0x8192  /*8192 PCI-E */
  85#define RTL_PCI_8192SE_DID      0x8192  /*8192 SE */
  86#define RTL_PCI_8174_DID        0x8174  /*8192 SE */
  87#define RTL_PCI_8173_DID        0x8173  /*8191 SE Crab */
  88#define RTL_PCI_8172_DID        0x8172  /*8191 SE RE */
  89#define RTL_PCI_8171_DID        0x8171  /*8191 SE Unicron */
  90#define RTL_PCI_8723AE_DID      0x8723  /*8723AE */
  91#define RTL_PCI_0045_DID        0x0045  /*8190 PCI for Ceraga */
  92#define RTL_PCI_0046_DID        0x0046  /*8190 Cardbus for Ceraga */
  93#define RTL_PCI_0044_DID        0x0044  /*8192e PCIE for Ceraga */
  94#define RTL_PCI_0047_DID        0x0047  /*8192e Express Card for Ceraga */
  95#define RTL_PCI_700F_DID        0x700F
  96#define RTL_PCI_701F_DID        0x701F
  97#define RTL_PCI_DLINK_DID       0x3304
  98#define RTL_PCI_8723AE_DID      0x8723  /*8723e */
  99#define RTL_PCI_8192CET_DID     0x8191  /*8192ce */
 100#define RTL_PCI_8192CE_DID      0x8178  /*8192ce */
 101#define RTL_PCI_8191CE_DID      0x8177  /*8192ce */
 102#define RTL_PCI_8188CE_DID      0x8176  /*8192ce */
 103#define RTL_PCI_8192CU_DID      0x8191  /*8192ce */
 104#define RTL_PCI_8192DE_DID      0x8193  /*8192de */
 105#define RTL_PCI_8192DE_DID2     0x002B  /*92DE*/
 106#define RTL_PCI_8188EE_DID      0x8179  /*8188ee*/
 107#define RTL_PCI_8723BE_DID      0xB723  /*8723be*/
 108#define RTL_PCI_8192EE_DID      0x818B  /*8192ee*/
 109#define RTL_PCI_8821AE_DID      0x8821  /*8821ae*/
 110#define RTL_PCI_8812AE_DID      0x8812  /*8812ae*/
 111
 112/*8192 support 16 pages of IO registers*/
 113#define RTL_MEM_MAPPED_IO_RANGE_8190PCI         0x1000
 114#define RTL_MEM_MAPPED_IO_RANGE_8192PCIE        0x4000
 115#define RTL_MEM_MAPPED_IO_RANGE_8192SE          0x4000
 116#define RTL_MEM_MAPPED_IO_RANGE_8192CE          0x4000
 117#define RTL_MEM_MAPPED_IO_RANGE_8192DE          0x4000
 118
 119#define RTL_PCI_REVISION_ID_8190PCI             0x00
 120#define RTL_PCI_REVISION_ID_8192PCIE            0x01
 121#define RTL_PCI_REVISION_ID_8192SE              0x10
 122#define RTL_PCI_REVISION_ID_8192CE              0x1
 123#define RTL_PCI_REVISION_ID_8192DE              0x0
 124
 125#define RTL_DEFAULT_HARDWARE_TYPE       HARDWARE_TYPE_RTL8192CE
 126
 127enum pci_bridge_vendor {
 128        PCI_BRIDGE_VENDOR_INTEL = 0x0,  /*0b'0000,0001 */
 129        PCI_BRIDGE_VENDOR_ATI,          /*0b'0000,0010*/
 130        PCI_BRIDGE_VENDOR_AMD,          /*0b'0000,0100*/
 131        PCI_BRIDGE_VENDOR_SIS,          /*0b'0000,1000*/
 132        PCI_BRIDGE_VENDOR_UNKNOWN,      /*0b'0100,0000*/
 133        PCI_BRIDGE_VENDOR_MAX,
 134};
 135
 136struct rtl_pci_capabilities_header {
 137        u8 capability_id;
 138        u8 next;
 139};
 140
 141/* In new TRX flow, Buffer_desc is new concept
 142 * But TX wifi info == TX descriptor in old flow
 143 * RX wifi info == RX descriptor in old flow
 144 */
 145struct rtl_tx_buffer_desc {
 146#if (RTL8192EE_SEG_NUM == 2)
 147        u32 dword[2*(DMA_IS_64BIT + 1)*8]; /*seg = 8*/
 148#elif (RTL8192EE_SEG_NUM == 1)
 149        u32 dword[2*(DMA_IS_64BIT + 1)*4]; /*seg = 4*/
 150#elif (RTL8192EE_SEG_NUM == 0)
 151        u32 dword[2*(DMA_IS_64BIT + 1)*2]; /*seg = 2*/
 152#endif
 153} __packed;
 154
 155struct rtl_tx_desc {
 156        u32 dword[16];
 157} __packed;
 158
 159struct rtl_rx_buffer_desc { /*rx buffer desc*/
 160        u32 dword[2];
 161} __packed;
 162
 163struct rtl_rx_desc { /*old: rx desc new: rx wifi info*/
 164        u32 dword[8];
 165} __packed;
 166
 167struct rtl_tx_cmd_desc {
 168        u32 dword[16];
 169} __packed;
 170
 171struct rtl8192_tx_ring {
 172        struct rtl_tx_desc *desc;
 173        dma_addr_t dma;
 174        unsigned int idx;
 175        unsigned int entries;
 176        struct sk_buff_head queue;
 177        /*add for new trx flow*/
 178        struct rtl_tx_buffer_desc *buffer_desc; /*tx buffer descriptor*/
 179        dma_addr_t buffer_desc_dma; /*tx bufferd desc dma memory*/
 180        u16 avl_desc; /* available_desc_to_write */
 181        u16 cur_tx_wp; /* current_tx_write_point */
 182        u16 cur_tx_rp; /* current_tx_read_point */
 183};
 184
 185struct rtl8192_rx_ring {
 186        struct rtl_rx_desc *desc;
 187        dma_addr_t dma;
 188        unsigned int idx;
 189        struct sk_buff *rx_buf[RTL_PCI_MAX_RX_COUNT];
 190        /*add for new trx flow*/
 191        struct rtl_rx_buffer_desc *buffer_desc; /*rx buffer descriptor*/
 192        u16 next_rx_rp; /* next_rx_read_point */
 193};
 194
 195struct rtl_pci {
 196        struct pci_dev *pdev;
 197        bool irq_enabled;
 198
 199        bool driver_is_goingto_unload;
 200        bool up_first_time;
 201        bool first_init;
 202        bool being_init_adapter;
 203        bool init_ready;
 204
 205        /*Tx */
 206        struct rtl8192_tx_ring tx_ring[RTL_PCI_MAX_TX_QUEUE_COUNT];
 207        int txringcount[RTL_PCI_MAX_TX_QUEUE_COUNT];
 208        u32 transmit_config;
 209
 210        /*Rx */
 211        struct rtl8192_rx_ring rx_ring[RTL_PCI_MAX_RX_QUEUE];
 212        int rxringcount;
 213        u16 rxbuffersize;
 214        u32 receive_config;
 215
 216        /*irq */
 217        u8 irq_alloc;
 218        u32 irq_mask[2];
 219        u32 sys_irq_mask;
 220
 221        /*Bcn control register setting */
 222        u32 reg_bcn_ctrl_val;
 223
 224         /*ASPM*/ u8 const_pci_aspm;
 225        u8 const_amdpci_aspm;
 226        u8 const_hwsw_rfoff_d3;
 227        u8 const_support_pciaspm;
 228        /*pci-e bridge */
 229        u8 const_hostpci_aspm_setting;
 230        /*pci-e device */
 231        u8 const_devicepci_aspm_setting;
 232        /*If it supports ASPM, Offset[560h] = 0x40,
 233           otherwise Offset[560h] = 0x00. */
 234        bool support_aspm;
 235        bool support_backdoor;
 236
 237        /*QOS & EDCA */
 238        enum acm_method acm_method;
 239
 240        u16 shortretry_limit;
 241        u16 longretry_limit;
 242
 243        /* MSI support */
 244        bool msi_support;
 245        bool using_msi;
 246        /* interrupt clear before set */
 247        bool int_clear;
 248};
 249
 250struct mp_adapter {
 251        u8 linkctrl_reg;
 252
 253        u8 busnumber;
 254        u8 devnumber;
 255        u8 funcnumber;
 256
 257        u8 pcibridge_busnum;
 258        u8 pcibridge_devnum;
 259        u8 pcibridge_funcnum;
 260
 261        u8 pcibridge_vendor;
 262        u16 pcibridge_vendorid;
 263        u16 pcibridge_deviceid;
 264
 265        u8 num4bytes;
 266
 267        u8 pcibridge_pciehdr_offset;
 268        u8 pcibridge_linkctrlreg;
 269
 270        bool amd_l1_patch;
 271};
 272
 273struct rtl_pci_priv {
 274        struct bt_coexist_info bt_coexist;
 275        struct rtl_led_ctl ledctl;
 276        struct rtl_pci dev;
 277        struct mp_adapter ndis_adapter;
 278};
 279
 280#define rtl_pcipriv(hw)         (((struct rtl_pci_priv *)(rtl_priv(hw))->priv))
 281#define rtl_pcidev(pcipriv)     (&((pcipriv)->dev))
 282
 283int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw);
 284
 285extern const struct rtl_intf_ops rtl_pci_ops;
 286
 287int rtl_pci_probe(struct pci_dev *pdev,
 288                            const struct pci_device_id *id);
 289void rtl_pci_disconnect(struct pci_dev *pdev);
 290#ifdef CONFIG_PM_SLEEP
 291int rtl_pci_suspend(struct device *dev);
 292int rtl_pci_resume(struct device *dev);
 293#endif /* CONFIG_PM_SLEEP */
 294static inline u8 pci_read8_sync(struct rtl_priv *rtlpriv, u32 addr)
 295{
 296        return readb((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
 297}
 298
 299static inline u16 pci_read16_sync(struct rtl_priv *rtlpriv, u32 addr)
 300{
 301        return readw((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
 302}
 303
 304static inline u32 pci_read32_sync(struct rtl_priv *rtlpriv, u32 addr)
 305{
 306        return readl((u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
 307}
 308
 309static inline void pci_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val)
 310{
 311        writeb(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
 312}
 313
 314static inline void pci_write16_async(struct rtl_priv *rtlpriv,
 315                                     u32 addr, u16 val)
 316{
 317        writew(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
 318}
 319
 320static inline void pci_write32_async(struct rtl_priv *rtlpriv,
 321                                     u32 addr, u32 val)
 322{
 323        writel(val, (u8 __iomem *) rtlpriv->io.pci_mem_start + addr);
 324}
 325
 326static inline u16 calc_fifo_space(u16 rp, u16 wp)
 327{
 328        if (rp <= wp)
 329                return RTL_PCI_MAX_RX_COUNT - 1 + rp - wp;
 330        return rp - wp - 1;
 331}
 332
 333#endif
 334