1/****************************************************************************** 2 * 3 * Copyright(c) 2009-2012 Realtek Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * The full GNU General Public License is included in this distribution in the 15 * file called LICENSE. 16 * 17 * Contact Information: 18 * wlanfae <wlanfae@realtek.com> 19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park, 20 * Hsinchu 300, Taiwan. 21 * 22 * Larry Finger <Larry.Finger@lwfinger.net> 23 * 24 *****************************************************************************/ 25 26#ifndef __RTL92C_REG_H__ 27#define __RTL92C_REG_H__ 28 29#define REG_SYS_ISO_CTRL 0x0000 30#define REG_SYS_FUNC_EN 0x0002 31#define REG_APS_FSMCO 0x0004 32#define REG_SYS_CLKR 0x0008 33#define REG_9346CR 0x000A 34#define REG_EE_VPD 0x000C 35#define REG_AFE_MISC 0x0010 36#define REG_SPS0_CTRL 0x0011 37#define REG_SPS_OCP_CFG 0x0018 38#define REG_RSV_CTRL 0x001C 39#define REG_RF_CTRL 0x001F 40#define REG_LDOA15_CTRL 0x0020 41#define REG_LDOV12D_CTRL 0x0021 42#define REG_LDOHCI12_CTRL 0x0022 43#define REG_LPLDO_CTRL 0x0023 44#define REG_AFE_XTAL_CTRL 0x0024 45#define REG_AFE_PLL_CTRL 0x0028 46#define REG_EFUSE_CTRL 0x0030 47#define REG_EFUSE_TEST 0x0034 48#define REG_PWR_DATA 0x0038 49#define REG_CAL_TIMER 0x003C 50#define REG_ACLK_MON 0x003E 51#define REG_GPIO_MUXCFG 0x0040 52#define REG_GPIO_IO_SEL 0x0042 53#define REG_MAC_PINMUX_CFG 0x0043 54#define REG_GPIO_PIN_CTRL 0x0044 55#define REG_GPIO_INTM 0x0048 56#define REG_LEDCFG0 0x004C 57#define REG_LEDCFG1 0x004D 58#define REG_LEDCFG2 0x004E 59#define REG_LEDCFG3 0x004F 60#define REG_FSIMR 0x0050 61#define REG_FSISR 0x0054 62#define REG_HSIMR 0x0058 63#define REG_HSISR 0x005c 64 65/* RTL8723 WIFI/BT/GPS Multi-Function GPIO Pin Control. */ 66#define REG_GPIO_PIN_CTRL_2 0x0060 67/* RTL8723 WIFI/BT/GPS Multi-Function GPIO Select. */ 68#define REG_GPIO_IO_SEL_2 0x0062 69/* RTL8723 WIFI/BT/GPS Multi-Function control source. */ 70#define REG_MULTI_FUNC_CTRL 0x0068 71 72#define REG_MCUFWDL 0x0080 73 74#define REG_HMEBOX_EXT_0 0x0088 75#define REG_HMEBOX_EXT_1 0x008A 76#define REG_HMEBOX_EXT_2 0x008C 77#define REG_HMEBOX_EXT_3 0x008E 78 79#define REG_BIST_SCAN 0x00D0 80#define REG_BIST_RPT 0x00D4 81#define REG_BIST_ROM_RPT 0x00D8 82#define REG_USB_SIE_INTF 0x00E0 83#define REG_PCIE_MIO_INTF 0x00E4 84#define REG_PCIE_MIO_INTD 0x00E8 85#define REG_HPON_FSM 0x00EC 86#define REG_SYS_CFG 0x00F0 87#define REG_GPIO_OUTSTS 0x00F4 /* For RTL8723 only.*/ 88 89#define REG_CR 0x0100 90#define REG_PBP 0x0104 91#define REG_TRXDMA_CTRL 0x010C 92#define REG_TRXFF_BNDY 0x0114 93#define REG_TRXFF_STATUS 0x0118 94#define REG_RXFF_PTR 0x011C 95#define REG_HIMR 0x0120 96#define REG_HISR 0x0124 97#define REG_HIMRE 0x0128 98#define REG_HISRE 0x012C 99#define REG_CPWM 0x012F 100#define REG_FWIMR 0x0130 101#define REG_FWISR 0x0134 102#define REG_PKTBUF_DBG_CTRL 0x0140 103#define REG_PKTBUF_DBG_DATA_L 0x0144 104#define REG_PKTBUF_DBG_DATA_H 0x0148 105 106#define REG_TC0_CTRL 0x0150 107#define REG_TC1_CTRL 0x0154 108#define REG_TC2_CTRL 0x0158 109#define REG_TC3_CTRL 0x015C 110#define REG_TC4_CTRL 0x0160 111#define REG_TCUNIT_BASE 0x0164 112#define REG_MBIST_START 0x0174 113#define REG_MBIST_DONE 0x0178 114#define REG_MBIST_FAIL 0x017C 115#define REG_C2HEVT_MSG_NORMAL 0x01A0 116#define REG_C2HEVT_MSG_TEST 0x01B8 117#define REG_C2HEVT_CLEAR 0x01BF 118#define REG_MCUTST_1 0x01c0 119#define REG_FMETHR 0x01C8 120#define REG_HMETFR 0x01CC 121#define REG_HMEBOX_0 0x01D0 122#define REG_HMEBOX_1 0x01D4 123#define REG_HMEBOX_2 0x01D8 124#define REG_HMEBOX_3 0x01DC 125 126#define REG_LLT_INIT 0x01E0 127#define REG_BB_ACCEESS_CTRL 0x01E8 128#define REG_BB_ACCESS_DATA 0x01EC 129 130#define REG_RQPN 0x0200 131#define REG_FIFOPAGE 0x0204 132#define REG_TDECTRL 0x0208 133#define REG_TXDMA_OFFSET_CHK 0x020C 134#define REG_TXDMA_STATUS 0x0210 135#define REG_RQPN_NPQ 0x0214 136 137#define REG_RXDMA_AGG_PG_TH 0x0280 138#define REG_RXPKT_NUM 0x0284 139#define REG_RXDMA_STATUS 0x0288 140 141#define REG_PCIE_CTRL_REG 0x0300 142#define REG_INT_MIG 0x0304 143#define REG_BCNQ_DESA 0x0308 144#define REG_HQ_DESA 0x0310 145#define REG_MGQ_DESA 0x0318 146#define REG_VOQ_DESA 0x0320 147#define REG_VIQ_DESA 0x0328 148#define REG_BEQ_DESA 0x0330 149#define REG_BKQ_DESA 0x0338 150#define REG_RX_DESA 0x0340 151#define REG_DBI 0x0348 152#define REG_MDIO 0x0354 153#define REG_DBG_SEL 0x0360 154#define REG_PCIE_HRPWM 0x0361 155#define REG_PCIE_HCPWM 0x0363 156#define REG_UART_CTRL 0x0364 157#define REG_UART_TX_DESA 0x0370 158#define REG_UART_RX_DESA 0x0378 159 160#define REG_HDAQ_DESA_NODEF 0x0000 161#define REG_CMDQ_DESA_NODEF 0x0000 162 163#define REG_VOQ_INFORMATION 0x0400 164#define REG_VIQ_INFORMATION 0x0404 165#define REG_BEQ_INFORMATION 0x0408 166#define REG_BKQ_INFORMATION 0x040C 167#define REG_MGQ_INFORMATION 0x0410 168#define REG_HGQ_INFORMATION 0x0414 169#define REG_BCNQ_INFORMATION 0x0418 170 171#define REG_CPU_MGQ_INFORMATION 0x041C 172#define REG_FWHW_TXQ_CTRL 0x0420 173#define REG_HWSEQ_CTRL 0x0423 174#define REG_TXPKTBUF_BCNQ_BDNY 0x0424 175#define REG_TXPKTBUF_MGQ_BDNY 0x0425 176#define REG_MULTI_BCNQ_EN 0x0426 177#define REG_MULTI_BCNQ_OFFSET 0x0427 178#define REG_SPEC_SIFS 0x0428 179#define REG_RL 0x042A 180#define REG_DARFRC 0x0430 181#define REG_RARFRC 0x0438 182#define REG_RRSR 0x0440 183#define REG_ARFR0 0x0444 184#define REG_ARFR1 0x0448 185#define REG_ARFR2 0x044C 186#define REG_ARFR3 0x0450 187#define REG_AGGLEN_LMT 0x0458 188#define REG_AMPDU_MIN_SPACE 0x045C 189#define REG_TXPKTBUF_WMAC_LBK_BF_HD 0x045D 190#define REG_FAST_EDCA_CTRL 0x0460 191#define REG_RD_RESP_PKT_TH 0x0463 192#define REG_INIRTS_RATE_SEL 0x0480 193#define REG_INIDATA_RATE_SEL 0x0484 194#define REG_POWER_STATUS 0x04A4 195#define REG_POWER_STAGE1 0x04B4 196#define REG_POWER_STAGE2 0x04B8 197#define REG_PKT_LIFE_TIME 0x04C0 198#define REG_STBC_SETTING 0x04C4 199#define REG_PROT_MODE_CTRL 0x04C8 200#define REG_BAR_MODE_CTRL 0x04CC 201#define REG_RA_TRY_RATE_AGG_LMT 0x04CF 202#define REG_NQOS_SEQ 0x04DC 203#define REG_QOS_SEQ 0x04DE 204#define REG_NEED_CPU_HANDLE 0x04E0 205#define REG_PKT_LOSE_RPT 0x04E1 206#define REG_PTCL_ERR_STATUS 0x04E2 207#define REG_DUMMY 0x04FC 208 209#define REG_EDCA_VO_PARAM 0x0500 210#define REG_EDCA_VI_PARAM 0x0504 211#define REG_EDCA_BE_PARAM 0x0508 212#define REG_EDCA_BK_PARAM 0x050C 213#define REG_BCNTCFG 0x0510 214#define REG_PIFS 0x0512 215#define REG_RDG_PIFS 0x0513 216#define REG_SIFS_CTX 0x0514 217#define REG_SIFS_TRX 0x0516 218#define REG_SIFS_CCK 0x0514 219#define REG_SIFS_OFDM 0x0516 220#define REG_AGGR_BREAK_TIME 0x051A 221#define REG_SLOT 0x051B 222#define REG_TX_PTCL_CTRL 0x0520 223#define REG_TXPAUSE 0x0522 224#define REG_DIS_TXREQ_CLR 0x0523 225#define REG_RD_CTRL 0x0524 226#define REG_TBTT_PROHIBIT 0x0540 227#define REG_RD_NAV_NXT 0x0544 228#define REG_NAV_PROT_LEN 0x0546 229#define REG_BCN_CTRL 0x0550 230#define REG_MBID_NUM 0x0552 231#define REG_DUAL_TSF_RST 0x0553 232#define REG_BCN_INTERVAL 0x0554 233#define REG_MBSSID_BCN_SPACE 0x0554 234#define REG_DRVERLYINT 0x0558 235#define REG_BCNDMATIM 0x0559 236#define REG_ATIMWND 0x055A 237#define REG_USTIME_TSF 0x055C 238#define REG_BCN_MAX_ERR 0x055D 239#define REG_RXTSF_OFFSET_CCK 0x055E 240#define REG_RXTSF_OFFSET_OFDM 0x055F 241#define REG_TSFTR 0x0560 242#define REG_INIT_TSFTR 0x0564 243#define REG_PSTIMER 0x0580 244#define REG_TIMER0 0x0584 245#define REG_TIMER1 0x0588 246#define REG_ACMHWCTRL 0x05C0 247#define REG_ACMRSTCTRL 0x05C1 248#define REG_ACMAVG 0x05C2 249#define REG_VO_ADMTIME 0x05C4 250#define REG_VI_ADMTIME 0x05C6 251#define REG_BE_ADMTIME 0x05C8 252#define REG_EDCA_RANDOM_GEN 0x05CC 253#define REG_SCH_TXCMD 0x05D0 254 255#define REG_APSD_CTRL 0x0600 256#define REG_BWOPMODE 0x0603 257#define REG_TCR 0x0604 258#define REG_RCR 0x0608 259#define REG_RX_PKT_LIMIT 0x060C 260#define REG_RX_DLK_TIME 0x060D 261#define REG_RX_DRVINFO_SZ 0x060F 262 263#define REG_MACID 0x0610 264#define REG_BSSID 0x0618 265#define REG_MAR 0x0620 266#define REG_MBIDCAMCFG 0x0628 267 268#define REG_USTIME_EDCA 0x0638 269#define REG_MAC_SPEC_SIFS 0x063A 270#define REG_RESP_SIFS_CCK 0x063C 271#define REG_RESP_SIFS_OFDM 0x063E 272/* [15:8]SIFS_R2T_OFDM, [7:0]SIFS_R2T_CCK */ 273#define REG_R2T_SIFS 0x063C 274/* [15:8]SIFS_T2T_OFDM, [7:0]SIFS_T2T_CCK */ 275#define REG_T2T_SIFS 0x063E 276#define REG_ACKTO 0x0640 277#define REG_CTS2TO 0x0641 278#define REG_EIFS 0x0642 279 280#define REG_NAV_CTRL 0x0650 281#define REG_BACAMCMD 0x0654 282#define REG_BACAMCONTENT 0x0658 283#define REG_LBDLY 0x0660 284#define REG_FWDLY 0x0661 285#define REG_RXERR_RPT 0x0664 286#define REG_WMAC_TRXPTCL_CTL 0x0668 287 288#define REG_CAMCMD 0x0670 289#define REG_CAMWRITE 0x0674 290#define REG_CAMREAD 0x0678 291#define REG_CAMDBG 0x067C 292#define REG_SECCFG 0x0680 293 294#define REG_WOW_CTRL 0x0690 295#define REG_PSSTATUS 0x0691 296#define REG_PS_RX_INFO 0x0692 297#define REG_LPNAV_CTRL 0x0694 298#define REG_WKFMCAM_CMD 0x0698 299#define REG_WKFMCAM_RWD 0x069C 300#define REG_RXFLTMAP0 0x06A0 301#define REG_RXFLTMAP1 0x06A2 302#define REG_RXFLTMAP2 0x06A4 303#define REG_BCN_PSR_RPT 0x06A8 304#define REG_CALB32K_CTRL 0x06AC 305#define REG_PKT_MON_CTRL 0x06B4 306#define REG_BT_COEX_TABLE 0x06C0 307#define REG_WMAC_RESP_TXINFO 0x06D8 308 309#define REG_USB_INFO 0xFE17 310#define REG_USB_SPECIAL_OPTION 0xFE55 311#define REG_USB_DMA_AGG_TO 0xFE5B 312#define REG_USB_AGG_TO 0xFE5C 313#define REG_USB_AGG_TH 0xFE5D 314 315#define REG_TEST_USB_TXQS 0xFE48 316#define REG_TEST_SIE_VID 0xFE60 317#define REG_TEST_SIE_PID 0xFE62 318#define REG_TEST_SIE_OPTIONAL 0xFE64 319#define REG_TEST_SIE_CHIRP_K 0xFE65 320#define REG_TEST_SIE_PHY 0xFE66 321#define REG_TEST_SIE_MAC_ADDR 0xFE70 322#define REG_TEST_SIE_STRING 0xFE80 323 324#define REG_NORMAL_SIE_VID 0xFE60 325#define REG_NORMAL_SIE_PID 0xFE62 326#define REG_NORMAL_SIE_OPTIONAL 0xFE64 327#define REG_NORMAL_SIE_EP 0xFE65 328#define REG_NORMAL_SIE_PHY 0xFE68 329#define REG_NORMAL_SIE_MAC_ADDR 0xFE70 330#define REG_NORMAL_SIE_STRING 0xFE80 331 332#define CR9346 REG_9346CR 333#define MSR (REG_CR + 2) 334#define ISR REG_HISR 335#define TSFR REG_TSFTR 336 337#define MACIDR0 REG_MACID 338#define MACIDR4 (REG_MACID + 4) 339 340#define PBP REG_PBP 341 342#define IDR0 MACIDR0 343#define IDR4 MACIDR4 344 345#define UNUSED_REGISTER 0x1BF 346#define DCAM UNUSED_REGISTER 347#define PSR UNUSED_REGISTER 348#define BBADDR UNUSED_REGISTER 349#define PHYDATAR UNUSED_REGISTER 350 351#define INVALID_BBRF_VALUE 0x12345678 352 353#define MAX_MSS_DENSITY_2T 0x13 354#define MAX_MSS_DENSITY_1T 0x0A 355 356#define CMDEEPROM_EN BIT(5) 357#define CMDEEPROM_SEL BIT(4) 358#define CMD9346CR_9356SEL BIT(4) 359#define AUTOLOAD_EEPROM (CMDEEPROM_EN|CMDEEPROM_SEL) 360#define AUTOLOAD_EFUSE CMDEEPROM_EN 361 362#define GPIOSEL_GPIO 0 363#define GPIOSEL_ENBT BIT(5) 364 365#define GPIO_IN REG_GPIO_PIN_CTRL 366#define GPIO_OUT (REG_GPIO_PIN_CTRL+1) 367#define GPIO_IO_SEL (REG_GPIO_PIN_CTRL+2) 368#define GPIO_MOD (REG_GPIO_PIN_CTRL+3) 369 370#define MSR_NOLINK 0x00 371#define MSR_ADHOC 0x01 372#define MSR_INFRA 0x02 373#define MSR_AP 0x03 374#define MSR_MASK 0x03 375 376#define RRSR_RSC_OFFSET 21 377#define RRSR_SHORT_OFFSET 23 378#define RRSR_RSC_BW_40M 0x600000 379#define RRSR_RSC_UPSUBCHNL 0x400000 380#define RRSR_RSC_LOWSUBCHNL 0x200000 381#define RRSR_SHORT 0x800000 382#define RRSR_1M BIT(0) 383#define RRSR_2M BIT(1) 384#define RRSR_5_5M BIT(2) 385#define RRSR_11M BIT(3) 386#define RRSR_6M BIT(4) 387#define RRSR_9M BIT(5) 388#define RRSR_12M BIT(6) 389#define RRSR_18M BIT(7) 390#define RRSR_24M BIT(8) 391#define RRSR_36M BIT(9) 392#define RRSR_48M BIT(10) 393#define RRSR_54M BIT(11) 394#define RRSR_MCS0 BIT(12) 395#define RRSR_MCS1 BIT(13) 396#define RRSR_MCS2 BIT(14) 397#define RRSR_MCS3 BIT(15) 398#define RRSR_MCS4 BIT(16) 399#define RRSR_MCS5 BIT(17) 400#define RRSR_MCS6 BIT(18) 401#define RRSR_MCS7 BIT(19) 402#define BRSR_ACKSHORTPMB BIT(23) 403 404#define RATR_1M 0x00000001 405#define RATR_2M 0x00000002 406#define RATR_55M 0x00000004 407#define RATR_11M 0x00000008 408#define RATR_6M 0x00000010 409#define RATR_9M 0x00000020 410#define RATR_12M 0x00000040 411#define RATR_18M 0x00000080 412#define RATR_24M 0x00000100 413#define RATR_36M 0x00000200 414#define RATR_48M 0x00000400 415#define RATR_54M 0x00000800 416#define RATR_MCS0 0x00001000 417#define RATR_MCS1 0x00002000 418#define RATR_MCS2 0x00004000 419#define RATR_MCS3 0x00008000 420#define RATR_MCS4 0x00010000 421#define RATR_MCS5 0x00020000 422#define RATR_MCS6 0x00040000 423#define RATR_MCS7 0x00080000 424#define RATR_MCS8 0x00100000 425#define RATR_MCS9 0x00200000 426#define RATR_MCS10 0x00400000 427#define RATR_MCS11 0x00800000 428#define RATR_MCS12 0x01000000 429#define RATR_MCS13 0x02000000 430#define RATR_MCS14 0x04000000 431#define RATR_MCS15 0x08000000 432 433#define RATE_1M BIT(0) 434#define RATE_2M BIT(1) 435#define RATE_5_5M BIT(2) 436#define RATE_11M BIT(3) 437#define RATE_6M BIT(4) 438#define RATE_9M BIT(5) 439#define RATE_12M BIT(6) 440#define RATE_18M BIT(7) 441#define RATE_24M BIT(8) 442#define RATE_36M BIT(9) 443#define RATE_48M BIT(10) 444#define RATE_54M BIT(11) 445#define RATE_MCS0 BIT(12) 446#define RATE_MCS1 BIT(13) 447#define RATE_MCS2 BIT(14) 448#define RATE_MCS3 BIT(15) 449#define RATE_MCS4 BIT(16) 450#define RATE_MCS5 BIT(17) 451#define RATE_MCS6 BIT(18) 452#define RATE_MCS7 BIT(19) 453#define RATE_MCS8 BIT(20) 454#define RATE_MCS9 BIT(21) 455#define RATE_MCS10 BIT(22) 456#define RATE_MCS11 BIT(23) 457#define RATE_MCS12 BIT(24) 458#define RATE_MCS13 BIT(25) 459#define RATE_MCS14 BIT(26) 460#define RATE_MCS15 BIT(27) 461 462#define RATE_ALL_CCK (RATR_1M | RATR_2M | RATR_55M | RATR_11M) 463#define RATE_ALL_OFDM_AG (RATR_6M | RATR_9M | RATR_12M | RATR_18M \ 464 | RATR_24M | RATR_36M | RATR_48M | RATR_54M) 465#define RATE_ALL_OFDM_1SS (RATR_MCS0 | RATR_MCS1 | RATR_MCS2 | \ 466 RATR_MCS3 | RATR_MCS4 | RATR_MCS5 | \ 467 RATR_MCS6 | RATR_MCS7) 468#define RATE_ALL_OFDM_2SS (RATR_MCS8 | RATR_MCS9 | RATR_MCS10 | \ 469 RATR_MCS11 | RATR_MCS12 | RATR_MCS13 | \ 470 RATR_MCS14 | RATR_MCS15) 471 472#define BW_OPMODE_20MHZ BIT(2) 473#define BW_OPMODE_5G BIT(1) 474#define BW_OPMODE_11J BIT(0) 475 476#define CAM_VALID BIT(15) 477#define CAM_NOTVALID 0x0000 478#define CAM_USEDK BIT(5) 479 480#define CAM_NONE 0x0 481#define CAM_WEP40 0x01 482#define CAM_TKIP 0x02 483#define CAM_AES 0x04 484#define CAM_WEP104 0x05 485 486#define TOTAL_CAM_ENTRY 32 487#define HALF_CAM_ENTRY 16 488 489#define CAM_WRITE BIT(16) 490#define CAM_READ 0x00000000 491#define CAM_POLLINIG BIT(31) 492 493#define SCR_USEDK 0x01 494#define SCR_TXSEC_ENABLE 0x02 495#define SCR_RXSEC_ENABLE 0x04 496 497#define WOW_PMEN BIT(0) 498#define WOW_WOMEN BIT(1) 499#define WOW_MAGIC BIT(2) 500#define WOW_UWF BIT(3) 501 502#define IMR8190_DISABLED 0x0 503#define IMR_BCNDMAINT6 BIT(31) 504#define IMR_BCNDMAINT5 BIT(30) 505#define IMR_BCNDMAINT4 BIT(29) 506#define IMR_BCNDMAINT3 BIT(28) 507#define IMR_BCNDMAINT2 BIT(27) 508#define IMR_BCNDMAINT1 BIT(26) 509#define IMR_BCNDOK8 BIT(25) 510#define IMR_BCNDOK7 BIT(24) 511#define IMR_BCNDOK6 BIT(23) 512#define IMR_BCNDOK5 BIT(22) 513#define IMR_BCNDOK4 BIT(21) 514#define IMR_BCNDOK3 BIT(20) 515#define IMR_BCNDOK2 BIT(19) 516#define IMR_BCNDOK1 BIT(18) 517#define IMR_TIMEOUT2 BIT(17) 518#define IMR_TIMEOUT1 BIT(16) 519#define IMR_TXFOVW BIT(15) 520#define IMR_PSTIMEOUT BIT(14) 521#define IMR_BCNINT BIT(13) 522#define IMR_RXFOVW BIT(12) 523#define IMR_RDU BIT(11) 524#define IMR_ATIMEND BIT(10) 525#define IMR_BDOK BIT(9) 526#define IMR_HIGHDOK BIT(8) 527#define IMR_TBDOK BIT(7) 528#define IMR_MGNTDOK BIT(6) 529#define IMR_TBDER BIT(5) 530#define IMR_BKDOK BIT(4) 531#define IMR_BEDOK BIT(3) 532#define IMR_VIDOK BIT(2) 533#define IMR_VODOK BIT(1) 534#define IMR_ROK BIT(0) 535 536#define IMR_TXERR BIT(11) 537#define IMR_RXERR BIT(10) 538#define IMR_C2HCMD BIT(9) 539#define IMR_CPWM BIT(8) 540#define IMR_OCPINT BIT(1) 541#define IMR_WLANOFF BIT(0) 542 543#define EFUSE_REAL_CONTENT_LEN 512 544#define EFUSE_OOB_PROTECT_BYTES 15 545 546#define EEPROM_DEFAULT_TSSI 0x0 547#define EEPROM_DEFAULT_TXPOWERDIFF 0x0 548#define EEPROM_DEFAULT_CRYSTALCAP 0x5 549#define EEPROM_DEFAULT_BOARDTYPE 0x02 550#define EEPROM_DEFAULT_TXPOWER 0x1010 551#define EEPROM_DEFAULT_HT2T_TXPWR 0x10 552 553#define EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF 0x3 554#define EEPROM_DEFAULT_THERMALMETER 0x12 555#define EEPROM_DEFAULT_ANTTXPOWERDIFF 0x0 556#define EEPROM_DEFAULT_TXPWDIFF_CRYSTALCAP 0x5 557#define EEPROM_DEFAULT_TXPOWERLEVEL 0x22 558#define EEPROM_DEFAULT_HT40_2SDIFF 0x0 559#define EEPROM_DEFAULT_HT20_DIFF 2 560#define EEPROM_DEFAULT_HT40_PWRMAXOFFSET 0 561#define EEPROM_DEFAULT_HT20_PWRMAXOFFSET 0 562 563#define RF_OPTION1 0x79 564#define RF_OPTION2 0x7A 565#define RF_OPTION3 0x7B 566#define RF_OPTION4 0x7C 567 568#define EEPROM_DEFAULT_PID 0x1234 569#define EEPROM_DEFAULT_VID 0x5678 570#define EEPROM_DEFAULT_CUSTOMERID 0xAB 571#define EEPROM_DEFAULT_SUBCUSTOMERID 0xCD 572#define EEPROM_DEFAULT_VERSION 0 573 574#define EEPROM_CHANNEL_PLAN_FCC 0x0 575#define EEPROM_CHANNEL_PLAN_IC 0x1 576#define EEPROM_CHANNEL_PLAN_ETSI 0x2 577#define EEPROM_CHANNEL_PLAN_SPAIN 0x3 578#define EEPROM_CHANNEL_PLAN_FRANCE 0x4 579#define EEPROM_CHANNEL_PLAN_MKK 0x5 580#define EEPROM_CHANNEL_PLAN_MKK1 0x6 581#define EEPROM_CHANNEL_PLAN_ISRAEL 0x7 582#define EEPROM_CHANNEL_PLAN_TELEC 0x8 583#define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9 584#define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA 585#define EEPROM_CHANNEL_PLAN_NCC 0xB 586#define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80 587 588#define EEPROM_CID_DEFAULT 0x0 589#define EEPROM_CID_TOSHIBA 0x4 590#define EEPROM_CID_CCX 0x10 591#define EEPROM_CID_QMI 0x0D 592#define EEPROM_CID_WHQL 0xFE 593 594#define RTL8192_EEPROM_ID 0x8129 595 596#define RTL8190_EEPROM_ID 0x8129 597#define EEPROM_HPON 0x02 598#define EEPROM_CLK 0x06 599#define EEPROM_TESTR 0x08 600 601#define EEPROM_VID 0x0A 602#define EEPROM_DID 0x0C 603#define EEPROM_SVID 0x0E 604#define EEPROM_SMID 0x10 605 606#define EEPROM_MAC_ADDR 0x16 607 608#define EEPROM_CCK_TX_PWR_INX 0x5A 609#define EEPROM_HT40_1S_TX_PWR_INX 0x60 610#define EEPROM_HT40_2S_TX_PWR_INX_DIFF 0x66 611#define EEPROM_HT20_TX_PWR_INX_DIFF 0x69 612#define EEPROM_OFDM_TX_PWR_INX_DIFF 0x6C 613#define EEPROM_HT40_MAX_PWR_OFFSET 0x6F 614#define EEPROM_HT20_MAX_PWR_OFFSET 0x72 615 616#define EEPROM_TSSI_A 0x76 617#define EEPROM_TSSI_B 0x77 618#define EEPROM_THERMAL_METER 0x78 619#define EEPROM_XTAL_K 0x78 620#define EEPROM_RF_OPT1 0x79 621#define EEPROM_RF_OPT2 0x7A 622#define EEPROM_RF_OPT3 0x7B 623#define EEPROM_RF_OPT4 0x7C 624#define EEPROM_CHANNEL_PLAN 0x7D 625#define EEPROM_VERSION 0x7E 626#define EEPROM_CUSTOMER_ID 0x7F 627 628#define EEPROM_PWRDIFF 0x54 629 630#define EEPROM_TXPOWERCCK 0x5A 631#define EEPROM_TXPOWERHT40_1S 0x60 632#define EEPROM_TXPOWERHT40_2SDIFF 0x66 633#define EEPROM_TXPOWERHT20DIFF 0x69 634#define EEPROM_TXPOWER_OFDMDIFF 0x6C 635 636#define EEPROM_TXPWR_GROUP 0x6F 637 638#define EEPROM_CHANNELPLAN 0x75 639 640#define STOPBECON BIT(6) 641#define STOPHIGHT BIT(5) 642#define STOPMGT BIT(4) 643#define STOPVO BIT(3) 644#define STOPVI BIT(2) 645#define STOPBE BIT(1) 646#define STOPBK BIT(0) 647 648#define RCR_APPFCS BIT(31) 649#define RCR_APP_FCS BIT(31) 650#define RCR_APP_MIC BIT(30) 651#define RCR_APP_ICV BIT(29) 652#define RCR_APP_PHYSTS BIT(28) 653#define RCR_APP_PHYST_RXFF BIT(28) 654#define RCR_APP_BA_SSN BIT(27) 655#define RCR_ENMBID BIT(24) 656#define RCR_LSIGEN BIT(23) 657#define RCR_MFBEN BIT(22) 658#define RCR_HTC_LOC_CTRL BIT(14) 659#define RCR_AMF BIT(13) 660#define RCR_ACF BIT(12) 661#define RCR_ADF BIT(11) 662#define RCR_AICV BIT(9) 663#define RCR_ACRC32 BIT(8) 664#define RCR_CBSSID_BCN BIT(7) 665#define RCR_CBSSID_DATA BIT(6) 666#define RCR_CBSSID RCR_CBSSID_DATA 667#define RCR_APWRMGT BIT(5) 668#define RCR_ADD3 BIT(4) 669#define RCR_AB BIT(3) 670#define RCR_AM BIT(2) 671#define RCR_APM BIT(1) 672#define RCR_AAP BIT(0) 673#define RCR_MXDMA_OFFSET 8 674#define RCR_FIFO_OFFSET 13 675 676#define RSV_CTRL 0x001C 677#define RD_CTRL 0x0524 678 679#define REG_USB_VID 0xFE60 680#define REG_USB_PID 0xFE62 681#define REG_USB_OPTIONAL 0xFE64 682#define REG_USB_CHIRP_K 0xFE65 683#define REG_USB_PHY 0xFE66 684#define REG_USB_MAC_ADDR 0xFE70 685#define REG_USB_HRPWM 0xFE58 686#define REG_USB_HCPWM 0xFE57 687 688#define SW18_FPWM BIT(3) 689 690#define ISO_MD2PP BIT(0) 691#define ISO_UA2USB BIT(1) 692#define ISO_UD2CORE BIT(2) 693#define ISO_PA2PCIE BIT(3) 694#define ISO_PD2CORE BIT(4) 695#define ISO_IP2MAC BIT(5) 696#define ISO_DIOP BIT(6) 697#define ISO_DIOE BIT(7) 698#define ISO_EB2CORE BIT(8) 699#define ISO_DIOR BIT(9) 700 701#define PWC_EV25V BIT(14) 702#define PWC_EV12V BIT(15) 703 704#define FEN_BBRSTB BIT(0) 705#define FEN_BB_GLB_RSTn BIT(1) 706#define FEN_USBA BIT(2) 707#define FEN_UPLL BIT(3) 708#define FEN_USBD BIT(4) 709#define FEN_DIO_PCIE BIT(5) 710#define FEN_PCIEA BIT(6) 711#define FEN_PPLL BIT(7) 712#define FEN_PCIED BIT(8) 713#define FEN_DIOE BIT(9) 714#define FEN_CPUEN BIT(10) 715#define FEN_DCORE BIT(11) 716#define FEN_ELDR BIT(12) 717#define FEN_DIO_RF BIT(13) 718#define FEN_HWPDN BIT(14) 719#define FEN_MREGEN BIT(15) 720 721#define PFM_LDALL BIT(0) 722#define PFM_ALDN BIT(1) 723#define PFM_LDKP BIT(2) 724#define PFM_WOWL BIT(3) 725#define EnPDN BIT(4) 726#define PDN_PL BIT(5) 727#define APFM_ONMAC BIT(8) 728#define APFM_OFF BIT(9) 729#define APFM_RSM BIT(10) 730#define AFSM_HSUS BIT(11) 731#define AFSM_PCIE BIT(12) 732#define APDM_MAC BIT(13) 733#define APDM_HOST BIT(14) 734#define APDM_HPDN BIT(15) 735#define RDY_MACON BIT(16) 736#define SUS_HOST BIT(17) 737#define ROP_ALD BIT(20) 738#define ROP_PWR BIT(21) 739#define ROP_SPS BIT(22) 740#define SOP_MRST BIT(25) 741#define SOP_FUSE BIT(26) 742#define SOP_ABG BIT(27) 743#define SOP_AMB BIT(28) 744#define SOP_RCK BIT(29) 745#define SOP_A8M BIT(30) 746#define XOP_BTCK BIT(31) 747 748#define ANAD16V_EN BIT(0) 749#define ANA8M BIT(1) 750#define MACSLP BIT(4) 751#define LOADER_CLK_EN BIT(5) 752#define _80M_SSC_DIS BIT(7) 753#define _80M_SSC_EN_HO BIT(8) 754#define PHY_SSC_RSTB BIT(9) 755#define SEC_CLK_EN BIT(10) 756#define MAC_CLK_EN BIT(11) 757#define SYS_CLK_EN BIT(12) 758#define RING_CLK_EN BIT(13) 759 760#define BOOT_FROM_EEPROM BIT(4) 761#define EEPROM_EN BIT(5) 762 763#define AFE_BGEN BIT(0) 764#define AFE_MBEN BIT(1) 765#define MAC_ID_EN BIT(7) 766 767#define WLOCK_ALL BIT(0) 768#define WLOCK_00 BIT(1) 769#define WLOCK_04 BIT(2) 770#define WLOCK_08 BIT(3) 771#define WLOCK_40 BIT(4) 772#define R_DIS_PRST_0 BIT(5) 773#define R_DIS_PRST_1 BIT(6) 774#define LOCK_ALL_EN BIT(7) 775 776#define RF_EN BIT(0) 777#define RF_RSTB BIT(1) 778#define RF_SDMRSTB BIT(2) 779 780#define LDA15_EN BIT(0) 781#define LDA15_STBY BIT(1) 782#define LDA15_OBUF BIT(2) 783#define LDA15_REG_VOS BIT(3) 784#define _LDA15_VOADJ(x) (((x) & 0x7) << 4) 785 786#define LDV12_EN BIT(0) 787#define LDV12_SDBY BIT(1) 788#define LPLDO_HSM BIT(2) 789#define LPLDO_LSM_DIS BIT(3) 790#define _LDV12_VADJ(x) (((x) & 0xF) << 4) 791 792#define XTAL_EN BIT(0) 793#define XTAL_BSEL BIT(1) 794#define _XTAL_BOSC(x) (((x) & 0x3) << 2) 795#define _XTAL_CADJ(x) (((x) & 0xF) << 4) 796#define XTAL_GATE_USB BIT(8) 797#define _XTAL_USB_DRV(x) (((x) & 0x3) << 9) 798#define XTAL_GATE_AFE BIT(11) 799#define _XTAL_AFE_DRV(x) (((x) & 0x3) << 12) 800#define XTAL_RF_GATE BIT(14) 801#define _XTAL_RF_DRV(x) (((x) & 0x3) << 15) 802#define XTAL_GATE_DIG BIT(17) 803#define _XTAL_DIG_DRV(x) (((x) & 0x3) << 18) 804#define XTAL_BT_GATE BIT(20) 805#define _XTAL_BT_DRV(x) (((x) & 0x3) << 21) 806#define _XTAL_GPIO(x) (((x) & 0x7) << 23) 807 808#define CKDLY_AFE BIT(26) 809#define CKDLY_USB BIT(27) 810#define CKDLY_DIG BIT(28) 811#define CKDLY_BT BIT(29) 812 813#define APLL_EN BIT(0) 814#define APLL_320_EN BIT(1) 815#define APLL_FREF_SEL BIT(2) 816#define APLL_EDGE_SEL BIT(3) 817#define APLL_WDOGB BIT(4) 818#define APLL_LPFEN BIT(5) 819 820#define APLL_REF_CLK_13MHZ 0x1 821#define APLL_REF_CLK_19_2MHZ 0x2 822#define APLL_REF_CLK_20MHZ 0x3 823#define APLL_REF_CLK_25MHZ 0x4 824#define APLL_REF_CLK_26MHZ 0x5 825#define APLL_REF_CLK_38_4MHZ 0x6 826#define APLL_REF_CLK_40MHZ 0x7 827 828#define APLL_320EN BIT(14) 829#define APLL_80EN BIT(15) 830#define APLL_1MEN BIT(24) 831 832#define ALD_EN BIT(18) 833#define EF_PD BIT(19) 834#define EF_FLAG BIT(31) 835 836#define EF_TRPT BIT(7) 837#define LDOE25_EN BIT(31) 838 839#define RSM_EN BIT(0) 840#define Timer_EN BIT(4) 841 842#define TRSW0EN BIT(2) 843#define TRSW1EN BIT(3) 844#define EROM_EN BIT(4) 845#define EnBT BIT(5) 846#define EnUart BIT(8) 847#define Uart_910 BIT(9) 848#define EnPMAC BIT(10) 849#define SIC_SWRST BIT(11) 850#define EnSIC BIT(12) 851#define SIC_23 BIT(13) 852#define EnHDP BIT(14) 853#define SIC_LBK BIT(15) 854 855#define LED0PL BIT(4) 856#define LED1PL BIT(12) 857#define LED0DIS BIT(7) 858 859#define MCUFWDL_EN BIT(0) 860#define MCUFWDL_RDY BIT(1) 861#define FWDL_ChkSum_rpt BIT(2) 862#define MACINI_RDY BIT(3) 863#define BBINI_RDY BIT(4) 864#define RFINI_RDY BIT(5) 865#define WINTINI_RDY BIT(6) 866#define CPRST BIT(23) 867 868#define XCLK_VLD BIT(0) 869#define ACLK_VLD BIT(1) 870#define UCLK_VLD BIT(2) 871#define PCLK_VLD BIT(3) 872#define PCIRSTB BIT(4) 873#define V15_VLD BIT(5) 874#define TRP_B15V_EN BIT(7) 875#define SIC_IDLE BIT(8) 876#define BD_MAC2 BIT(9) 877#define BD_MAC1 BIT(10) 878#define IC_MACPHY_MODE BIT(11) 879#define BT_FUNC BIT(16) 880#define VENDOR_ID BIT(19) 881#define PAD_HWPD_IDN BIT(22) 882#define TRP_VAUX_EN BIT(23) 883#define TRP_BT_EN BIT(24) 884#define BD_PKG_SEL BIT(25) 885#define BD_HCI_SEL BIT(26) 886#define TYPE_ID BIT(27) 887#define RF_RL_ID (BIT(31) | BIT(30) | BIT(29) | BIT(28)) 888 889#define CHIP_VER_RTL_MASK 0xF000 890#define CHIP_VER_RTL_SHIFT 12 891 892#define REG_LBMODE (REG_CR + 3) 893 894#define HCI_TXDMA_EN BIT(0) 895#define HCI_RXDMA_EN BIT(1) 896#define TXDMA_EN BIT(2) 897#define RXDMA_EN BIT(3) 898#define PROTOCOL_EN BIT(4) 899#define SCHEDULE_EN BIT(5) 900#define MACTXEN BIT(6) 901#define MACRXEN BIT(7) 902#define ENSWBCN BIT(8) 903#define ENSEC BIT(9) 904 905#define _NETTYPE(x) (((x) & 0x3) << 16) 906#define MASK_NETTYPE 0x30000 907#define NT_NO_LINK 0x0 908#define NT_LINK_AD_HOC 0x1 909#define NT_LINK_AP 0x2 910#define NT_AS_AP 0x3 911 912#define _LBMODE(x) (((x) & 0xF) << 24) 913#define MASK_LBMODE 0xF000000 914#define LOOPBACK_NORMAL 0x0 915#define LOOPBACK_IMMEDIATELY 0xB 916#define LOOPBACK_MAC_DELAY 0x3 917#define LOOPBACK_PHY 0x1 918#define LOOPBACK_DMA 0x7 919 920#define GET_RX_PAGE_SIZE(value) ((value) & 0xF) 921#define GET_TX_PAGE_SIZE(value) (((value) & 0xF0) >> 4) 922#define _PSRX_MASK 0xF 923#define _PSTX_MASK 0xF0 924#define _PSRX(x) (x) 925#define _PSTX(x) ((x) << 4) 926 927#define PBP_64 0x0 928#define PBP_128 0x1 929#define PBP_256 0x2 930#define PBP_512 0x3 931#define PBP_1024 0x4 932 933#define RXDMA_ARBBW_EN BIT(0) 934#define RXSHFT_EN BIT(1) 935#define RXDMA_AGG_EN BIT(2) 936#define QS_VO_QUEUE BIT(8) 937#define QS_VI_QUEUE BIT(9) 938#define QS_BE_QUEUE BIT(10) 939#define QS_BK_QUEUE BIT(11) 940#define QS_MANAGER_QUEUE BIT(12) 941#define QS_HIGH_QUEUE BIT(13) 942 943#define HQSEL_VOQ BIT(0) 944#define HQSEL_VIQ BIT(1) 945#define HQSEL_BEQ BIT(2) 946#define HQSEL_BKQ BIT(3) 947#define HQSEL_MGTQ BIT(4) 948#define HQSEL_HIQ BIT(5) 949 950#define _TXDMA_HIQ_MAP(x) (((x)&0x3) << 14) 951#define _TXDMA_MGQ_MAP(x) (((x)&0x3) << 12) 952#define _TXDMA_BKQ_MAP(x) (((x)&0x3) << 10) 953#define _TXDMA_BEQ_MAP(x) (((x)&0x3) << 8) 954#define _TXDMA_VIQ_MAP(x) (((x)&0x3) << 6) 955#define _TXDMA_VOQ_MAP(x) (((x)&0x3) << 4) 956 957#define QUEUE_LOW 1 958#define QUEUE_NORMAL 2 959#define QUEUE_HIGH 3 960 961#define _LLT_NO_ACTIVE 0x0 962#define _LLT_WRITE_ACCESS 0x1 963#define _LLT_READ_ACCESS 0x2 964 965#define _LLT_INIT_DATA(x) ((x) & 0xFF) 966#define _LLT_INIT_ADDR(x) (((x) & 0xFF) << 8) 967#define _LLT_OP(x) (((x) & 0x3) << 30) 968#define _LLT_OP_VALUE(x) (((x) >> 30) & 0x3) 969 970#define BB_WRITE_READ_MASK (BIT(31) | BIT(30)) 971#define BB_WRITE_EN BIT(30) 972#define BB_READ_EN BIT(31) 973 974#define _HPQ(x) ((x) & 0xFF) 975#define _LPQ(x) (((x) & 0xFF) << 8) 976#define _PUBQ(x) (((x) & 0xFF) << 16) 977#define _NPQ(x) ((x) & 0xFF) 978 979#define HPQ_PUBLIC_DIS BIT(24) 980#define LPQ_PUBLIC_DIS BIT(25) 981#define LD_RQPN BIT(31) 982 983#define BCN_VALID BIT(16) 984#define BCN_HEAD(x) (((x) & 0xFF) << 8) 985#define BCN_HEAD_MASK 0xFF00 986 987#define BLK_DESC_NUM_SHIFT 4 988#define BLK_DESC_NUM_MASK 0xF 989 990#define DROP_DATA_EN BIT(9) 991 992#define EN_AMPDU_RTY_NEW BIT(7) 993 994#define _INIRTSMCS_SEL(x) ((x) & 0x3F) 995 996#define _SPEC_SIFS_CCK(x) ((x) & 0xFF) 997#define _SPEC_SIFS_OFDM(x) (((x) & 0xFF) << 8) 998 999#define RATE_REG_BITMAP_ALL 0xFFFFF 1000
1001#define _RRSC_BITMAP(x) ((x) & 0xFFFFF) 1002 1003#define _RRSR_RSC(x) (((x) & 0x3) << 21) 1004#define RRSR_RSC_RESERVED 0x0 1005#define RRSR_RSC_UPPER_SUBCHANNEL 0x1 1006#define RRSR_RSC_LOWER_SUBCHANNEL 0x2 1007#define RRSR_RSC_DUPLICATE_MODE 0x3 1008 1009#define USE_SHORT_G1 BIT(20) 1010 1011#define _AGGLMT_MCS0(x) ((x) & 0xF) 1012#define _AGGLMT_MCS1(x) (((x) & 0xF) << 4) 1013#define _AGGLMT_MCS2(x) (((x) & 0xF) << 8) 1014#define _AGGLMT_MCS3(x) (((x) & 0xF) << 12) 1015#define _AGGLMT_MCS4(x) (((x) & 0xF) << 16) 1016#define _AGGLMT_MCS5(x) (((x) & 0xF) << 20) 1017#define _AGGLMT_MCS6(x) (((x) & 0xF) << 24) 1018#define _AGGLMT_MCS7(x) (((x) & 0xF) << 28) 1019 1020#define RETRY_LIMIT_SHORT_SHIFT 8 1021#define RETRY_LIMIT_LONG_SHIFT 0 1022 1023#define _DARF_RC1(x) ((x) & 0x1F) 1024#define _DARF_RC2(x) (((x) & 0x1F) << 8) 1025#define _DARF_RC3(x) (((x) & 0x1F) << 16) 1026#define _DARF_RC4(x) (((x) & 0x1F) << 24) 1027#define _DARF_RC5(x) ((x) & 0x1F) 1028#define _DARF_RC6(x) (((x) & 0x1F) << 8) 1029#define _DARF_RC7(x) (((x) & 0x1F) << 16) 1030#define _DARF_RC8(x) (((x) & 0x1F) << 24) 1031 1032#define _RARF_RC1(x) ((x) & 0x1F) 1033#define _RARF_RC2(x) (((x) & 0x1F) << 8) 1034#define _RARF_RC3(x) (((x) & 0x1F) << 16) 1035#define _RARF_RC4(x) (((x) & 0x1F) << 24) 1036#define _RARF_RC5(x) ((x) & 0x1F) 1037#define _RARF_RC6(x) (((x) & 0x1F) << 8) 1038#define _RARF_RC7(x) (((x) & 0x1F) << 16) 1039#define _RARF_RC8(x) (((x) & 0x1F) << 24) 1040 1041#define AC_PARAM_TXOP_OFFSET 16 1042#define AC_PARAM_TXOP_LIMIT_OFFSET 16 1043#define AC_PARAM_ECW_MAX_OFFSET 12 1044#define AC_PARAM_ECW_MIN_OFFSET 8 1045#define AC_PARAM_AIFS_OFFSET 0 1046 1047#define _AIFS(x) (x) 1048#define _ECW_MAX_MIN(x) ((x) << 8) 1049#define _TXOP_LIMIT(x) ((x) << 16) 1050 1051#define _BCNIFS(x) ((x) & 0xFF) 1052#define _BCNECW(x) ((((x) & 0xF)) << 8) 1053 1054#define _LRL(x) ((x) & 0x3F) 1055#define _SRL(x) (((x) & 0x3F) << 8) 1056 1057#define _SIFS_CCK_CTX(x) ((x) & 0xFF) 1058#define _SIFS_CCK_TRX(x) (((x) & 0xFF) << 8) 1059 1060#define _SIFS_OFDM_CTX(x) ((x) & 0xFF) 1061#define _SIFS_OFDM_TRX(x) (((x) & 0xFF) << 8) 1062 1063#define _TBTT_PROHIBIT_HOLD(x) (((x) & 0xFF) << 8) 1064 1065#define DIS_EDCA_CNT_DWN BIT(11) 1066 1067#define EN_MBSSID BIT(1) 1068#define EN_TXBCN_RPT BIT(2) 1069#define EN_BCN_FUNCTION BIT(3) 1070 1071#define TSFTR_RST BIT(0) 1072#define TSFTR1_RST BIT(1) 1073 1074#define STOP_BCNQ BIT(6) 1075 1076#define DIS_TSF_UDT0_NORMAL_CHIP BIT(4) 1077#define DIS_TSF_UDT0_TEST_CHIP BIT(5) 1078 1079#define AcmHw_HwEn BIT(0) 1080#define AcmHw_BeqEn BIT(1) 1081#define AcmHw_ViqEn BIT(2) 1082#define AcmHw_VoqEn BIT(3) 1083#define AcmHw_BeqStatus BIT(4) 1084#define AcmHw_ViqStatus BIT(5) 1085#define AcmHw_VoqStatus BIT(6) 1086 1087#define APSDOFF BIT(6) 1088#define APSDOFF_STATUS BIT(7) 1089 1090#define BW_20MHZ BIT(2) 1091 1092#define RATE_BITMAP_ALL 0xFFFFF 1093 1094#define RATE_RRSR_CCK_ONLY_1M 0xFFFF1 1095 1096#define TSFRST BIT(0) 1097#define DIS_GCLK BIT(1) 1098#define PAD_SEL BIT(2) 1099#define PWR_ST BIT(6) 1100#define PWRBIT_OW_EN BIT(7) 1101#define ACRC BIT(8) 1102#define CFENDFORM BIT(9) 1103#define ICV BIT(10) 1104 1105#define AAP BIT(0) 1106#define APM BIT(1) 1107#define AM BIT(2) 1108#define AB BIT(3) 1109#define ADD3 BIT(4) 1110#define APWRMGT BIT(5) 1111#define CBSSID BIT(6) 1112#define CBSSID_DATA BIT(6) 1113#define CBSSID_BCN BIT(7) 1114#define ACRC32 BIT(8) 1115#define AICV BIT(9) 1116#define ADF BIT(11) 1117#define ACF BIT(12) 1118#define AMF BIT(13) 1119#define HTC_LOC_CTRL BIT(14) 1120#define UC_DATA_EN BIT(16) 1121#define BM_DATA_EN BIT(17) 1122#define MFBEN BIT(22) 1123#define LSIGEN BIT(23) 1124#define EnMBID BIT(24) 1125#define APP_BASSN BIT(27) 1126#define APP_PHYSTS BIT(28) 1127#define APP_ICV BIT(29) 1128#define APP_MIC BIT(30) 1129#define APP_FCS BIT(31) 1130 1131#define _MIN_SPACE(x) ((x) & 0x7) 1132#define _SHORT_GI_PADDING(x) (((x) & 0x1F) << 3) 1133 1134#define RXERR_TYPE_OFDM_PPDU 0 1135#define RXERR_TYPE_OFDM_FALSE_ALARM 1 1136#define RXERR_TYPE_OFDM_MPDU_OK 2 1137#define RXERR_TYPE_OFDM_MPDU_FAIL 3 1138#define RXERR_TYPE_CCK_PPDU 4 1139#define RXERR_TYPE_CCK_FALSE_ALARM 5 1140#define RXERR_TYPE_CCK_MPDU_OK 6 1141#define RXERR_TYPE_CCK_MPDU_FAIL 7 1142#define RXERR_TYPE_HT_PPDU 8 1143#define RXERR_TYPE_HT_FALSE_ALARM 9 1144#define RXERR_TYPE_HT_MPDU_TOTAL 10 1145#define RXERR_TYPE_HT_MPDU_OK 11 1146#define RXERR_TYPE_HT_MPDU_FAIL 12 1147#define RXERR_TYPE_RX_FULL_DROP 15 1148 1149#define RXERR_COUNTER_MASK 0xFFFFF 1150#define RXERR_RPT_RST BIT(27) 1151#define _RXERR_RPT_SEL(type) ((type) << 28) 1152 1153#define SCR_TxUseDK BIT(0) 1154#define SCR_RxUseDK BIT(1) 1155#define SCR_TxEncEnable BIT(2) 1156#define SCR_RxDecEnable BIT(3) 1157#define SCR_SKByA2 BIT(4) 1158#define SCR_NoSKMC BIT(5) 1159#define SCR_TXBCUSEDK BIT(6) 1160#define SCR_RXBCUSEDK BIT(7) 1161 1162#define USB_IS_HIGH_SPEED 0 1163#define USB_IS_FULL_SPEED 1 1164#define USB_SPEED_MASK BIT(5) 1165 1166#define USB_NORMAL_SIE_EP_MASK 0xF 1167#define USB_NORMAL_SIE_EP_SHIFT 4 1168 1169#define USB_TEST_EP_MASK 0x30 1170#define USB_TEST_EP_SHIFT 4 1171 1172#define USB_AGG_EN BIT(3) 1173 1174#define LAST_ENTRY_OF_TX_PKT_BUFFER 255 1175 1176#define POLLING_LLT_THRESHOLD 20 1177#define POLLING_READY_TIMEOUT_COUNT 1000 1178 1179#define EPROM_CMD_OPERATING_MODE_MASK ((1<<7)|(1<<6)) 1180#define EPROM_CMD_CONFIG 0x3 1181#define EPROM_CMD_LOAD 1 1182 1183#define HWSET_MAX_SIZE 128 1184#define HWSET_MAX_SIZE_92S HWSET_MAX_SIZE 1185#define EFUSE_MAX_SECTION 16 1186 1187#define WL_HWPDN_EN BIT(0) 1188 1189#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2) 1190 1191#define RPMAC_RESET 0x100 1192#define RPMAC_TXSTART 0x104 1193#define RPMAC_TXLEGACYSIG 0x108 1194#define RPMAC_TXHTSIG1 0x10c 1195#define RPMAC_TXHTSIG2 0x110 1196#define RPMAC_PHYDEBUG 0x114 1197#define RPMAC_TXPACKETNUM 0x118 1198#define RPMAC_TXIDLE 0x11c 1199#define RPMAC_TXMACHEADER0 0x120 1200#define RPMAC_TXMACHEADER1 0x124 1201#define RPMAC_TXMACHEADER2 0x128 1202#define RPMAC_TXMACHEADER3 0x12c 1203#define RPMAC_TXMACHEADER4 0x130 1204#define RPMAC_TXMACHEADER5 0x134 1205#define RPMAC_TXDADATYPE 0x138 1206#define RPMAC_TXRANDOMSEED 0x13c 1207#define RPMAC_CCKPLCPPREAMBLE 0x140 1208#define RPMAC_CCKPLCPHEADER 0x144 1209#define RPMAC_CCKCRC16 0x148 1210#define RPMAC_OFDMRXCRC32OK 0x170 1211#define RPMAC_OFDMRXCRC32Er 0x174 1212#define RPMAC_OFDMRXPARITYER 0x178 1213#define RPMAC_OFDMRXCRC8ER 0x17c 1214#define RPMAC_CCKCRXRC16ER 0x180 1215#define RPMAC_CCKCRXRC32ER 0x184 1216#define RPMAC_CCKCRXRC32OK 0x188 1217#define RPMAC_TXSTATUS 0x18c 1218 1219#define RFPGA0_RFMOD 0x800 1220 1221#define RFPGA0_TXINFO 0x804 1222#define RFPGA0_PSDFUNCTION 0x808 1223 1224#define RFPGA0_TXGAINSTAGE 0x80c 1225 1226#define RFPGA0_RFTIMING1 0x810 1227#define RFPGA0_RFTIMING2 0x814 1228 1229#define RFPGA0_XA_HSSIPARAMETER1 0x820 1230#define RFPGA0_XA_HSSIPARAMETER2 0x824 1231#define RFPGA0_XB_HSSIPARAMETER1 0x828 1232#define RFPGA0_XB_HSSIPARAMETER2 0x82c 1233 1234#define RFPGA0_XA_LSSIPARAMETER 0x840 1235#define RFPGA0_XB_LSSIPARAMETER 0x844 1236 1237#define RFPGA0_RFWAKEUPPARAMETER 0x850 1238#define RFPGA0_RFSLEEPUPPARAMETER 0x854 1239 1240#define RFPGA0_XAB_SWITCHCONTROL 0x858 1241#define RFPGA0_XCD_SWITCHCONTROL 0x85c 1242 1243#define RFPGA0_XA_RFINTERFACEOE 0x860 1244#define RFPGA0_XB_RFINTERFACEOE 0x864 1245 1246#define RFPGA0_XAB_RFINTERFACESW 0x870 1247#define RFPGA0_XCD_RFINTERFACESW 0x874 1248 1249#define rFPGA0_XAB_RFPARAMETER 0x878 1250#define rFPGA0_XCD_RFPARAMETER 0x87c 1251 1252#define RFPGA0_ANALOGPARAMETER1 0x880 1253#define RFPGA0_ANALOGPARAMETER2 0x884 1254#define RFPGA0_ANALOGPARAMETER3 0x888 1255#define RFPGA0_ANALOGPARAMETER4 0x88c 1256 1257#define RFPGA0_XA_LSSIREADBACK 0x8a0 1258#define RFPGA0_XB_LSSIREADBACK 0x8a4 1259#define RFPGA0_XC_LSSIREADBACK 0x8a8 1260#define RFPGA0_XD_LSSIREADBACK 0x8ac 1261 1262#define RFPGA0_PSDREPORT 0x8b4 1263#define TRANSCEIVEA_HSPI_READBACK 0x8b8 1264#define TRANSCEIVEB_HSPI_READBACK 0x8bc 1265#define RFPGA0_XAB_RFINTERFACERB 0x8e0 1266#define RFPGA0_XCD_RFINTERFACERB 0x8e4 1267 1268#define RFPGA1_RFMOD 0x900 1269 1270#define RFPGA1_TXBLOCK 0x904 1271#define RFPGA1_DEBUGSELECT 0x908 1272#define RFPGA1_TXINFO 0x90c 1273 1274#define RCCK0_SYSTEM 0xa00 1275 1276#define RCCK0_AFESETTING 0xa04 1277#define RCCK0_CCA 0xa08 1278 1279#define RCCK0_RXAGC1 0xa0c 1280#define RCCK0_RXAGC2 0xa10 1281 1282#define RCCK0_RXHP 0xa14 1283 1284#define RCCK0_DSPPARAMETER1 0xa18 1285#define RCCK0_DSPPARAMETER2 0xa1c 1286 1287#define RCCK0_TXFILTER1 0xa20 1288#define RCCK0_TXFILTER2 0xa24 1289#define RCCK0_DEBUGPORT 0xa28 1290#define RCCK0_FALSEALARMREPORT 0xa2c 1291#define RCCK0_TRSSIREPORT 0xa50 1292#define RCCK0_RXREPORT 0xa54 1293#define RCCK0_FACOUNTERLOWER 0xa5c 1294#define RCCK0_FACOUNTERUPPER 0xa58 1295 1296#define ROFDM0_LSTF 0xc00 1297 1298#define ROFDM0_TRXPATHENABLE 0xc04 1299#define ROFDM0_TRMUXPAR 0xc08 1300#define ROFDM0_TRSWISOLATION 0xc0c 1301 1302#define ROFDM0_XARXAFE 0xc10 1303#define ROFDM0_XARXIQIMBALANCE 0xc14 1304#define ROFDM0_XBRXAFE 0xc18 1305#define ROFDM0_XBRXIQIMBALANCE 0xc1c 1306#define ROFDM0_XCRXAFE 0xc20 1307#define ROFDM0_XCRXIQIMBANLANCE 0xc24 1308#define ROFDM0_XDRXAFE 0xc28 1309#define ROFDM0_XDRXIQIMBALANCE 0xc2c 1310 1311#define ROFDM0_RXDETECTOR1 0xc30 1312#define ROFDM0_RXDETECTOR2 0xc34 1313#define ROFDM0_RXDETECTOR3 0xc38 1314#define ROFDM0_RXDETECTOR4 0xc3c 1315 1316#define ROFDM0_RXDSP 0xc40 1317#define ROFDM0_CFOANDDAGC 0xc44 1318#define ROFDM0_CCADROPTHRESHOLD 0xc48 1319#define ROFDM0_ECCATHRESHOLD 0xc4c 1320 1321#define ROFDM0_XAAGCCORE1 0xc50 1322#define ROFDM0_XAAGCCORE2 0xc54 1323#define ROFDM0_XBAGCCORE1 0xc58 1324#define ROFDM0_XBAGCCORE2 0xc5c 1325#define ROFDM0_XCAGCCORE1 0xc60 1326#define ROFDM0_XCAGCCORE2 0xc64 1327#define ROFDM0_XDAGCCORE1 0xc68 1328#define ROFDM0_XDAGCCORE2 0xc6c 1329 1330#define ROFDM0_AGCPARAMETER1 0xc70 1331#define ROFDM0_AGCPARAMETER2 0xc74 1332#define ROFDM0_AGCRSSITABLE 0xc78 1333#define ROFDM0_HTSTFAGC 0xc7c 1334 1335#define ROFDM0_XATXIQIMBALANCE 0xc80 1336#define ROFDM0_XATXAFE 0xc84 1337#define ROFDM0_XBTXIQIMBALANCE 0xc88 1338#define ROFDM0_XBTXAFE 0xc8c 1339#define ROFDM0_XCTXIQIMBALANCE 0xc90 1340#define ROFDM0_XCTXAFE 0xc94 1341#define ROFDM0_XDTXIQIMBALANCE 0xc98 1342#define ROFDM0_XDTXAFE 0xc9c 1343 1344#define ROFDM0_RXIQEXTANTA 0xca0 1345 1346#define ROFDM0_RXHPPARAMETER 0xce0 1347#define ROFDM0_TXPSEUDONOISEWGT 0xce4 1348#define ROFDM0_FRAMESYNC 0xcf0 1349#define ROFDM0_DFSREPORT 0xcf4 1350#define ROFDM0_TXCOEFF1 0xca4 1351#define ROFDM0_TXCOEFF2 0xca8 1352#define ROFDM0_TXCOEFF3 0xcac 1353#define ROFDM0_TXCOEFF4 0xcb0 1354#define ROFDM0_TXCOEFF5 0xcb4 1355#define ROFDM0_TXCOEFF6 0xcb8 1356 1357#define ROFDM1_LSTF 0xd00 1358#define ROFDM1_TRXPATHENABLE 0xd04 1359 1360#define ROFDM1_CF0 0xd08 1361#define ROFDM1_CSI1 0xd10 1362#define ROFDM1_SBD 0xd14 1363#define ROFDM1_CSI2 0xd18 1364#define ROFDM1_CFOTRACKING 0xd2c 1365#define ROFDM1_TRXMESAURE1 0xd34 1366#define ROFDM1_INTFDET 0xd3c 1367#define ROFDM1_PSEUDONOISESTATEAB 0xd50 1368#define ROFDM1_PSEUDONOISESTATECD 0xd54 1369#define ROFDM1_RXPSEUDONOISEWGT 0xd58 1370 1371#define ROFDM_PHYCOUNTER1 0xda0 1372#define ROFDM_PHYCOUNTER2 0xda4 1373#define ROFDM_PHYCOUNTER3 0xda8 1374 1375#define ROFDM_SHORTCFOAB 0xdac 1376#define ROFDM_SHORTCFOCD 0xdb0 1377#define ROFDM_LONGCFOAB 0xdb4 1378#define ROFDM_LONGCFOCD 0xdb8 1379#define ROFDM_TAILCF0AB 0xdbc 1380#define ROFDM_TAILCF0CD 0xdc0 1381#define ROFDM_PWMEASURE1 0xdc4 1382#define ROFDM_PWMEASURE2 0xdc8 1383#define ROFDM_BWREPORT 0xdcc 1384#define ROFDM_AGCREPORT 0xdd0 1385#define ROFDM_RXSNR 0xdd4 1386#define ROFDM_RXEVMCSI 0xdd8 1387#define ROFDM_SIGREPORT 0xddc 1388 1389#define RTXAGC_A_RATE18_06 0xe00 1390#define RTXAGC_A_RATE54_24 0xe04 1391#define RTXAGC_A_CCK1_MCS32 0xe08 1392#define RTXAGC_A_MCS03_MCS00 0xe10 1393#define RTXAGC_A_MCS07_MCS04 0xe14 1394#define RTXAGC_A_MCS11_MCS08 0xe18 1395#define RTXAGC_A_MCS15_MCS12 0xe1c 1396 1397#define RTXAGC_B_RATE18_06 0x830 1398#define RTXAGC_B_RATE54_24 0x834 1399#define RTXAGC_B_CCK1_55_MCS32 0x838 1400#define RTXAGC_B_MCS03_MCS00 0x83c 1401#define RTXAGC_B_MCS07_MCS04 0x848 1402#define RTXAGC_B_MCS11_MCS08 0x84c 1403#define RTXAGC_B_MCS15_MCS12 0x868 1404#define RTXAGC_B_CCK11_A_CCK2_11 0x86c 1405 1406#define RZEBRA1_HSSIENABLE 0x0 1407#define RZEBRA1_TRXENABLE1 0x1 1408#define RZEBRA1_TRXENABLE2 0x2 1409#define RZEBRA1_AGC 0x4 1410#define RZEBRA1_CHARGEPUMP 0x5 1411#define RZEBRA1_CHANNEL 0x7 1412 1413#define RZEBRA1_TXGAIN 0x8 1414#define RZEBRA1_TXLPF 0x9 1415#define RZEBRA1_RXLPF 0xb 1416#define RZEBRA1_RXHPFCORNER 0xc 1417 1418#define RGLOBALCTRL 0 1419#define RRTL8256_TXLPF 19 1420#define RRTL8256_RXLPF 11 1421#define RRTL8258_TXLPF 0x11 1422#define RRTL8258_RXLPF 0x13 1423#define RRTL8258_RSSILPF 0xa 1424 1425#define RF_AC 0x00 1426 1427#define RF_IQADJ_G1 0x01 1428#define RF_IQADJ_G2 0x02 1429#define RF_POW_TRSW 0x05 1430 1431#define RF_GAIN_RX 0x06 1432#define RF_GAIN_TX 0x07 1433 1434#define RF_TXM_IDAC 0x08 1435#define RF_BS_IQGEN 0x0F 1436 1437#define RF_MODE1 0x10 1438#define RF_MODE2 0x11 1439 1440#define RF_RX_AGC_HP 0x12 1441#define RF_TX_AGC 0x13 1442#define RF_BIAS 0x14 1443#define RF_IPA 0x15 1444#define RF_POW_ABILITY 0x17 1445#define RF_MODE_AG 0x18 1446#define RRFCHANNEL 0x18 1447#define RF_CHNLBW 0x18 1448#define RF_TOP 0x19 1449 1450#define RF_RX_G1 0x1A 1451#define RF_RX_G2 0x1B 1452 1453#define RF_RX_BB2 0x1C 1454#define RF_RX_BB1 0x1D 1455 1456#define RF_RCK1 0x1E 1457#define RF_RCK2 0x1F 1458 1459#define RF_TX_G1 0x20 1460#define RF_TX_G2 0x21 1461#define RF_TX_G3 0x22 1462 1463#define RF_TX_BB1 0x23 1464#define RF_T_METER 0x24 1465 1466#define RF_SYN_G1 0x25 1467#define RF_SYN_G2 0x26 1468#define RF_SYN_G3 0x27 1469#define RF_SYN_G4 0x28 1470#define RF_SYN_G5 0x29 1471#define RF_SYN_G6 0x2A 1472#define RF_SYN_G7 0x2B 1473#define RF_SYN_G8 0x2C 1474 1475#define RF_RCK_OS 0x30 1476#define RF_TXPA_G1 0x31 1477#define RF_TXPA_G2 0x32 1478#define RF_TXPA_G3 0x33 1479 1480#define BBBRESETB 0x100 1481#define BGLOBALRESETB 0x200 1482#define BOFDMTXSTART 0x4 1483#define BCCKTXSTART 0x8 1484#define BCRC32DEBUG 0x100 1485#define BPMACLOOPBACK 0x10 1486#define BTXLSIG 0xffffff 1487#define BOFDMTXRATE 0xf 1488#define BOFDMTXRESERVED 0x10 1489#define BOFDMTXLENGTH 0x1ffe0 1490#define BOFDMTXPARITY 0x20000 1491#define BTXHTSIG1 0xffffff 1492#define BTXHTMCSRATE 0x7f 1493#define BTXHTBW 0x80 1494#define BTXHTLENGTH 0xffff00 1495#define BTXHTSIG2 0xffffff 1496#define BTXHTSMOOTHING 0x1 1497#define BTXHTSOUNDING 0x2 1498#define BTXHTRESERVED 0x4 1499#define BTXHTAGGREATION 0x8 1500#define BTXHTSTBC 0x30 1501#define BTXHTADVANCECODING 0x40 1502#define BTXHTSHORTGI 0x80 1503#define BTXHTNUMBERHT_LTF 0x300 1504#define BTXHTCRC8 0x3fc00 1505#define BCOUNTERRESET 0x10000 1506#define BNUMOFOFDMTX 0xffff 1507#define BNUMOFCCKTX 0xffff0000 1508#define BTXIDLEINTERVAL 0xffff 1509#define BOFDMSERVICE 0xffff0000 1510#define BTXMACHEADER 0xffffffff 1511#define BTXDATAINIT 0xff 1512#define BTXHTMODE 0x100 1513#define BTXDATATYPE 0x30000 1514#define BTXRANDOMSEED 0xffffffff 1515#define BCCKTXPREAMBLE 0x1 1516#define BCCKTXSFD 0xffff0000 1517#define BCCKTXSIG 0xff 1518#define BCCKTXSERVICE 0xff00 1519#define BCCKLENGTHEXT 0x8000 1520#define BCCKTXLENGHT 0xffff0000 1521#define BCCKTXCRC16 0xffff 1522#define BCCKTXSTATUS 0x1 1523#define BOFDMTXSTATUS 0x2 1524#define IS_BB_REG_OFFSET_92S(_Offset) \ 1525 ((_Offset >= 0x800) && (_Offset <= 0xfff)) 1526 1527#define BRFMOD 0x1 1528#define BJAPANMODE 0x2 1529#define BCCKTXSC 0x30 1530#define BCCKEN 0x1000000 1531#define BOFDMEN 0x2000000 1532 1533#define BOFDMRXADCPHASE 0x10000 1534#define BOFDMTXDACPHASE 0x40000 1535#define BXATXAGC 0x3f 1536 1537#define BXBTXAGC 0xf00 1538#define BXCTXAGC 0xf000 1539#define BXDTXAGC 0xf0000 1540 1541#define BPASTART 0xf0000000 1542#define BTRSTART 0x00f00000 1543#define BRFSTART 0x0000f000 1544#define BBBSTART 0x000000f0 1545#define BBBCCKSTART 0x0000000f 1546#define BPAEND 0xf 1547#define BTREND 0x0f000000 1548#define BRFEND 0x000f0000 1549#define BCCAMASK 0x000000f0 1550#define BR2RCCAMASK 0x00000f00 1551#define BHSSI_R2TDELAY 0xf8000000 1552#define BHSSI_T2RDELAY 0xf80000 1553#define BCONTXHSSI 0x400 1554#define BIGFROMCCK 0x200 1555#define BAGCADDRESS 0x3f 1556#define BRXHPTX 0x7000 1557#define BRXHP2RX 0x38000 1558#define BRXHPCCKINI 0xc0000 1559#define BAGCTXCODE 0xc00000 1560#define BAGCRXCODE 0x300000 1561 1562#define B3WIREDATALENGTH 0x800 1563#define B3WIREADDREAALENGTH 0x400 1564 1565#define B3WIRERFPOWERDOWN 0x1 1566#define B5GPAPEPOLARITY 0x40000000 1567#define B2GPAPEPOLARITY 0x80000000 1568#define BRFSW_TXDEFAULTANT 0x3 1569#define BRFSW_TXOPTIONANT 0x30 1570#define BRFSW_RXDEFAULTANT 0x300 1571#define BRFSW_RXOPTIONANT 0x3000 1572#define BRFSI_3WIREDATA 0x1 1573#define BRFSI_3WIRECLOCK 0x2 1574#define BRFSI_3WIRELOAD 0x4 1575#define BRFSI_3WIRERW 0x8 1576#define BRFSI_3WIRE 0xf 1577 1578#define BRFSI_RFENV 0x10 1579 1580#define BRFSI_TRSW 0x20 1581#define BRFSI_TRSWB 0x40 1582#define BRFSI_ANTSW 0x100 1583#define BRFSI_ANTSWB 0x200 1584#define BRFSI_PAPE 0x400 1585#define BRFSI_PAPE5G 0x800 1586#define BBANDSELECT 0x1 1587#define BHTSIG2_GI 0x80 1588#define BHTSIG2_SMOOTHING 0x01 1589#define BHTSIG2_SOUNDING 0x02 1590#define BHTSIG2_AGGREATON 0x08 1591#define BHTSIG2_STBC 0x30 1592#define BHTSIG2_ADVCODING 0x40 1593#define BHTSIG2_NUMOFHTLTF 0x300 1594#define BHTSIG2_CRC8 0x3fc 1595#define BHTSIG1_MCS 0x7f 1596#define BHTSIG1_BANDWIDTH 0x80 1597#define BHTSIG1_HTLENGTH 0xffff 1598#define BLSIG_RATE 0xf 1599#define BLSIG_RESERVED 0x10 1600#define BLSIG_LENGTH 0x1fffe 1601#define BLSIG_PARITY 0x20 1602#define BCCKRXPHASE 0x4 1603 1604#define BLSSIREADADDRESS 0x7f800000 1605#define BLSSIREADEDGE 0x80000000 1606 1607#define BLSSIREADBACKDATA 0xfffff 1608 1609#define BLSSIREADOKFLAG 0x1000 1610#define BCCKSAMPLERATE 0x8 1611#define BREGULATOR0STANDBY 0x1 1612#define BREGULATORPLLSTANDBY 0x2 1613#define BREGULATOR1STANDBY 0x4 1614#define BPLLPOWERUP 0x8 1615#define BDPLLPOWERUP 0x10 1616#define BDA10POWERUP 0x20 1617#define BAD7POWERUP 0x200 1618#define BDA6POWERUP 0x2000 1619#define BXTALPOWERUP 0x4000 1620#define B40MDCLKPOWERUP 0x8000 1621#define BDA6DEBUGMODE 0x20000 1622#define BDA6SWING 0x380000 1623 1624#define BADCLKPHASE 0x4000000 1625#define B80MCLKDELAY 0x18000000 1626#define BAFEWATCHDOGENABLE 0x20000000 1627 1628#define BXTALCAP01 0xc0000000 1629#define BXTALCAP23 0x3 1630#define BXTALCAP92X 0x0f000000 1631#define BXTALCAP 0x0f000000 1632 1633#define BINTDIFCLKENABLE 0x400 1634#define BEXTSIGCLKENABLE 0x800 1635#define BBANDGAP_MBIAS_POWERUP 0x10000 1636#define BAD11SH_GAIN 0xc0000 1637#define BAD11NPUT_RANGE 0x700000 1638#define BAD110P_CURRENT 0x3800000 1639#define BLPATH_LOOPBACK 0x4000000 1640#define BQPATH_LOOPBACK 0x8000000 1641#define BAFE_LOOPBACK 0x10000000 1642#define BDA10_SWING 0x7e0 1643#define BDA10_REVERSE 0x800 1644#define BDA_CLK_SOURCE 0x1000 1645#define BDA7INPUT_RANGE 0x6000 1646#define BDA7_GAIN 0x38000 1647#define BDA7OUTPUT_CM_MODE 0x40000 1648#define BDA7INPUT_CM_MODE 0x380000 1649#define BDA7CURRENT 0xc00000 1650#define BREGULATOR_ADJUST 0x7000000 1651#define BAD11POWERUP_ATTX 0x1 1652#define BDA10PS_ATTX 0x10 1653#define BAD11POWERUP_ATRX 0x100 1654#define BDA10PS_ATRX 0x1000 1655#define BCCKRX_AGC_FORMAT 0x200 1656#define BPSDFFT_SAMPLE_POINT 0xc000 1657#define BPSD_AVERAGE_NUM 0x3000 1658#define BIQPATH_CONTROL 0xc00 1659#define BPSD_FREQ 0x3ff 1660#define BPSD_ANTENNA_PATH 0x30 1661#define BPSD_IQ_SWITCH 0x40 1662#define BPSD_RX_TRIGGER 0x400000 1663#define BPSD_TX_TRIGGER 0x80000000 1664#define BPSD_SINE_TONE_SCALE 0x7f000000 1665#define BPSD_REPORT 0xffff 1666 1667#define BOFDM_TXSC 0x30000000 1668#define BCCK_TXON 0x1 1669#define BOFDM_TXON 0x2 1670#define BDEBUG_PAGE 0xfff 1671#define BDEBUG_ITEM 0xff 1672#define BANTL 0x10 1673#define BANT_NONHT 0x100 1674#define BANT_HT1 0x1000 1675#define BANT_HT2 0x10000 1676#define BANT_HT1S1 0x100000 1677#define BANT_NONHTS1 0x1000000 1678 1679#define BCCK_BBMODE 0x3 1680#define BCCK_TXPOWERSAVING 0x80 1681#define BCCK_RXPOWERSAVING 0x40 1682 1683#define BCCK_SIDEBAND 0x10 1684 1685#define BCCK_SCRAMBLE 0x8 1686#define BCCK_ANTDIVERSITY 0x8000 1687#define BCCK_CARRIER_RECOVERY 0x4000 1688#define BCCK_TXRATE 0x3000 1689#define BCCK_DCCANCEL 0x0800 1690#define BCCK_ISICANCEL 0x0400 1691#define BCCK_MATCH_FILTER 0x0200 1692#define BCCK_EQUALIZER 0x0100 1693#define BCCK_PREAMBLE_DETECT 0x800000 1694#define BCCK_FAST_FALSECCA 0x400000 1695#define BCCK_CH_ESTSTART 0x300000 1696#define BCCK_CCA_COUNT 0x080000 1697#define BCCK_CS_LIM 0x070000 1698#define BCCK_BIST_MODE 0x80000000 1699#define BCCK_CCAMASK 0x40000000 1700#define BCCK_TX_DAC_PHASE 0x4 1701#define BCCK_RX_ADC_PHASE 0x20000000 1702#define BCCKR_CP_MODE 0x0100 1703#define BCCK_TXDC_OFFSET 0xf0 1704#define BCCK_RXDC_OFFSET 0xf 1705#define BCCK_CCA_MODE 0xc000 1706#define BCCK_FALSECS_LIM 0x3f00 1707#define BCCK_CS_RATIO 0xc00000 1708#define BCCK_CORGBIT_SEL 0x300000 1709#define BCCK_PD_LIM 0x0f0000 1710#define BCCK_NEWCCA 0x80000000 1711#define BCCK_RXHP_OF_IG 0x8000 1712#define BCCK_RXIG 0x7f00 1713#define BCCK_LNA_POLARITY 0x800000 1714#define BCCK_RX1ST_BAIN 0x7f0000 1715#define BCCK_RF_EXTEND 0x20000000 1716#define BCCK_RXAGC_SATLEVEL 0x1f000000 1717#define BCCK_RXAGC_SATCOUNT 0xe0 1718#define bCCKRxRFSettle 0x1f 1719#define BCCK_FIXED_RXAGC 0x8000 1720#define BCCK_ANTENNA_POLARITY 0x2000 1721#define BCCK_TXFILTER_TYPE 0x0c00 1722#define BCCK_RXAGC_REPORTTYPE 0x0300 1723#define BCCK_RXDAGC_EN 0x80000000 1724#define BCCK_RXDAGC_PERIOD 0x20000000 1725#define BCCK_RXDAGC_SATLEVEL 0x1f000000 1726#define BCCK_TIMING_RECOVERY 0x800000 1727#define BCCK_TXC0 0x3f0000 1728#define BCCK_TXC1 0x3f000000 1729#define BCCK_TXC2 0x3f 1730#define BCCK_TXC3 0x3f00 1731#define BCCK_TXC4 0x3f0000 1732#define BCCK_TXC5 0x3f000000 1733#define BCCK_TXC6 0x3f 1734#define BCCK_TXC7 0x3f00 1735#define BCCK_DEBUGPORT 0xff0000 1736#define BCCK_DAC_DEBUG 0x0f000000 1737#define BCCK_FALSEALARM_ENABLE 0x8000 1738#define BCCK_FALSEALARM_READ 0x4000 1739#define BCCK_TRSSI 0x7f 1740#define BCCK_RXAGC_REPORT 0xfe 1741#define BCCK_RXREPORT_ANTSEL 0x80000000 1742#define BCCK_RXREPORT_MFOFF 0x40000000 1743#define BCCK_RXREPORT_SQLOSS 0x20000000 1744#define BCCK_RXREPORT_PKTLOSS 0x10000000 1745#define BCCK_RXREPORT_LOCKEDBIT 0x08000000 1746#define BCCK_RXREPORT_RATEERROR 0x04000000 1747#define BCCK_RXREPORT_RXRATE 0x03000000 1748#define BCCK_RXFA_COUNTER_LOWER 0xff 1749#define BCCK_RXFA_COUNTER_UPPER 0xff000000 1750#define BCCK_RXHPAGC_START 0xe000 1751#define BCCK_RXHPAGC_FINAL 0x1c00 1752#define BCCK_RXFALSEALARM_ENABLE 0x8000 1753#define BCCK_FACOUNTER_FREEZE 0x4000 1754#define BCCK_TXPATH_SEL 0x10000000 1755#define BCCK_DEFAULT_RXPATH 0xc000000 1756#define BCCK_OPTION_RXPATH 0x3000000 1757 1758#define BNUM_OFSTF 0x3 1759#define BSHIFT_L 0xc0 1760#define BGI_TH 0xc 1761#define BRXPATH_A 0x1 1762#define BRXPATH_B 0x2 1763#define BRXPATH_C 0x4 1764#define BRXPATH_D 0x8 1765#define BTXPATH_A 0x1 1766#define BTXPATH_B 0x2 1767#define BTXPATH_C 0x4 1768#define BTXPATH_D 0x8 1769#define BTRSSI_FREQ 0x200 1770#define BADC_BACKOFF 0x3000 1771#define BDFIR_BACKOFF 0xc000 1772#define BTRSSI_LATCH_PHASE 0x10000 1773#define BRX_LDC_OFFSET 0xff 1774#define BRX_QDC_OFFSET 0xff00 1775#define BRX_DFIR_MODE 0x1800000 1776#define BRX_DCNF_TYPE 0xe000000 1777#define BRXIQIMB_A 0x3ff 1778#define BRXIQIMB_B 0xfc00 1779#define BRXIQIMB_C 0x3f0000 1780#define BRXIQIMB_D 0xffc00000 1781#define BDC_DC_NOTCH 0x60000 1782#define BRXNB_NOTCH 0x1f000000 1783#define BPD_TH 0xf 1784#define BPD_TH_OPT2 0xc000 1785#define BPWED_TH 0x700 1786#define BIFMF_WIN_L 0x800 1787#define BPD_OPTION 0x1000 1788#define BMF_WIN_L 0xe000 1789#define BBW_SEARCH_L 0x30000 1790#define BWIN_ENH_L 0xc0000 1791#define BBW_TH 0x700000 1792#define BED_TH2 0x3800000 1793#define BBW_OPTION 0x4000000 1794#define BRADIO_TH 0x18000000 1795#define BWINDOW_L 0xe0000000 1796#define BSBD_OPTION 0x1 1797#define BFRAME_TH 0x1c 1798#define BFS_OPTION 0x60 1799#define BDC_SLOPE_CHECK 0x80 1800#define BFGUARD_COUNTER_DC_L 0xe00 1801#define BFRAME_WEIGHT_SHORT 0x7000 1802#define BSUB_TUNE 0xe00000 1803#define BFRAME_DC_LENGTH 0xe000000 1804#define BSBD_START_OFFSET 0x30000000 1805#define BFRAME_TH_2 0x7 1806#define BFRAME_GI2_TH 0x38 1807#define BGI2_SYNC_EN 0x40 1808#define BSARCH_SHORT_EARLY 0x300 1809#define BSARCH_SHORT_LATE 0xc00 1810#define BSARCH_GI2_LATE 0x70000 1811#define BCFOANTSUM 0x1 1812#define BCFOACC 0x2 1813#define BCFOSTARTOFFSET 0xc 1814#define BCFOLOOPBACK 0x70 1815#define BCFOSUMWEIGHT 0x80 1816#define BDAGCENABLE 0x10000 1817#define BTXIQIMB_A 0x3ff 1818#define BTXIQIMB_b 0xfc00 1819#define BTXIQIMB_C 0x3f0000 1820#define BTXIQIMB_D 0xffc00000 1821#define BTXIDCOFFSET 0xff 1822#define BTXIQDCOFFSET 0xff00 1823#define BTXDFIRMODE 0x10000 1824#define BTXPESUDO_NOISEON 0x4000000 1825#define BTXPESUDO_NOISE_A 0xff 1826#define BTXPESUDO_NOISE_B 0xff00 1827#define BTXPESUDO_NOISE_C 0xff0000 1828#define BTXPESUDO_NOISE_D 0xff000000 1829#define BCCA_DROPOPTION 0x20000 1830#define BCCA_DROPTHRES 0xfff00000 1831#define BEDCCA_H 0xf 1832#define BEDCCA_L 0xf0 1833#define BLAMBDA_ED 0x300 1834#define BRX_INITIALGAIN 0x7f 1835#define BRX_ANTDIV_EN 0x80 1836#define BRX_AGC_ADDRESS_FOR_LNA 0x7f00 1837#define BRX_HIGHPOWER_FLOW 0x8000 1838#define BRX_AGC_FREEZE_THRES 0xc0000 1839#define BRX_FREEZESTEP_AGC1 0x300000 1840#define BRX_FREEZESTEP_AGC2 0xc00000 1841#define BRX_FREEZESTEP_AGC3 0x3000000 1842#define BRX_FREEZESTEP_AGC0 0xc000000 1843#define BRXRSSI_CMP_EN 0x10000000 1844#define BRXQUICK_AGCEN 0x20000000 1845#define BRXAGC_FREEZE_THRES_MODE 0x40000000 1846#define BRX_OVERFLOW_CHECKTYPE 0x80000000 1847#define BRX_AGCSHIFT 0x7f 1848#define BTRSW_TRI_ONLY 0x80 1849#define BPOWER_THRES 0x300 1850#define BRXAGC_EN 0x1 1851#define BRXAGC_TOGETHER_EN 0x2 1852#define BRXAGC_MIN 0x4 1853#define BRXHP_INI 0x7 1854#define BRXHP_TRLNA 0x70 1855#define BRXHP_RSSI 0x700 1856#define BRXHP_BBP1 0x7000 1857#define BRXHP_BBP2 0x70000 1858#define BRXHP_BBP3 0x700000 1859#define BRSSI_H 0x7f0000 1860#define BRSSI_GEN 0x7f000000 1861#define BRXSETTLE_TRSW 0x7 1862#define BRXSETTLE_LNA 0x38 1863#define BRXSETTLE_RSSI 0x1c0 1864#define BRXSETTLE_BBP 0xe00 1865#define BRXSETTLE_RXHP 0x7000 1866#define BRXSETTLE_ANTSW_RSSI 0x38000 1867#define BRXSETTLE_ANTSW 0xc0000 1868#define BRXPROCESS_TIME_DAGC 0x300000 1869#define BRXSETTLE_HSSI 0x400000 1870#define BRXPROCESS_TIME_BBPPW 0x800000 1871#define BRXANTENNA_POWER_SHIFT 0x3000000 1872#define BRSSI_TABLE_SELECT 0xc000000 1873#define BRXHP_FINAL 0x7000000 1874#define BRXHPSETTLE_BBP 0x7 1875#define BRXHTSETTLE_HSSI 0x8 1876#define BRXHTSETTLE_RXHP 0x70 1877#define BRXHTSETTLE_BBPPW 0x80 1878#define BRXHTSETTLE_IDLE 0x300 1879#define BRXHTSETTLE_RESERVED 0x1c00 1880#define BRXHT_RXHP_EN 0x8000 1881#define BRXAGC_FREEZE_THRES 0x30000 1882#define BRXAGC_TOGETHEREN 0x40000 1883#define BRXHTAGC_MIN 0x80000 1884#define BRXHTAGC_EN 0x100000 1885#define BRXHTDAGC_EN 0x200000 1886#define BRXHT_RXHP_BBP 0x1c00000 1887#define BRXHT_RXHP_FINAL 0xe0000000 1888#define BRXPW_RADIO_TH 0x3 1889#define BRXPW_RADIO_EN 0x4 1890#define BRXMF_HOLD 0x3800 1891#define BRXPD_DELAY_TH1 0x38 1892#define BRXPD_DELAY_TH2 0x1c0 1893#define BRXPD_DC_COUNT_MAX 0x600 1894#define BRXPD_DELAY_TH 0x8000 1895#define BRXPROCESS_DELAY 0xf0000 1896#define BRXSEARCHRANGE_GI2_EARLY 0x700000 1897#define BRXFRAME_FUARD_COUNTER_L 0x3800000 1898#define BRXSGI_GUARD_L 0xc000000 1899#define BRXSGI_SEARCH_L 0x30000000 1900#define BRXSGI_TH 0xc0000000 1901#define BDFSCNT0 0xff 1902#define BDFSCNT1 0xff00 1903#define BDFSFLAG 0xf0000 1904#define BMF_WEIGHT_SUM 0x300000 1905#define BMINIDX_TH 0x7f000000 1906#define BDAFORMAT 0x40000 1907#define BTXCH_EMU_ENABLE 0x01000000 1908#define BTRSW_ISOLATION_A 0x7f 1909#define BTRSW_ISOLATION_B 0x7f00 1910#define BTRSW_ISOLATION_C 0x7f0000 1911#define BTRSW_ISOLATION_D 0x7f000000 1912#define BEXT_LNA_GAIN 0x7c00 1913 1914#define BSTBC_EN 0x4 1915#define BANTENNA_MAPPING 0x10 1916#define BNSS 0x20 1917#define BCFO_ANTSUM_ID 0x200 1918#define BPHY_COUNTER_RESET 0x8000000 1919#define BCFO_REPORT_GET 0x4000000 1920#define BOFDM_CONTINUE_TX 0x10000000 1921#define BOFDM_SINGLE_CARRIER 0x20000000 1922#define BOFDM_SINGLE_TONE 0x40000000 1923#define BHT_DETECT 0x100 1924#define BCFOEN 0x10000 1925#define BCFOVALUE 0xfff00000 1926#define BSIGTONE_RE 0x3f 1927#define BSIGTONE_IM 0x7f00 1928#define BCOUNTER_CCA 0xffff 1929#define BCOUNTER_PARITYFAIL 0xffff0000 1930#define BCOUNTER_RATEILLEGAL 0xffff 1931#define BCOUNTER_CRC8FAIL 0xffff0000 1932#define BCOUNTER_MCSNOSUPPORT 0xffff 1933#define BCOUNTER_FASTSYNC 0xffff 1934#define BSHORTCFO 0xfff 1935#define BSHORTCFOT_LENGTH 12 1936#define BSHORTCFOF_LENGTH 11 1937#define BLONGCFO 0x7ff 1938#define BLONGCFOT_LENGTH 11 1939#define BLONGCFOF_LENGTH 11 1940#define BTAILCFO 0x1fff 1941#define BTAILCFOT_LENGTH 13 1942#define BTAILCFOF_LENGTH 12 1943#define BNOISE_EN_PWDB 0xffff 1944#define BCC_POWER_DB 0xffff0000 1945#define BMOISE_PWDB 0xffff 1946#define BPOWERMEAST_LENGTH 10 1947#define BPOWERMEASF_LENGTH 3 1948#define BRX_HT_BW 0x1 1949#define BRXSC 0x6 1950#define BRX_HT 0x8 1951#define BNB_INTF_DET_ON 0x1 1952#define BINTF_WIN_LEN_CFG 0x30 1953#define BNB_INTF_TH_CFG 0x1c0 1954#define BRFGAIN 0x3f 1955#define BTABLESEL 0x40 1956#define BTRSW 0x80 1957#define BRXSNR_A 0xff 1958#define BRXSNR_B 0xff00 1959#define BRXSNR_C 0xff0000 1960#define BRXSNR_D 0xff000000 1961#define BSNR_EVMT_LENGTH 8 1962#define BSNR_EVMF_LENGTH 1 1963#define BCSI1ST 0xff 1964#define BCSI2ND 0xff00 1965#define BRXEVM1ST 0xff0000 1966#define BRXEVM2ND 0xff000000 1967#define BSIGEVM 0xff 1968#define BPWDB 0xff00 1969#define BSGIEN 0x10000 1970 1971#define BSFACTOR_QMA1 0xf 1972#define BSFACTOR_QMA2 0xf0 1973#define BSFACTOR_QMA3 0xf00 1974#define BSFACTOR_QMA4 0xf000 1975#define BSFACTOR_QMA5 0xf0000 1976#define BSFACTOR_QMA6 0xf0000 1977#define BSFACTOR_QMA7 0xf00000 1978#define BSFACTOR_QMA8 0xf000000 1979#define BSFACTOR_QMA9 0xf0000000 1980#define BCSI_SCHEME 0x100000 1981 1982#define BNOISE_LVL_TOP_SET 0x3 1983#define BCHSMOOTH 0x4 1984#define BCHSMOOTH_CFG1 0x38 1985#define BCHSMOOTH_CFG2 0x1c0 1986#define BCHSMOOTH_CFG3 0xe00 1987#define BCHSMOOTH_CFG4 0x7000 1988#define BMRCMODE 0x800000 1989#define BTHEVMCFG 0x7000000 1990 1991#define BLOOP_FIT_TYPE 0x1 1992#define BUPD_CFO 0x40 1993#define BUPD_CFO_OFFDATA 0x80 1994#define BADV_UPD_CFO 0x100 1995#define BADV_TIME_CTRL 0x800 1996#define BUPD_CLKO 0x1000 1997#define BFC 0x6000 1998#define BTRACKING_MODE 0x8000 1999#define BPHCMP_ENABLE 0x10000 2000#define BUPD_CLKO_LTF 0x20000
2001#define BCOM_CH_CFO 0x40000 2002#define BCSI_ESTI_MODE 0x80000 2003#define BADV_UPD_EQZ 0x100000 2004#define BUCHCFG 0x7000000 2005#define BUPDEQZ 0x8000000 2006 2007#define BRX_PESUDO_NOISE_ON 0x20000000 2008#define BRX_PESUDO_NOISE_A 0xff 2009#define BRX_PESUDO_NOISE_B 0xff00 2010#define BRX_PESUDO_NOISE_C 0xff0000 2011#define BRX_PESUDO_NOISE_D 0xff000000 2012#define BRX_PESUDO_NOISESTATE_A 0xffff 2013#define BRX_PESUDO_NOISESTATE_B 0xffff0000 2014#define BRX_PESUDO_NOISESTATE_C 0xffff 2015#define BRX_PESUDO_NOISESTATE_D 0xffff0000 2016 2017#define BZEBRA1_HSSIENABLE 0x8 2018#define BZEBRA1_TRXCONTROL 0xc00 2019#define BZEBRA1_TRXGAINSETTING 0x07f 2020#define BZEBRA1_RXCOUNTER 0xc00 2021#define BZEBRA1_TXCHANGEPUMP 0x38 2022#define BZEBRA1_RXCHANGEPUMP 0x7 2023#define BZEBRA1_CHANNEL_NUM 0xf80 2024#define BZEBRA1_TXLPFBW 0x400 2025#define BZEBRA1_RXLPFBW 0x600 2026 2027#define BRTL8256REG_MODE_CTRL1 0x100 2028#define BRTL8256REG_MODE_CTRL0 0x40 2029#define BRTL8256REG_TXLPFBW 0x18 2030#define BRTL8256REG_RXLPFBW 0x600 2031 2032#define BRTL8258_TXLPFBW 0xc 2033#define BRTL8258_RXLPFBW 0xc00 2034#define BRTL8258_RSSILPFBW 0xc0 2035 2036#define BBYTE0 0x1 2037#define BBYTE1 0x2 2038#define BBYTE2 0x4 2039#define BBYTE3 0x8 2040#define BWORD0 0x3 2041#define BWORD1 0xc 2042#define BWORD 0xf 2043 2044#define BENABLE 0x1 2045#define BDISABLE 0x0 2046 2047#define LEFT_ANTENNA 0x0 2048#define RIGHT_ANTENNA 0x1 2049 2050#define TCHECK_TXSTATUS 500 2051#define TUPDATE_RXCOUNTER 100 2052 2053#endif 2054