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23
24#ifndef __CONF_H__
25#define __CONF_H__
26
27enum {
28 CONF_HW_BIT_RATE_1MBPS = BIT(0),
29 CONF_HW_BIT_RATE_2MBPS = BIT(1),
30 CONF_HW_BIT_RATE_5_5MBPS = BIT(2),
31 CONF_HW_BIT_RATE_6MBPS = BIT(3),
32 CONF_HW_BIT_RATE_9MBPS = BIT(4),
33 CONF_HW_BIT_RATE_11MBPS = BIT(5),
34 CONF_HW_BIT_RATE_12MBPS = BIT(6),
35 CONF_HW_BIT_RATE_18MBPS = BIT(7),
36 CONF_HW_BIT_RATE_22MBPS = BIT(8),
37 CONF_HW_BIT_RATE_24MBPS = BIT(9),
38 CONF_HW_BIT_RATE_36MBPS = BIT(10),
39 CONF_HW_BIT_RATE_48MBPS = BIT(11),
40 CONF_HW_BIT_RATE_54MBPS = BIT(12),
41 CONF_HW_BIT_RATE_MCS_0 = BIT(13),
42 CONF_HW_BIT_RATE_MCS_1 = BIT(14),
43 CONF_HW_BIT_RATE_MCS_2 = BIT(15),
44 CONF_HW_BIT_RATE_MCS_3 = BIT(16),
45 CONF_HW_BIT_RATE_MCS_4 = BIT(17),
46 CONF_HW_BIT_RATE_MCS_5 = BIT(18),
47 CONF_HW_BIT_RATE_MCS_6 = BIT(19),
48 CONF_HW_BIT_RATE_MCS_7 = BIT(20),
49 CONF_HW_BIT_RATE_MCS_8 = BIT(21),
50 CONF_HW_BIT_RATE_MCS_9 = BIT(22),
51 CONF_HW_BIT_RATE_MCS_10 = BIT(23),
52 CONF_HW_BIT_RATE_MCS_11 = BIT(24),
53 CONF_HW_BIT_RATE_MCS_12 = BIT(25),
54 CONF_HW_BIT_RATE_MCS_13 = BIT(26),
55 CONF_HW_BIT_RATE_MCS_14 = BIT(27),
56 CONF_HW_BIT_RATE_MCS_15 = BIT(28),
57};
58
59enum {
60 CONF_HW_RATE_INDEX_1MBPS = 0,
61 CONF_HW_RATE_INDEX_2MBPS = 1,
62 CONF_HW_RATE_INDEX_5_5MBPS = 2,
63 CONF_HW_RATE_INDEX_11MBPS = 3,
64 CONF_HW_RATE_INDEX_6MBPS = 4,
65 CONF_HW_RATE_INDEX_9MBPS = 5,
66 CONF_HW_RATE_INDEX_12MBPS = 6,
67 CONF_HW_RATE_INDEX_18MBPS = 7,
68 CONF_HW_RATE_INDEX_24MBPS = 8,
69 CONF_HW_RATE_INDEX_36MBPS = 9,
70 CONF_HW_RATE_INDEX_48MBPS = 10,
71 CONF_HW_RATE_INDEX_54MBPS = 11,
72 CONF_HW_RATE_INDEX_MCS0 = 12,
73 CONF_HW_RATE_INDEX_MCS1 = 13,
74 CONF_HW_RATE_INDEX_MCS2 = 14,
75 CONF_HW_RATE_INDEX_MCS3 = 15,
76 CONF_HW_RATE_INDEX_MCS4 = 16,
77 CONF_HW_RATE_INDEX_MCS5 = 17,
78 CONF_HW_RATE_INDEX_MCS6 = 18,
79 CONF_HW_RATE_INDEX_MCS7 = 19,
80 CONF_HW_RATE_INDEX_MCS7_SGI = 20,
81 CONF_HW_RATE_INDEX_MCS0_40MHZ = 21,
82 CONF_HW_RATE_INDEX_MCS1_40MHZ = 22,
83 CONF_HW_RATE_INDEX_MCS2_40MHZ = 23,
84 CONF_HW_RATE_INDEX_MCS3_40MHZ = 24,
85 CONF_HW_RATE_INDEX_MCS4_40MHZ = 25,
86 CONF_HW_RATE_INDEX_MCS5_40MHZ = 26,
87 CONF_HW_RATE_INDEX_MCS6_40MHZ = 27,
88 CONF_HW_RATE_INDEX_MCS7_40MHZ = 28,
89 CONF_HW_RATE_INDEX_MCS7_40MHZ_SGI = 29,
90
91
92 CONF_HW_RATE_INDEX_MCS8 = 21,
93 CONF_HW_RATE_INDEX_MCS9 = 22,
94 CONF_HW_RATE_INDEX_MCS10 = 23,
95 CONF_HW_RATE_INDEX_MCS11 = 24,
96 CONF_HW_RATE_INDEX_MCS12 = 25,
97 CONF_HW_RATE_INDEX_MCS13 = 26,
98 CONF_HW_RATE_INDEX_MCS14 = 27,
99 CONF_HW_RATE_INDEX_MCS15 = 28,
100 CONF_HW_RATE_INDEX_MCS15_SGI = 29,
101
102 CONF_HW_RATE_INDEX_MAX = CONF_HW_RATE_INDEX_MCS7_40MHZ_SGI,
103};
104
105#define CONF_HW_RXTX_RATE_UNSUPPORTED 0xff
106
107enum {
108 CONF_SG_DISABLE = 0,
109 CONF_SG_PROTECTIVE,
110 CONF_SG_OPPORTUNISTIC
111};
112
113#define WLCORE_CONF_SG_PARAMS_MAX 67
114#define WLCORE_CONF_SG_PARAMS_ALL 0xff
115
116struct conf_sg_settings {
117 u32 params[WLCORE_CONF_SG_PARAMS_MAX];
118 u8 state;
119} __packed;
120
121enum conf_rx_queue_type {
122 CONF_RX_QUEUE_TYPE_LOW_PRIORITY,
123 CONF_RX_QUEUE_TYPE_HIGH_PRIORITY,
124};
125
126struct conf_rx_settings {
127
128
129
130
131
132
133 u32 rx_msdu_life_time;
134
135
136
137
138
139
140 u32 packet_detection_threshold;
141
142
143
144
145
146
147
148 u16 ps_poll_timeout;
149
150
151
152
153
154
155 u16 upsd_timeout;
156
157
158
159
160
161
162
163 u16 rts_threshold;
164
165
166
167
168
169
170
171
172 u16 rx_cca_threshold;
173
174
175
176
177
178
179
180 u16 irq_blk_threshold;
181
182
183
184
185
186
187
188 u16 irq_pkt_threshold;
189
190
191
192
193
194
195 u16 irq_timeout;
196
197
198
199
200
201
202 u8 queue_type;
203} __packed;
204
205#define CONF_TX_MAX_RATE_CLASSES 10
206
207#define CONF_TX_RATE_MASK_UNSPECIFIED 0
208#define CONF_TX_RATE_MASK_BASIC (CONF_HW_BIT_RATE_1MBPS | \
209 CONF_HW_BIT_RATE_2MBPS)
210#define CONF_TX_RATE_RETRY_LIMIT 10
211
212
213#define CONF_TX_RATE_MASK_BASIC_P2P CONF_HW_BIT_RATE_6MBPS
214
215
216
217
218
219
220#define CONF_TX_ENABLED_RATES (CONF_HW_BIT_RATE_1MBPS | \
221 CONF_HW_BIT_RATE_2MBPS | CONF_HW_BIT_RATE_5_5MBPS | \
222 CONF_HW_BIT_RATE_6MBPS | CONF_HW_BIT_RATE_9MBPS | \
223 CONF_HW_BIT_RATE_11MBPS | CONF_HW_BIT_RATE_12MBPS | \
224 CONF_HW_BIT_RATE_18MBPS | CONF_HW_BIT_RATE_24MBPS | \
225 CONF_HW_BIT_RATE_36MBPS | CONF_HW_BIT_RATE_48MBPS | \
226 CONF_HW_BIT_RATE_54MBPS)
227
228#define CONF_TX_CCK_RATES (CONF_HW_BIT_RATE_1MBPS | \
229 CONF_HW_BIT_RATE_2MBPS | CONF_HW_BIT_RATE_5_5MBPS | \
230 CONF_HW_BIT_RATE_11MBPS)
231
232#define CONF_TX_OFDM_RATES (CONF_HW_BIT_RATE_6MBPS | \
233 CONF_HW_BIT_RATE_12MBPS | CONF_HW_BIT_RATE_24MBPS | \
234 CONF_HW_BIT_RATE_36MBPS | CONF_HW_BIT_RATE_48MBPS | \
235 CONF_HW_BIT_RATE_54MBPS)
236
237#define CONF_TX_MCS_RATES (CONF_HW_BIT_RATE_MCS_0 | \
238 CONF_HW_BIT_RATE_MCS_1 | CONF_HW_BIT_RATE_MCS_2 | \
239 CONF_HW_BIT_RATE_MCS_3 | CONF_HW_BIT_RATE_MCS_4 | \
240 CONF_HW_BIT_RATE_MCS_5 | CONF_HW_BIT_RATE_MCS_6 | \
241 CONF_HW_BIT_RATE_MCS_7)
242
243#define CONF_TX_MIMO_RATES (CONF_HW_BIT_RATE_MCS_8 | \
244 CONF_HW_BIT_RATE_MCS_9 | CONF_HW_BIT_RATE_MCS_10 | \
245 CONF_HW_BIT_RATE_MCS_11 | CONF_HW_BIT_RATE_MCS_12 | \
246 CONF_HW_BIT_RATE_MCS_13 | CONF_HW_BIT_RATE_MCS_14 | \
247 CONF_HW_BIT_RATE_MCS_15)
248
249
250
251
252
253#define CONF_TX_AP_DEFAULT_MGMT_RATES (CONF_HW_BIT_RATE_1MBPS | \
254 CONF_HW_BIT_RATE_2MBPS | CONF_HW_BIT_RATE_5_5MBPS)
255
256
257#define CONF_TX_IBSS_DEFAULT_RATES (CONF_HW_BIT_RATE_1MBPS | \
258 CONF_HW_BIT_RATE_2MBPS | CONF_HW_BIT_RATE_5_5MBPS | \
259 CONF_HW_BIT_RATE_11MBPS | CONF_TX_OFDM_RATES);
260
261struct conf_tx_rate_class {
262
263
264
265
266
267
268 u32 enabled_rates;
269
270
271
272
273
274
275 u8 short_retry_limit;
276
277
278
279
280
281
282 u8 long_retry_limit;
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300 u8 aflags;
301} __packed;
302
303#define CONF_TX_MAX_AC_COUNT 4
304
305
306#define CONF_TX_AIFS_PIFS 1
307
308
309#define CONF_TX_AIFS_DIFS 2
310
311
312enum conf_tx_ac {
313 CONF_TX_AC_BE = 0,
314 CONF_TX_AC_BK = 1,
315 CONF_TX_AC_VI = 2,
316 CONF_TX_AC_VO = 3,
317 CONF_TX_AC_CTS2SELF = 4,
318 CONF_TX_AC_ANY_TID = 0xff
319};
320
321struct conf_tx_ac_category {
322
323
324
325
326
327 u8 ac;
328
329
330
331
332
333
334
335 u8 cw_min;
336
337
338
339
340
341
342
343 u16 cw_max;
344
345
346
347
348
349
350 u8 aifsn;
351
352
353
354
355
356
357 u16 tx_op_limit;
358} __packed;
359
360#define CONF_TX_MAX_TID_COUNT 8
361
362
363#define CONF_TX_BA_ENABLED_TID_BITMAP 0x3F
364
365enum {
366 CONF_CHANNEL_TYPE_DCF = 0,
367 CONF_CHANNEL_TYPE_EDCF = 1,
368 CONF_CHANNEL_TYPE_HCCA = 2,
369};
370
371enum {
372 CONF_PS_SCHEME_LEGACY = 0,
373 CONF_PS_SCHEME_UPSD_TRIGGER = 1,
374 CONF_PS_SCHEME_LEGACY_PSPOLL = 2,
375 CONF_PS_SCHEME_SAPSD = 3,
376};
377
378enum {
379 CONF_ACK_POLICY_LEGACY = 0,
380 CONF_ACK_POLICY_NO_ACK = 1,
381 CONF_ACK_POLICY_BLOCK = 2,
382};
383
384
385struct conf_tx_tid {
386 u8 queue_id;
387 u8 channel_type;
388 u8 tsid;
389 u8 ps_scheme;
390 u8 ack_policy;
391 u32 apsd_conf[2];
392} __packed;
393
394struct conf_tx_settings {
395
396
397
398
399
400 u8 tx_energy_detection;
401
402
403
404
405
406 struct conf_tx_rate_class sta_rc_conf;
407
408
409
410
411 u8 ac_conf_count;
412 struct conf_tx_ac_category ac_conf[CONF_TX_MAX_AC_COUNT];
413
414
415
416
417
418
419
420 u8 max_tx_retries;
421
422
423
424
425
426 u16 ap_aging_period;
427
428
429
430
431 u8 tid_conf_count;
432 struct conf_tx_tid tid_conf[CONF_TX_MAX_TID_COUNT];
433
434
435
436
437
438
439 u16 frag_threshold;
440
441
442
443
444
445
446 u16 tx_compl_timeout;
447
448
449
450
451
452
453
454 u16 tx_compl_threshold;
455
456
457
458
459
460
461 u32 basic_rate;
462
463
464
465
466
467
468 u32 basic_rate_5;
469
470
471
472
473 u8 tmpl_short_retry_limit;
474 u8 tmpl_long_retry_limit;
475
476
477 u32 tx_watchdog_timeout;
478
479
480
481
482
483 u8 slow_link_thold;
484
485
486
487
488
489 u8 fast_link_thold;
490} __packed;
491
492enum {
493 CONF_WAKE_UP_EVENT_BEACON = 0x01,
494 CONF_WAKE_UP_EVENT_DTIM = 0x02,
495 CONF_WAKE_UP_EVENT_N_DTIM = 0x04,
496 CONF_WAKE_UP_EVENT_N_BEACONS = 0x08,
497 CONF_WAKE_UP_EVENT_BITS_MASK = 0x0F
498};
499
500#define CONF_MAX_BCN_FILT_IE_COUNT 32
501
502#define CONF_BCN_RULE_PASS_ON_CHANGE BIT(0)
503#define CONF_BCN_RULE_PASS_ON_APPEARANCE BIT(1)
504
505#define CONF_BCN_IE_OUI_LEN 3
506#define CONF_BCN_IE_VER_LEN 2
507
508struct conf_bcn_filt_rule {
509
510
511
512
513
514 u8 ie;
515
516
517
518
519
520
521 u8 rule;
522
523
524
525
526 u8 oui[CONF_BCN_IE_OUI_LEN];
527
528
529
530
531 u8 type;
532
533
534
535
536 u8 version[CONF_BCN_IE_VER_LEN];
537} __packed;
538
539#define CONF_MAX_RSSI_SNR_TRIGGERS 8
540
541enum {
542 CONF_TRIG_METRIC_RSSI_BEACON = 0,
543 CONF_TRIG_METRIC_RSSI_DATA,
544 CONF_TRIG_METRIC_SNR_BEACON,
545 CONF_TRIG_METRIC_SNR_DATA
546};
547
548enum {
549 CONF_TRIG_EVENT_TYPE_LEVEL = 0,
550 CONF_TRIG_EVENT_TYPE_EDGE
551};
552
553enum {
554 CONF_TRIG_EVENT_DIR_LOW = 0,
555 CONF_TRIG_EVENT_DIR_HIGH,
556 CONF_TRIG_EVENT_DIR_BIDIR
557};
558
559struct conf_sig_weights {
560
561
562
563
564
565
566 u8 rssi_bcn_avg_weight;
567
568
569
570
571
572
573 u8 rssi_pkt_avg_weight;
574
575
576
577
578
579
580 u8 snr_bcn_avg_weight;
581
582
583
584
585
586
587 u8 snr_pkt_avg_weight;
588} __packed;
589
590enum conf_bcn_filt_mode {
591 CONF_BCN_FILT_MODE_DISABLED = 0,
592 CONF_BCN_FILT_MODE_ENABLED = 1
593};
594
595enum conf_bet_mode {
596 CONF_BET_MODE_DISABLE = 0,
597 CONF_BET_MODE_ENABLE = 1,
598};
599
600struct conf_conn_settings {
601
602
603
604
605
606
607 u8 wake_up_event;
608
609
610
611
612
613
614
615
616 u8 listen_interval;
617
618
619
620
621
622 u8 suspend_wake_up_event;
623
624
625
626
627
628
629 u8 suspend_listen_interval;
630
631
632
633
634
635
636 u8 bcn_filt_mode;
637
638
639
640
641 u8 bcn_filt_ie_count;
642 struct conf_bcn_filt_rule bcn_filt_ie[CONF_MAX_BCN_FILT_IE_COUNT];
643
644
645
646
647
648
649
650 u32 synch_fail_thold;
651
652
653
654
655
656
657
658
659 u32 bss_lose_timeout;
660
661
662
663
664
665
666 u32 beacon_rx_timeout;
667
668
669
670
671
672
673 u32 broadcast_timeout;
674
675
676
677
678
679
680 u8 rx_broadcast_in_ps;
681
682
683
684
685
686
687 u8 ps_poll_threshold;
688
689
690
691
692 struct conf_sig_weights sig_weights;
693
694
695
696
697
698
699
700 u8 bet_enable;
701
702
703
704
705
706
707
708
709
710 u8 bet_max_consecutive;
711
712
713
714
715
716
717
718 u8 psm_entry_retries;
719
720
721
722
723
724
725
726 u8 psm_exit_retries;
727
728
729
730
731
732
733
734 u8 psm_entry_nullfunc_retries;
735
736
737
738
739
740 u16 dynamic_ps_timeout;
741
742
743
744
745
746 u8 forced_ps;
747
748
749
750
751
752
753
754
755 u32 keep_alive_interval;
756
757
758
759
760
761
762 u8 max_listen_interval;
763
764
765
766
767
768 u8 sta_sleep_auth;
769
770
771
772
773 u8 suspend_rx_ba_activity;
774} __packed;
775
776enum {
777 CONF_REF_CLK_19_2_E,
778 CONF_REF_CLK_26_E,
779 CONF_REF_CLK_38_4_E,
780 CONF_REF_CLK_52_E,
781 CONF_REF_CLK_38_4_M_XTAL,
782 CONF_REF_CLK_26_M_XTAL,
783};
784
785enum single_dual_band_enum {
786 CONF_SINGLE_BAND,
787 CONF_DUAL_BAND
788};
789
790#define CONF_RSSI_AND_PROCESS_COMPENSATION_SIZE 15
791#define CONF_NUMBER_OF_SUB_BANDS_5 7
792#define CONF_NUMBER_OF_RATE_GROUPS 6
793#define CONF_NUMBER_OF_CHANNELS_2_4 14
794#define CONF_NUMBER_OF_CHANNELS_5 35
795
796struct conf_itrim_settings {
797
798 u8 enable;
799
800
801 u32 timeout;
802} __packed;
803
804enum conf_fast_wakeup {
805 CONF_FAST_WAKEUP_ENABLE,
806 CONF_FAST_WAKEUP_DISABLE,
807};
808
809struct conf_pm_config_settings {
810
811
812
813
814
815 u32 host_clk_settling_time;
816
817
818
819
820
821
822 u8 host_fast_wakeup_support;
823} __packed;
824
825struct conf_roam_trigger_settings {
826
827
828
829
830
831 u16 trigger_pacing;
832
833
834
835
836
837
838 u8 avg_weight_rssi_beacon;
839
840
841
842
843
844
845 u8 avg_weight_rssi_data;
846
847
848
849
850
851
852 u8 avg_weight_snr_beacon;
853
854
855
856
857
858
859 u8 avg_weight_snr_data;
860} __packed;
861
862struct conf_scan_settings {
863
864
865
866
867
868
869 u32 min_dwell_time_active;
870
871
872
873
874
875
876
877
878
879 u32 max_dwell_time_active;
880
881
882
883
884
885
886
887
888
889 u32 min_dwell_time_active_long;
890
891
892
893
894
895
896
897 u32 max_dwell_time_active_long;
898
899
900 u32 dwell_time_passive;
901
902
903 u32 dwell_time_dfs;
904
905
906
907
908
909
910 u16 num_probe_reqs;
911
912
913
914
915
916
917
918
919 u32 split_scan_timeout;
920} __packed;
921
922struct conf_sched_scan_settings {
923
924
925
926
927
928
929
930 u32 base_dwell_time;
931
932
933
934
935
936 u32 max_dwell_time_delta;
937
938
939 u32 dwell_time_delta_per_probe;
940
941
942 u32 dwell_time_delta_per_probe_5;
943
944
945 u32 dwell_time_passive;
946
947
948 u32 dwell_time_dfs;
949
950
951 u8 num_probe_reqs;
952
953
954 s8 rssi_threshold;
955
956
957 s8 snr_threshold;
958
959
960
961
962
963 u8 num_short_intervals;
964
965
966 u16 long_interval;
967} __packed;
968
969struct conf_ht_setting {
970 u8 rx_ba_win_size;
971 u8 tx_ba_win_size;
972 u16 inactivity_timeout;
973
974
975 u8 tx_ba_tid_bitmap;
976} __packed;
977
978struct conf_memory_settings {
979
980 u8 num_stations;
981
982
983 u8 ssid_profiles;
984
985
986 u8 rx_block_num;
987
988
989 u8 tx_min_block_num;
990
991
992 u8 dynamic_memory;
993
994
995
996
997
998
999
1000 u8 min_req_tx_blocks;
1001
1002
1003
1004
1005
1006
1007
1008 u8 min_req_rx_blocks;
1009
1010
1011
1012
1013
1014
1015 u8 tx_min;
1016} __packed;
1017
1018struct conf_fm_coex {
1019 u8 enable;
1020 u8 swallow_period;
1021 u8 n_divider_fref_set_1;
1022 u8 n_divider_fref_set_2;
1023 u16 m_divider_fref_set_1;
1024 u16 m_divider_fref_set_2;
1025 u32 coex_pll_stabilization_time;
1026 u16 ldo_stabilization_time;
1027 u8 fm_disturbed_band_margin;
1028 u8 swallow_clk_diff;
1029} __packed;
1030
1031struct conf_rx_streaming_settings {
1032
1033
1034
1035
1036
1037 u32 duration;
1038
1039
1040
1041
1042
1043
1044
1045 u8 queues;
1046
1047
1048
1049
1050
1051
1052 u8 interval;
1053
1054
1055
1056
1057 u8 always;
1058} __packed;
1059
1060#define CONF_FWLOG_MIN_MEM_BLOCKS 2
1061#define CONF_FWLOG_MAX_MEM_BLOCKS 16
1062
1063struct conf_fwlog {
1064
1065 u8 mode;
1066
1067
1068
1069
1070
1071
1072 u8 mem_blocks;
1073
1074
1075 u8 severity;
1076
1077
1078 u8 timestamp;
1079
1080
1081 u8 output;
1082
1083
1084 u8 threshold;
1085} __packed;
1086
1087#define ACX_RATE_MGMT_NUM_OF_RATES 13
1088struct conf_rate_policy_settings {
1089 u16 rate_retry_score;
1090 u16 per_add;
1091 u16 per_th1;
1092 u16 per_th2;
1093 u16 max_per;
1094 u8 inverse_curiosity_factor;
1095 u8 tx_fail_low_th;
1096 u8 tx_fail_high_th;
1097 u8 per_alpha_shift;
1098 u8 per_add_shift;
1099 u8 per_beta1_shift;
1100 u8 per_beta2_shift;
1101 u8 rate_check_up;
1102 u8 rate_check_down;
1103 u8 rate_retry_policy[ACX_RATE_MGMT_NUM_OF_RATES];
1104} __packed;
1105
1106struct conf_hangover_settings {
1107 u32 recover_time;
1108 u8 hangover_period;
1109 u8 dynamic_mode;
1110 u8 early_termination_mode;
1111 u8 max_period;
1112 u8 min_period;
1113 u8 increase_delta;
1114 u8 decrease_delta;
1115 u8 quiet_time;
1116 u8 increase_time;
1117 u8 window_size;
1118} __packed;
1119
1120struct conf_recovery_settings {
1121
1122 u8 bug_on_recovery;
1123
1124
1125 u8 no_recovery;
1126} __packed;
1127
1128
1129
1130
1131
1132
1133#define WLCORE_CONF_VERSION (0x0007 << 16)
1134#define WLCORE_CONF_MASK 0xffff0000
1135#define WLCORE_CONF_SIZE (sizeof(struct wlcore_conf_header) + \
1136 sizeof(struct wlcore_conf))
1137
1138struct wlcore_conf_header {
1139 __le32 magic;
1140 __le32 version;
1141 __le32 checksum;
1142} __packed;
1143
1144struct wlcore_conf {
1145 struct conf_sg_settings sg;
1146 struct conf_rx_settings rx;
1147 struct conf_tx_settings tx;
1148 struct conf_conn_settings conn;
1149 struct conf_itrim_settings itrim;
1150 struct conf_pm_config_settings pm_config;
1151 struct conf_roam_trigger_settings roam_trigger;
1152 struct conf_scan_settings scan;
1153 struct conf_sched_scan_settings sched_scan;
1154 struct conf_ht_setting ht;
1155 struct conf_memory_settings mem;
1156 struct conf_fm_coex fm_coex;
1157 struct conf_rx_streaming_settings rx_streaming;
1158 struct conf_fwlog fwlog;
1159 struct conf_rate_policy_settings rate;
1160 struct conf_hangover_settings hangover;
1161 struct conf_recovery_settings recovery;
1162} __packed;
1163
1164struct wlcore_conf_file {
1165 struct wlcore_conf_header header;
1166 struct wlcore_conf core;
1167 u8 priv[0];
1168} __packed;
1169
1170#endif
1171