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15#include <linux/clk.h>
16#include <linux/interrupt.h>
17#include <linux/kernel.h>
18#include <linux/init.h>
19#include <linux/of.h>
20#include <linux/pci.h>
21#include <linux/phy/phy.h>
22#include <linux/platform_device.h>
23#include <linux/resource.h>
24
25#include "pcie-designware.h"
26
27struct spear13xx_pcie {
28 struct dw_pcie *pci;
29 void __iomem *app_base;
30 struct phy *phy;
31 struct clk *clk;
32 bool is_gen1;
33};
34
35struct pcie_app_reg {
36 u32 app_ctrl_0;
37 u32 app_ctrl_1;
38 u32 app_status_0;
39 u32 app_status_1;
40 u32 msg_status;
41 u32 msg_payload;
42 u32 int_sts;
43 u32 int_clr;
44 u32 int_mask;
45 u32 mst_bmisc;
46 u32 phy_ctrl;
47 u32 phy_status;
48 u32 cxpl_debug_info_0;
49 u32 cxpl_debug_info_1;
50 u32 ven_msg_ctrl_0;
51 u32 ven_msg_ctrl_1;
52 u32 ven_msg_data_0;
53 u32 ven_msg_data_1;
54 u32 ven_msi_0;
55 u32 ven_msi_1;
56 u32 mst_rmisc;
57};
58
59
60#define APP_LTSSM_ENABLE_ID 3
61#define DEVICE_TYPE_RC (4 << 25)
62#define MISCTRL_EN_ID 30
63#define REG_TRANSLATION_ENABLE 31
64
65
66#define XMLH_LINK_UP (1 << 6)
67
68
69#define MSI_CTRL_INT (1 << 26)
70
71#define EXP_CAP_ID_OFFSET 0x70
72
73#define to_spear13xx_pcie(x) dev_get_drvdata((x)->dev)
74
75static int spear13xx_pcie_establish_link(struct spear13xx_pcie *spear13xx_pcie)
76{
77 struct dw_pcie *pci = spear13xx_pcie->pci;
78 struct pcie_port *pp = &pci->pp;
79 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
80 u32 val;
81 u32 exp_cap_off = EXP_CAP_ID_OFFSET;
82
83 if (dw_pcie_link_up(pci)) {
84 dev_err(pci->dev, "link already up\n");
85 return 0;
86 }
87
88 dw_pcie_setup_rc(pp);
89
90
91
92
93
94
95 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, &val);
96 val &= ~PCI_EXP_DEVCTL_READRQ;
97 dw_pcie_write(pci->dbi_base + exp_cap_off + PCI_EXP_DEVCTL, 2, val);
98
99 dw_pcie_write(pci->dbi_base + PCI_VENDOR_ID, 2, 0x104A);
100 dw_pcie_write(pci->dbi_base + PCI_DEVICE_ID, 2, 0xCD80);
101
102
103
104
105
106 if (spear13xx_pcie->is_gen1) {
107 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCAP,
108 4, &val);
109 if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
110 val &= ~((u32)PCI_EXP_LNKCAP_SLS);
111 val |= PCI_EXP_LNKCAP_SLS_2_5GB;
112 dw_pcie_write(pci->dbi_base + exp_cap_off +
113 PCI_EXP_LNKCAP, 4, val);
114 }
115
116 dw_pcie_read(pci->dbi_base + exp_cap_off + PCI_EXP_LNKCTL2,
117 2, &val);
118 if ((val & PCI_EXP_LNKCAP_SLS) != PCI_EXP_LNKCAP_SLS_2_5GB) {
119 val &= ~((u32)PCI_EXP_LNKCAP_SLS);
120 val |= PCI_EXP_LNKCAP_SLS_2_5GB;
121 dw_pcie_write(pci->dbi_base + exp_cap_off +
122 PCI_EXP_LNKCTL2, 2, val);
123 }
124 }
125
126
127 writel(DEVICE_TYPE_RC | (1 << MISCTRL_EN_ID)
128 | (1 << APP_LTSSM_ENABLE_ID)
129 | ((u32)1 << REG_TRANSLATION_ENABLE),
130 &app_reg->app_ctrl_0);
131
132 return dw_pcie_wait_for_link(pci);
133}
134
135static irqreturn_t spear13xx_pcie_irq_handler(int irq, void *arg)
136{
137 struct spear13xx_pcie *spear13xx_pcie = arg;
138 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
139 struct dw_pcie *pci = spear13xx_pcie->pci;
140 struct pcie_port *pp = &pci->pp;
141 unsigned int status;
142
143 status = readl(&app_reg->int_sts);
144
145 if (status & MSI_CTRL_INT) {
146 BUG_ON(!IS_ENABLED(CONFIG_PCI_MSI));
147 dw_handle_msi_irq(pp);
148 }
149
150 writel(status, &app_reg->int_clr);
151
152 return IRQ_HANDLED;
153}
154
155static void spear13xx_pcie_enable_interrupts(struct spear13xx_pcie *spear13xx_pcie)
156{
157 struct dw_pcie *pci = spear13xx_pcie->pci;
158 struct pcie_port *pp = &pci->pp;
159 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
160
161
162 if (IS_ENABLED(CONFIG_PCI_MSI)) {
163 dw_pcie_msi_init(pp);
164 writel(readl(&app_reg->int_mask) |
165 MSI_CTRL_INT, &app_reg->int_mask);
166 }
167}
168
169static int spear13xx_pcie_link_up(struct dw_pcie *pci)
170{
171 struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci);
172 struct pcie_app_reg *app_reg = spear13xx_pcie->app_base;
173
174 if (readl(&app_reg->app_status_1) & XMLH_LINK_UP)
175 return 1;
176
177 return 0;
178}
179
180static void spear13xx_pcie_host_init(struct pcie_port *pp)
181{
182 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
183 struct spear13xx_pcie *spear13xx_pcie = to_spear13xx_pcie(pci);
184
185 spear13xx_pcie_establish_link(spear13xx_pcie);
186 spear13xx_pcie_enable_interrupts(spear13xx_pcie);
187}
188
189static const struct dw_pcie_host_ops spear13xx_pcie_host_ops = {
190 .host_init = spear13xx_pcie_host_init,
191};
192
193static int spear13xx_add_pcie_port(struct spear13xx_pcie *spear13xx_pcie,
194 struct platform_device *pdev)
195{
196 struct dw_pcie *pci = spear13xx_pcie->pci;
197 struct pcie_port *pp = &pci->pp;
198 struct device *dev = &pdev->dev;
199 int ret;
200
201 pp->irq = platform_get_irq(pdev, 0);
202 if (!pp->irq) {
203 dev_err(dev, "failed to get irq\n");
204 return -ENODEV;
205 }
206 ret = devm_request_irq(dev, pp->irq, spear13xx_pcie_irq_handler,
207 IRQF_SHARED | IRQF_NO_THREAD,
208 "spear1340-pcie", spear13xx_pcie);
209 if (ret) {
210 dev_err(dev, "failed to request irq %d\n", pp->irq);
211 return ret;
212 }
213
214 pp->root_bus_nr = -1;
215 pp->ops = &spear13xx_pcie_host_ops;
216
217 ret = dw_pcie_host_init(pp);
218 if (ret) {
219 dev_err(dev, "failed to initialize host\n");
220 return ret;
221 }
222
223 return 0;
224}
225
226static const struct dw_pcie_ops dw_pcie_ops = {
227 .link_up = spear13xx_pcie_link_up,
228};
229
230static int spear13xx_pcie_probe(struct platform_device *pdev)
231{
232 struct device *dev = &pdev->dev;
233 struct dw_pcie *pci;
234 struct spear13xx_pcie *spear13xx_pcie;
235 struct device_node *np = dev->of_node;
236 struct resource *dbi_base;
237 int ret;
238
239 spear13xx_pcie = devm_kzalloc(dev, sizeof(*spear13xx_pcie), GFP_KERNEL);
240 if (!spear13xx_pcie)
241 return -ENOMEM;
242
243 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
244 if (!pci)
245 return -ENOMEM;
246
247 pci->dev = dev;
248 pci->ops = &dw_pcie_ops;
249
250 spear13xx_pcie->pci = pci;
251
252 spear13xx_pcie->phy = devm_phy_get(dev, "pcie-phy");
253 if (IS_ERR(spear13xx_pcie->phy)) {
254 ret = PTR_ERR(spear13xx_pcie->phy);
255 if (ret == -EPROBE_DEFER)
256 dev_info(dev, "probe deferred\n");
257 else
258 dev_err(dev, "couldn't get pcie-phy\n");
259 return ret;
260 }
261
262 phy_init(spear13xx_pcie->phy);
263
264 spear13xx_pcie->clk = devm_clk_get(dev, NULL);
265 if (IS_ERR(spear13xx_pcie->clk)) {
266 dev_err(dev, "couldn't get clk for pcie\n");
267 return PTR_ERR(spear13xx_pcie->clk);
268 }
269 ret = clk_prepare_enable(spear13xx_pcie->clk);
270 if (ret) {
271 dev_err(dev, "couldn't enable clk for pcie\n");
272 return ret;
273 }
274
275 dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
276 pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
277 if (IS_ERR(pci->dbi_base)) {
278 dev_err(dev, "couldn't remap dbi base %p\n", dbi_base);
279 ret = PTR_ERR(pci->dbi_base);
280 goto fail_clk;
281 }
282 spear13xx_pcie->app_base = pci->dbi_base + 0x2000;
283
284 if (of_property_read_bool(np, "st,pcie-is-gen1"))
285 spear13xx_pcie->is_gen1 = true;
286
287 platform_set_drvdata(pdev, spear13xx_pcie);
288
289 ret = spear13xx_add_pcie_port(spear13xx_pcie, pdev);
290 if (ret < 0)
291 goto fail_clk;
292
293 return 0;
294
295fail_clk:
296 clk_disable_unprepare(spear13xx_pcie->clk);
297
298 return ret;
299}
300
301static const struct of_device_id spear13xx_pcie_of_match[] = {
302 { .compatible = "st,spear1340-pcie", },
303 {},
304};
305
306static struct platform_driver spear13xx_pcie_driver = {
307 .probe = spear13xx_pcie_probe,
308 .driver = {
309 .name = "spear-pcie",
310 .of_match_table = of_match_ptr(spear13xx_pcie_of_match),
311 .suppress_bind_attrs = true,
312 },
313};
314
315builtin_platform_driver(spear13xx_pcie_driver);
316
