1
2
3
4
5
6
7
8
9
10
11
12
13
14#include <linux/delay.h>
15#include <linux/io.h>
16#include <linux/module.h>
17#include <linux/of_device.h>
18#include <linux/regmap.h>
19#include <linux/phy/phy.h>
20#include <linux/platform_device.h>
21#include <linux/usb/of.h>
22
23
24#define U2P_R0 0x0
25 #define U2P_R0_BYPASS_SEL BIT(0)
26 #define U2P_R0_BYPASS_DM_EN BIT(1)
27 #define U2P_R0_BYPASS_DP_EN BIT(2)
28 #define U2P_R0_TXBITSTUFF_ENH BIT(3)
29 #define U2P_R0_TXBITSTUFF_EN BIT(4)
30 #define U2P_R0_DM_PULLDOWN BIT(5)
31 #define U2P_R0_DP_PULLDOWN BIT(6)
32 #define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7)
33 #define U2P_R0_DP_VBUS_VLD_EXT BIT(8)
34 #define U2P_R0_ADP_PRB_EN BIT(9)
35 #define U2P_R0_ADP_DISCHARGE BIT(10)
36 #define U2P_R0_ADP_CHARGE BIT(11)
37 #define U2P_R0_DRV_VBUS BIT(12)
38 #define U2P_R0_ID_PULLUP BIT(13)
39 #define U2P_R0_LOOPBACK_EN_B BIT(14)
40 #define U2P_R0_OTG_DISABLE BIT(15)
41 #define U2P_R0_COMMON_ONN BIT(16)
42 #define U2P_R0_FSEL_MASK GENMASK(19, 17)
43 #define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20)
44 #define U2P_R0_POWER_ON_RESET BIT(22)
45 #define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23)
46 #define U2P_R0_ID_SET_ID_DQ BIT(25)
47 #define U2P_R0_ATE_RESET BIT(26)
48 #define U2P_R0_FSV_MINUS BIT(27)
49 #define U2P_R0_FSV_PLUS BIT(28)
50 #define U2P_R0_BYPASS_DM_DATA BIT(29)
51 #define U2P_R0_BYPASS_DP_DATA BIT(30)
52
53#define U2P_R1 0x4
54 #define U2P_R1_BURN_IN_TEST BIT(0)
55 #define U2P_R1_ACA_ENABLE BIT(1)
56 #define U2P_R1_DCD_ENABLE BIT(2)
57 #define U2P_R1_VDAT_SRC_EN_B BIT(3)
58 #define U2P_R1_VDAT_DET_EN_B BIT(4)
59 #define U2P_R1_CHARGES_SEL BIT(5)
60 #define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6)
61 #define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7)
62 #define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9)
63 #define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11)
64 #define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13)
65 #define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17)
66 #define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21)
67 #define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23)
68 #define U2P_R1_SQRX_TUNE_MASK GENMASK(28, 26)
69 #define U2P_R1_COMP_DIS_TUNE_MASK GENMASK(31, 29)
70
71
72#define U2P_R2 0x8
73 #define U2P_R2_DATA_IN_MASK GENMASK(3, 0)
74 #define U2P_R2_DATA_IN_EN_MASK GENMASK(7, 4)
75 #define U2P_R2_ADDR_MASK GENMASK(11, 8)
76 #define U2P_R2_DATA_OUT_SEL BIT(12)
77 #define U2P_R2_CLK BIT(13)
78 #define U2P_R2_DATA_OUT_MASK GENMASK(17, 14)
79 #define U2P_R2_ACA_PIN_RANGE_C BIT(18)
80 #define U2P_R2_ACA_PIN_RANGE_B BIT(19)
81 #define U2P_R2_ACA_PIN_RANGE_A BIT(20)
82 #define U2P_R2_ACA_PIN_GND BIT(21)
83 #define U2P_R2_ACA_PIN_FLOAT BIT(22)
84 #define U2P_R2_CHARGE_DETECT BIT(23)
85 #define U2P_R2_DEVICE_SESSION_VALID BIT(24)
86 #define U2P_R2_ADP_PROBE BIT(25)
87 #define U2P_R2_ADP_SENSE BIT(26)
88 #define U2P_R2_SESSION_END BIT(27)
89 #define U2P_R2_VBUS_VALID BIT(28)
90 #define U2P_R2_B_VALID BIT(29)
91 #define U2P_R2_A_VALID BIT(30)
92 #define U2P_R2_ID_DIG BIT(31)
93
94#define U2P_R3 0xc
95
96#define RESET_COMPLETE_TIME 500
97
98struct phy_meson_gxl_usb2_priv {
99 struct regmap *regmap;
100 enum phy_mode mode;
101 int is_enabled;
102};
103
104static const struct regmap_config phy_meson_gxl_usb2_regmap_conf = {
105 .reg_bits = 8,
106 .val_bits = 32,
107 .reg_stride = 4,
108 .max_register = U2P_R3,
109};
110
111static int phy_meson_gxl_usb2_reset(struct phy *phy)
112{
113 struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy);
114
115 if (priv->is_enabled) {
116
117 regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_POWER_ON_RESET,
118 U2P_R0_POWER_ON_RESET);
119 udelay(RESET_COMPLETE_TIME);
120 regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_POWER_ON_RESET,
121 0);
122 udelay(RESET_COMPLETE_TIME);
123 }
124
125 return 0;
126}
127
128static int phy_meson_gxl_usb2_set_mode(struct phy *phy, enum phy_mode mode)
129{
130 struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy);
131
132 switch (mode) {
133 case PHY_MODE_USB_HOST:
134 case PHY_MODE_USB_OTG:
135 regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_DM_PULLDOWN,
136 U2P_R0_DM_PULLDOWN);
137 regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_DP_PULLDOWN,
138 U2P_R0_DP_PULLDOWN);
139 regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_ID_PULLUP, 0);
140 break;
141
142 case PHY_MODE_USB_DEVICE:
143 regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_DM_PULLDOWN,
144 0);
145 regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_DP_PULLDOWN,
146 0);
147 regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_ID_PULLUP,
148 U2P_R0_ID_PULLUP);
149 break;
150
151 default:
152 return -EINVAL;
153 }
154
155 phy_meson_gxl_usb2_reset(phy);
156
157 priv->mode = mode;
158
159 return 0;
160}
161
162static int phy_meson_gxl_usb2_power_off(struct phy *phy)
163{
164 struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy);
165
166 priv->is_enabled = 0;
167
168
169 regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_POWER_ON_RESET,
170 U2P_R0_POWER_ON_RESET);
171
172 return 0;
173}
174
175static int phy_meson_gxl_usb2_power_on(struct phy *phy)
176{
177 struct phy_meson_gxl_usb2_priv *priv = phy_get_drvdata(phy);
178 int ret;
179
180 priv->is_enabled = 1;
181
182
183 regmap_update_bits(priv->regmap, U2P_R0, U2P_R0_POWER_ON_RESET, 0);
184
185 ret = phy_meson_gxl_usb2_set_mode(phy, priv->mode);
186 if (ret) {
187 phy_meson_gxl_usb2_power_off(phy);
188
189 dev_err(&phy->dev, "Failed to initialize PHY with mode %d\n",
190 priv->mode);
191 return ret;
192 }
193
194 return 0;
195}
196
197static const struct phy_ops phy_meson_gxl_usb2_ops = {
198 .power_on = phy_meson_gxl_usb2_power_on,
199 .power_off = phy_meson_gxl_usb2_power_off,
200 .set_mode = phy_meson_gxl_usb2_set_mode,
201 .reset = phy_meson_gxl_usb2_reset,
202 .owner = THIS_MODULE,
203};
204
205static int phy_meson_gxl_usb2_probe(struct platform_device *pdev)
206{
207 struct device *dev = &pdev->dev;
208 struct phy_provider *phy_provider;
209 struct resource *res;
210 struct phy_meson_gxl_usb2_priv *priv;
211 struct phy *phy;
212 void __iomem *base;
213
214 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
215 if (!priv)
216 return -ENOMEM;
217
218 platform_set_drvdata(pdev, priv);
219
220 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
221 base = devm_ioremap_resource(dev, res);
222 if (IS_ERR(base))
223 return PTR_ERR(base);
224
225 switch (of_usb_get_dr_mode_by_phy(dev->of_node, -1)) {
226 case USB_DR_MODE_PERIPHERAL:
227 priv->mode = PHY_MODE_USB_DEVICE;
228 break;
229 case USB_DR_MODE_OTG:
230 priv->mode = PHY_MODE_USB_OTG;
231 break;
232 case USB_DR_MODE_HOST:
233 default:
234 priv->mode = PHY_MODE_USB_HOST;
235 break;
236 }
237
238 priv->regmap = devm_regmap_init_mmio(dev, base,
239 &phy_meson_gxl_usb2_regmap_conf);
240 if (IS_ERR(priv->regmap))
241 return PTR_ERR(priv->regmap);
242
243 phy = devm_phy_create(dev, NULL, &phy_meson_gxl_usb2_ops);
244 if (IS_ERR(phy)) {
245 dev_err(dev, "failed to create PHY\n");
246 return PTR_ERR(phy);
247 }
248
249 phy_set_drvdata(phy, priv);
250
251 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
252
253 return PTR_ERR_OR_ZERO(phy_provider);
254}
255
256static const struct of_device_id phy_meson_gxl_usb2_of_match[] = {
257 { .compatible = "amlogic,meson-gxl-usb2-phy", },
258 { },
259};
260MODULE_DEVICE_TABLE(of, phy_meson_gxl_usb2_of_match);
261
262static struct platform_driver phy_meson_gxl_usb2_driver = {
263 .probe = phy_meson_gxl_usb2_probe,
264 .driver = {
265 .name = "phy-meson-gxl-usb2",
266 .of_match_table = phy_meson_gxl_usb2_of_match,
267 },
268};
269module_platform_driver(phy_meson_gxl_usb2_driver);
270
271MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
272MODULE_DESCRIPTION("Meson GXL and GXM USB2 PHY driver");
273MODULE_LICENSE("GPL v2");
274
