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17#include <linux/delay.h>
18#include <linux/device.h>
19#include <linux/init.h>
20#include <linux/interrupt.h>
21#include <linux/io.h>
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/of.h>
25#include <linux/phy/phy.h>
26#include <linux/platform_device.h>
27
28#define SATA_PCB_BANK_OFFSET 0x23c
29#define SATA_PCB_REG_OFFSET(ofs) ((ofs) * 4)
30
31#define MAX_PORTS 2
32
33
34#define SATA_PCB_REG_28NM_SPACE_SIZE 0x1000
35
36
37
38
39#define SATA_PCB_REG_40NM_SPACE_SIZE 0x10
40
41
42#define SATA_PHY_CTRL_REG_28NM_SPACE_SIZE 0x8
43
44enum brcm_sata_phy_version {
45 BRCM_SATA_PHY_STB_28NM,
46 BRCM_SATA_PHY_STB_40NM,
47 BRCM_SATA_PHY_IPROC_NS2,
48 BRCM_SATA_PHY_IPROC_NSP,
49 BRCM_SATA_PHY_IPROC_SR,
50};
51
52struct brcm_sata_port {
53 int portnum;
54 struct phy *phy;
55 struct brcm_sata_phy *phy_priv;
56 bool ssc_en;
57};
58
59struct brcm_sata_phy {
60 struct device *dev;
61 void __iomem *phy_base;
62 void __iomem *ctrl_base;
63 enum brcm_sata_phy_version version;
64
65 struct brcm_sata_port phys[MAX_PORTS];
66};
67
68enum sata_phy_regs {
69 BLOCK0_REG_BANK = 0x000,
70 BLOCK0_XGXSSTATUS = 0x81,
71 BLOCK0_XGXSSTATUS_PLL_LOCK = BIT(12),
72 BLOCK0_SPARE = 0x8d,
73 BLOCK0_SPARE_OOB_CLK_SEL_MASK = 0x3,
74 BLOCK0_SPARE_OOB_CLK_SEL_REFBY2 = 0x1,
75
76 PLL_REG_BANK_0 = 0x050,
77 PLL_REG_BANK_0_PLLCONTROL_0 = 0x81,
78 PLLCONTROL_0_FREQ_DET_RESTART = BIT(13),
79 PLLCONTROL_0_FREQ_MONITOR = BIT(12),
80 PLLCONTROL_0_SEQ_START = BIT(15),
81 PLL_CAP_CONTROL = 0x85,
82 PLL_ACTRL2 = 0x8b,
83 PLL_ACTRL2_SELDIV_MASK = 0x1f,
84 PLL_ACTRL2_SELDIV_SHIFT = 9,
85 PLL_ACTRL6 = 0x86,
86
87 PLL1_REG_BANK = 0x060,
88 PLL1_ACTRL2 = 0x82,
89 PLL1_ACTRL3 = 0x83,
90 PLL1_ACTRL4 = 0x84,
91
92 TX_REG_BANK = 0x070,
93 TX_ACTRL0 = 0x80,
94 TX_ACTRL0_TXPOL_FLIP = BIT(6),
95
96 OOB_REG_BANK = 0x150,
97 OOB1_REG_BANK = 0x160,
98 OOB_CTRL1 = 0x80,
99 OOB_CTRL1_BURST_MAX_MASK = 0xf,
100 OOB_CTRL1_BURST_MAX_SHIFT = 12,
101 OOB_CTRL1_BURST_MIN_MASK = 0xf,
102 OOB_CTRL1_BURST_MIN_SHIFT = 8,
103 OOB_CTRL1_WAKE_IDLE_MAX_MASK = 0xf,
104 OOB_CTRL1_WAKE_IDLE_MAX_SHIFT = 4,
105 OOB_CTRL1_WAKE_IDLE_MIN_MASK = 0xf,
106 OOB_CTRL1_WAKE_IDLE_MIN_SHIFT = 0,
107 OOB_CTRL2 = 0x81,
108 OOB_CTRL2_SEL_ENA_SHIFT = 15,
109 OOB_CTRL2_SEL_ENA_RC_SHIFT = 14,
110 OOB_CTRL2_RESET_IDLE_MAX_MASK = 0x3f,
111 OOB_CTRL2_RESET_IDLE_MAX_SHIFT = 8,
112 OOB_CTRL2_BURST_CNT_MASK = 0x3,
113 OOB_CTRL2_BURST_CNT_SHIFT = 6,
114 OOB_CTRL2_RESET_IDLE_MIN_MASK = 0x3f,
115 OOB_CTRL2_RESET_IDLE_MIN_SHIFT = 0,
116
117 TXPMD_REG_BANK = 0x1a0,
118 TXPMD_CONTROL1 = 0x81,
119 TXPMD_CONTROL1_TX_SSC_EN_FRC = BIT(0),
120 TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL = BIT(1),
121 TXPMD_TX_FREQ_CTRL_CONTROL1 = 0x82,
122 TXPMD_TX_FREQ_CTRL_CONTROL2 = 0x83,
123 TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK = 0x3ff,
124 TXPMD_TX_FREQ_CTRL_CONTROL3 = 0x84,
125 TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK = 0x3ff,
126};
127
128enum sata_phy_ctrl_regs {
129 PHY_CTRL_1 = 0x0,
130 PHY_CTRL_1_RESET = BIT(0),
131};
132
133static inline void __iomem *brcm_sata_pcb_base(struct brcm_sata_port *port)
134{
135 struct brcm_sata_phy *priv = port->phy_priv;
136 u32 size = 0;
137
138 switch (priv->version) {
139 case BRCM_SATA_PHY_STB_28NM:
140 case BRCM_SATA_PHY_IPROC_NS2:
141 size = SATA_PCB_REG_28NM_SPACE_SIZE;
142 break;
143 case BRCM_SATA_PHY_STB_40NM:
144 size = SATA_PCB_REG_40NM_SPACE_SIZE;
145 break;
146 default:
147 dev_err(priv->dev, "invalid phy version\n");
148 break;
149 }
150
151 return priv->phy_base + (port->portnum * size);
152}
153
154static inline void __iomem *brcm_sata_ctrl_base(struct brcm_sata_port *port)
155{
156 struct brcm_sata_phy *priv = port->phy_priv;
157 u32 size = 0;
158
159 switch (priv->version) {
160 case BRCM_SATA_PHY_IPROC_NS2:
161 size = SATA_PHY_CTRL_REG_28NM_SPACE_SIZE;
162 break;
163 default:
164 dev_err(priv->dev, "invalid phy version\n");
165 break;
166 }
167
168 return priv->ctrl_base + (port->portnum * size);
169}
170
171static void brcm_sata_phy_wr(void __iomem *pcb_base, u32 bank,
172 u32 ofs, u32 msk, u32 value)
173{
174 u32 tmp;
175
176 writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);
177 tmp = readl(pcb_base + SATA_PCB_REG_OFFSET(ofs));
178 tmp = (tmp & msk) | value;
179 writel(tmp, pcb_base + SATA_PCB_REG_OFFSET(ofs));
180}
181
182static u32 brcm_sata_phy_rd(void __iomem *pcb_base, u32 bank, u32 ofs)
183{
184 writel(bank, pcb_base + SATA_PCB_BANK_OFFSET);
185 return readl(pcb_base + SATA_PCB_REG_OFFSET(ofs));
186}
187
188
189#define STB_FMIN_VAL_DEFAULT 0x3df
190#define STB_FMAX_VAL_DEFAULT 0x3df
191#define STB_FMAX_VAL_SSC 0x83
192
193static int brcm_stb_sata_init(struct brcm_sata_port *port)
194{
195 void __iomem *base = brcm_sata_pcb_base(port);
196 struct brcm_sata_phy *priv = port->phy_priv;
197 u32 tmp;
198
199
200 tmp = TXPMD_CONTROL1_TX_SSC_EN_FRC_VAL | TXPMD_CONTROL1_TX_SSC_EN_FRC;
201 brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_CONTROL1, ~tmp, tmp);
202
203
204 brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL2,
205 ~TXPMD_TX_FREQ_CTRL_CONTROL2_FMIN_MASK,
206 STB_FMIN_VAL_DEFAULT);
207
208
209 if (port->ssc_en) {
210 dev_info(priv->dev, "enabling SSC on port%d\n", port->portnum);
211 tmp = STB_FMAX_VAL_SSC;
212 } else {
213 tmp = STB_FMAX_VAL_DEFAULT;
214 }
215
216 brcm_sata_phy_wr(base, TXPMD_REG_BANK, TXPMD_TX_FREQ_CTRL_CONTROL3,
217 ~TXPMD_TX_FREQ_CTRL_CONTROL3_FMAX_MASK, tmp);
218
219 return 0;
220}
221
222
223#define NS2_PLL1_ACTRL2_MAGIC 0x1df8
224#define NS2_PLL1_ACTRL3_MAGIC 0x2b00
225#define NS2_PLL1_ACTRL4_MAGIC 0x8824
226
227static int brcm_ns2_sata_init(struct brcm_sata_port *port)
228{
229 int try;
230 unsigned int val;
231 void __iomem *base = brcm_sata_pcb_base(port);
232 void __iomem *ctrl_base = brcm_sata_ctrl_base(port);
233 struct device *dev = port->phy_priv->dev;
234
235
236 val = 0x0;
237 val |= (0xc << OOB_CTRL1_BURST_MAX_SHIFT);
238 val |= (0x4 << OOB_CTRL1_BURST_MIN_SHIFT);
239 val |= (0x9 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
240 val |= (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
241 brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
242 val = 0x0;
243 val |= (0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
244 val |= (0x2 << OOB_CTRL2_BURST_CNT_SHIFT);
245 val |= (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
246 brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
247
248
249 val = NS2_PLL1_ACTRL2_MAGIC;
250 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
251 val = NS2_PLL1_ACTRL3_MAGIC;
252 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
253 val = NS2_PLL1_ACTRL4_MAGIC;
254 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
255
256
257
258 brcm_sata_phy_wr(base, BLOCK0_REG_BANK, BLOCK0_SPARE,
259 ~BLOCK0_SPARE_OOB_CLK_SEL_MASK,
260 BLOCK0_SPARE_OOB_CLK_SEL_REFBY2);
261
262
263 writel(PHY_CTRL_1_RESET, ctrl_base + PHY_CTRL_1);
264 mdelay(1);
265 writel(0x0, ctrl_base + PHY_CTRL_1);
266 mdelay(1);
267
268
269 try = 50;
270 while (try) {
271 val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
272 BLOCK0_XGXSSTATUS);
273 if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
274 break;
275 msleep(20);
276 try--;
277 }
278 if (!try) {
279
280 dev_err(dev, "port%d PLL did not lock\n", port->portnum);
281 return -ETIMEDOUT;
282 }
283
284 dev_dbg(dev, "port%d initialized\n", port->portnum);
285
286 return 0;
287}
288
289static int brcm_nsp_sata_init(struct brcm_sata_port *port)
290{
291 struct brcm_sata_phy *priv = port->phy_priv;
292 struct device *dev = port->phy_priv->dev;
293 void __iomem *base = priv->phy_base;
294 unsigned int oob_bank;
295 unsigned int val, try;
296
297
298 if (port->portnum == 0)
299 oob_bank = OOB_REG_BANK;
300 else if (port->portnum == 1)
301 oob_bank = OOB1_REG_BANK;
302 else
303 return -EINVAL;
304
305 val = 0x0;
306 val |= (0x0f << OOB_CTRL1_BURST_MAX_SHIFT);
307 val |= (0x06 << OOB_CTRL1_BURST_MIN_SHIFT);
308 val |= (0x0f << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT);
309 val |= (0x06 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT);
310 brcm_sata_phy_wr(base, oob_bank, OOB_CTRL1, 0x0, val);
311
312 val = 0x0;
313 val |= (0x2e << OOB_CTRL2_RESET_IDLE_MAX_SHIFT);
314 val |= (0x02 << OOB_CTRL2_BURST_CNT_SHIFT);
315 val |= (0x16 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT);
316 brcm_sata_phy_wr(base, oob_bank, OOB_CTRL2, 0x0, val);
317
318
319 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_ACTRL2,
320 ~(PLL_ACTRL2_SELDIV_MASK << PLL_ACTRL2_SELDIV_SHIFT),
321 0x0c << PLL_ACTRL2_SELDIV_SHIFT);
322
323 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_CAP_CONTROL,
324 0xff0, 0x4f0);
325
326 val = PLLCONTROL_0_FREQ_DET_RESTART | PLLCONTROL_0_FREQ_MONITOR;
327 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
328 ~val, val);
329 val = PLLCONTROL_0_SEQ_START;
330 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
331 ~val, 0);
332 mdelay(10);
333 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_REG_BANK_0_PLLCONTROL_0,
334 ~val, val);
335
336
337 try = 50;
338 while (try--) {
339 val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
340 BLOCK0_XGXSSTATUS);
341 if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
342 break;
343 msleep(20);
344 }
345 if (!try) {
346
347 dev_err(dev, "port%d PLL did not lock\n", port->portnum);
348 return -ETIMEDOUT;
349 }
350
351 dev_dbg(dev, "port%d initialized\n", port->portnum);
352
353 return 0;
354}
355
356
357#define SR_PLL0_ACTRL6_MAGIC 0xa
358
359
360#define SR_PLL1_ACTRL2_MAGIC 0x32
361#define SR_PLL1_ACTRL3_MAGIC 0x2
362#define SR_PLL1_ACTRL4_MAGIC 0x3e8
363
364static int brcm_sr_sata_init(struct brcm_sata_port *port)
365{
366 struct brcm_sata_phy *priv = port->phy_priv;
367 struct device *dev = port->phy_priv->dev;
368 void __iomem *base = priv->phy_base;
369 unsigned int val, try;
370
371
372 val = SR_PLL1_ACTRL2_MAGIC;
373 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL2, 0x0, val);
374 val = SR_PLL1_ACTRL3_MAGIC;
375 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL3, 0x0, val);
376 val = SR_PLL1_ACTRL4_MAGIC;
377 brcm_sata_phy_wr(base, PLL1_REG_BANK, PLL1_ACTRL4, 0x0, val);
378
379
380 val = SR_PLL0_ACTRL6_MAGIC;
381 brcm_sata_phy_wr(base, PLL_REG_BANK_0, PLL_ACTRL6, 0x0, val);
382
383
384 try = 50;
385 do {
386 val = brcm_sata_phy_rd(base, BLOCK0_REG_BANK,
387 BLOCK0_XGXSSTATUS);
388 if (val & BLOCK0_XGXSSTATUS_PLL_LOCK)
389 break;
390 msleep(20);
391 try--;
392 } while (try);
393
394 if ((val & BLOCK0_XGXSSTATUS_PLL_LOCK) == 0) {
395
396 dev_err(dev, "port%d PLL did not lock\n", port->portnum);
397 return -ETIMEDOUT;
398 }
399
400
401 brcm_sata_phy_wr(base, TX_REG_BANK, TX_ACTRL0,
402 ~TX_ACTRL0_TXPOL_FLIP, TX_ACTRL0_TXPOL_FLIP);
403
404
405 val = ((0xc << OOB_CTRL1_BURST_MAX_SHIFT) |
406 (0x4 << OOB_CTRL1_BURST_MIN_SHIFT) |
407 (0x8 << OOB_CTRL1_WAKE_IDLE_MAX_SHIFT) |
408 (0x3 << OOB_CTRL1_WAKE_IDLE_MIN_SHIFT));
409 brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL1, 0x0, val);
410 val = ((0x1b << OOB_CTRL2_RESET_IDLE_MAX_SHIFT) |
411 (0x2 << OOB_CTRL2_BURST_CNT_SHIFT) |
412 (0x9 << OOB_CTRL2_RESET_IDLE_MIN_SHIFT));
413 brcm_sata_phy_wr(base, OOB_REG_BANK, OOB_CTRL2, 0x0, val);
414
415 return 0;
416}
417
418static int brcm_sata_phy_init(struct phy *phy)
419{
420 int rc;
421 struct brcm_sata_port *port = phy_get_drvdata(phy);
422
423 switch (port->phy_priv->version) {
424 case BRCM_SATA_PHY_STB_28NM:
425 case BRCM_SATA_PHY_STB_40NM:
426 rc = brcm_stb_sata_init(port);
427 break;
428 case BRCM_SATA_PHY_IPROC_NS2:
429 rc = brcm_ns2_sata_init(port);
430 break;
431 case BRCM_SATA_PHY_IPROC_NSP:
432 rc = brcm_nsp_sata_init(port);
433 break;
434 case BRCM_SATA_PHY_IPROC_SR:
435 rc = brcm_sr_sata_init(port);
436 break;
437 default:
438 rc = -ENODEV;
439 }
440
441 return rc;
442}
443
444static const struct phy_ops phy_ops = {
445 .init = brcm_sata_phy_init,
446 .owner = THIS_MODULE,
447};
448
449static const struct of_device_id brcm_sata_phy_of_match[] = {
450 { .compatible = "brcm,bcm7445-sata-phy",
451 .data = (void *)BRCM_SATA_PHY_STB_28NM },
452 { .compatible = "brcm,bcm7425-sata-phy",
453 .data = (void *)BRCM_SATA_PHY_STB_40NM },
454 { .compatible = "brcm,iproc-ns2-sata-phy",
455 .data = (void *)BRCM_SATA_PHY_IPROC_NS2 },
456 { .compatible = "brcm,iproc-nsp-sata-phy",
457 .data = (void *)BRCM_SATA_PHY_IPROC_NSP },
458 { .compatible = "brcm,iproc-sr-sata-phy",
459 .data = (void *)BRCM_SATA_PHY_IPROC_SR },
460 {},
461};
462MODULE_DEVICE_TABLE(of, brcm_sata_phy_of_match);
463
464static int brcm_sata_phy_probe(struct platform_device *pdev)
465{
466 struct device *dev = &pdev->dev;
467 struct device_node *dn = dev->of_node, *child;
468 const struct of_device_id *of_id;
469 struct brcm_sata_phy *priv;
470 struct resource *res;
471 struct phy_provider *provider;
472 int ret, count = 0;
473
474 if (of_get_child_count(dn) == 0)
475 return -ENODEV;
476
477 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
478 if (!priv)
479 return -ENOMEM;
480 dev_set_drvdata(dev, priv);
481 priv->dev = dev;
482
483 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy");
484 priv->phy_base = devm_ioremap_resource(dev, res);
485 if (IS_ERR(priv->phy_base))
486 return PTR_ERR(priv->phy_base);
487
488 of_id = of_match_node(brcm_sata_phy_of_match, dn);
489 if (of_id)
490 priv->version = (enum brcm_sata_phy_version)of_id->data;
491 else
492 priv->version = BRCM_SATA_PHY_STB_28NM;
493
494 if (priv->version == BRCM_SATA_PHY_IPROC_NS2) {
495 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
496 "phy-ctrl");
497 priv->ctrl_base = devm_ioremap_resource(dev, res);
498 if (IS_ERR(priv->ctrl_base))
499 return PTR_ERR(priv->ctrl_base);
500 }
501
502 for_each_available_child_of_node(dn, child) {
503 unsigned int id;
504 struct brcm_sata_port *port;
505
506 if (of_property_read_u32(child, "reg", &id)) {
507 dev_err(dev, "missing reg property in node %s\n",
508 child->name);
509 ret = -EINVAL;
510 goto put_child;
511 }
512
513 if (id >= MAX_PORTS) {
514 dev_err(dev, "invalid reg: %u\n", id);
515 ret = -EINVAL;
516 goto put_child;
517 }
518 if (priv->phys[id].phy) {
519 dev_err(dev, "already registered port %u\n", id);
520 ret = -EINVAL;
521 goto put_child;
522 }
523
524 port = &priv->phys[id];
525 port->portnum = id;
526 port->phy_priv = priv;
527 port->phy = devm_phy_create(dev, child, &phy_ops);
528 port->ssc_en = of_property_read_bool(child, "brcm,enable-ssc");
529 if (IS_ERR(port->phy)) {
530 dev_err(dev, "failed to create PHY\n");
531 ret = PTR_ERR(port->phy);
532 goto put_child;
533 }
534
535 phy_set_drvdata(port->phy, port);
536 count++;
537 }
538
539 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
540 if (IS_ERR(provider)) {
541 dev_err(dev, "could not register PHY provider\n");
542 return PTR_ERR(provider);
543 }
544
545 dev_info(dev, "registered %d port(s)\n", count);
546
547 return 0;
548put_child:
549 of_node_put(child);
550 return ret;
551}
552
553static struct platform_driver brcm_sata_phy_driver = {
554 .probe = brcm_sata_phy_probe,
555 .driver = {
556 .of_match_table = brcm_sata_phy_of_match,
557 .name = "brcm-sata-phy",
558 }
559};
560module_platform_driver(brcm_sata_phy_driver);
561
562MODULE_DESCRIPTION("Broadcom SATA PHY driver");
563MODULE_LICENSE("GPL");
564MODULE_AUTHOR("Marc Carino");
565MODULE_AUTHOR("Brian Norris");
566MODULE_ALIAS("platform:phy-brcm-sata");
567
