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13#include <linux/clk.h>
14#include <linux/module.h>
15#include <linux/phy/phy.h>
16#include <linux/io.h>
17#include <linux/platform_device.h>
18
19#define HOST_VSA_ADDR 0x0
20#define HOST_VSA_DATA 0x4
21#define PORT_SCR_CTL 0x2c
22#define PORT_VSR_ADDR 0x78
23#define PORT_VSR_DATA 0x7c
24
25#define CONTROL_REGISTER 0x0
26#define MBUS_SIZE_CONTROL 0x4
27
28#define POWER_DOWN_PHY0 BIT(6)
29#define POWER_DOWN_PHY1 BIT(14)
30#define MBUS_WRITE_REQUEST_SIZE_128 (BIT(2) << 16)
31#define MBUS_READ_REQUEST_SIZE_128 (BIT(2) << 19)
32
33#define BG2_PHY_BASE 0x080
34#define BG2Q_PHY_BASE 0x200
35
36
37#define REF_FREF_SEL_25 BIT(0)
38#define PHY_MODE_SATA (0x0 << 5)
39
40
41#define USE_MAX_PLL_RATE BIT(12)
42
43
44#define DATA_BIT_WIDTH_10 (0x0 << 10)
45#define DATA_BIT_WIDTH_20 (0x1 << 10)
46#define DATA_BIT_WIDTH_40 (0x2 << 10)
47
48
49#define PHY_GEN_MAX_1_5 (0x0 << 10)
50#define PHY_GEN_MAX_3_0 (0x1 << 10)
51#define PHY_GEN_MAX_6_0 (0x2 << 10)
52
53struct phy_berlin_desc {
54 struct phy *phy;
55 u32 power_bit;
56 unsigned index;
57};
58
59struct phy_berlin_priv {
60 void __iomem *base;
61 spinlock_t lock;
62 struct clk *clk;
63 struct phy_berlin_desc **phys;
64 unsigned nphys;
65 u32 phy_base;
66};
67
68static inline void phy_berlin_sata_reg_setbits(void __iomem *ctrl_reg,
69 u32 phy_base, u32 reg, u32 mask, u32 val)
70{
71 u32 regval;
72
73
74 writel(phy_base + reg, ctrl_reg + PORT_VSR_ADDR);
75
76
77 regval = readl(ctrl_reg + PORT_VSR_DATA);
78 regval &= ~mask;
79 regval |= val;
80 writel(regval, ctrl_reg + PORT_VSR_DATA);
81}
82
83static int phy_berlin_sata_power_on(struct phy *phy)
84{
85 struct phy_berlin_desc *desc = phy_get_drvdata(phy);
86 struct phy_berlin_priv *priv = dev_get_drvdata(phy->dev.parent);
87 void __iomem *ctrl_reg = priv->base + 0x60 + (desc->index * 0x80);
88 u32 regval;
89
90 clk_prepare_enable(priv->clk);
91
92 spin_lock(&priv->lock);
93
94
95 writel(CONTROL_REGISTER, priv->base + HOST_VSA_ADDR);
96 regval = readl(priv->base + HOST_VSA_DATA);
97 regval &= ~desc->power_bit;
98 writel(regval, priv->base + HOST_VSA_DATA);
99
100
101 writel(MBUS_SIZE_CONTROL, priv->base + HOST_VSA_ADDR);
102 regval = readl(priv->base + HOST_VSA_DATA);
103 regval |= MBUS_WRITE_REQUEST_SIZE_128 | MBUS_READ_REQUEST_SIZE_128;
104 writel(regval, priv->base + HOST_VSA_DATA);
105
106
107 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01,
108 0x00ff, REF_FREF_SEL_25 | PHY_MODE_SATA);
109
110
111 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25,
112 0x0c00, PHY_GEN_MAX_6_0);
113
114
115 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x23,
116 0x0c00, DATA_BIT_WIDTH_40);
117
118
119 phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x02,
120 0x0000, USE_MAX_PLL_RATE);
121
122
123 regval = readl(ctrl_reg + PORT_SCR_CTL);
124 regval &= ~GENMASK(7, 4);
125 regval |= 0x30;
126 writel(regval, ctrl_reg + PORT_SCR_CTL);
127
128 spin_unlock(&priv->lock);
129
130 clk_disable_unprepare(priv->clk);
131
132 return 0;
133}
134
135static int phy_berlin_sata_power_off(struct phy *phy)
136{
137 struct phy_berlin_desc *desc = phy_get_drvdata(phy);
138 struct phy_berlin_priv *priv = dev_get_drvdata(phy->dev.parent);
139 u32 regval;
140
141 clk_prepare_enable(priv->clk);
142
143 spin_lock(&priv->lock);
144
145
146 writel(CONTROL_REGISTER, priv->base + HOST_VSA_ADDR);
147 regval = readl(priv->base + HOST_VSA_DATA);
148 regval |= desc->power_bit;
149 writel(regval, priv->base + HOST_VSA_DATA);
150
151 spin_unlock(&priv->lock);
152
153 clk_disable_unprepare(priv->clk);
154
155 return 0;
156}
157
158static struct phy *phy_berlin_sata_phy_xlate(struct device *dev,
159 struct of_phandle_args *args)
160{
161 struct phy_berlin_priv *priv = dev_get_drvdata(dev);
162 int i;
163
164 if (WARN_ON(args->args[0] >= priv->nphys))
165 return ERR_PTR(-ENODEV);
166
167 for (i = 0; i < priv->nphys; i++) {
168 if (priv->phys[i]->index == args->args[0])
169 break;
170 }
171
172 if (i == priv->nphys)
173 return ERR_PTR(-ENODEV);
174
175 return priv->phys[i]->phy;
176}
177
178static const struct phy_ops phy_berlin_sata_ops = {
179 .power_on = phy_berlin_sata_power_on,
180 .power_off = phy_berlin_sata_power_off,
181 .owner = THIS_MODULE,
182};
183
184static u32 phy_berlin_power_down_bits[] = {
185 POWER_DOWN_PHY0,
186 POWER_DOWN_PHY1,
187};
188
189static int phy_berlin_sata_probe(struct platform_device *pdev)
190{
191 struct device *dev = &pdev->dev;
192 struct device_node *child;
193 struct phy *phy;
194 struct phy_provider *phy_provider;
195 struct phy_berlin_priv *priv;
196 struct resource *res;
197 int ret, i = 0;
198 u32 phy_id;
199
200 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
201 if (!priv)
202 return -ENOMEM;
203
204 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
205 if (!res)
206 return -EINVAL;
207
208 priv->base = devm_ioremap(dev, res->start, resource_size(res));
209 if (!priv->base)
210 return -ENOMEM;
211
212 priv->clk = devm_clk_get(dev, NULL);
213 if (IS_ERR(priv->clk))
214 return PTR_ERR(priv->clk);
215
216 priv->nphys = of_get_child_count(dev->of_node);
217 if (priv->nphys == 0)
218 return -ENODEV;
219
220 priv->phys = devm_kcalloc(dev, priv->nphys, sizeof(*priv->phys),
221 GFP_KERNEL);
222 if (!priv->phys)
223 return -ENOMEM;
224
225 if (of_device_is_compatible(dev->of_node, "marvell,berlin2-sata-phy"))
226 priv->phy_base = BG2_PHY_BASE;
227 else
228 priv->phy_base = BG2Q_PHY_BASE;
229
230 dev_set_drvdata(dev, priv);
231 spin_lock_init(&priv->lock);
232
233 for_each_available_child_of_node(dev->of_node, child) {
234 struct phy_berlin_desc *phy_desc;
235
236 if (of_property_read_u32(child, "reg", &phy_id)) {
237 dev_err(dev, "missing reg property in node %s\n",
238 child->name);
239 ret = -EINVAL;
240 goto put_child;
241 }
242
243 if (phy_id >= ARRAY_SIZE(phy_berlin_power_down_bits)) {
244 dev_err(dev, "invalid reg in node %s\n", child->name);
245 ret = -EINVAL;
246 goto put_child;
247 }
248
249 phy_desc = devm_kzalloc(dev, sizeof(*phy_desc), GFP_KERNEL);
250 if (!phy_desc) {
251 ret = -ENOMEM;
252 goto put_child;
253 }
254
255 phy = devm_phy_create(dev, NULL, &phy_berlin_sata_ops);
256 if (IS_ERR(phy)) {
257 dev_err(dev, "failed to create PHY %d\n", phy_id);
258 ret = PTR_ERR(phy);
259 goto put_child;
260 }
261
262 phy_desc->phy = phy;
263 phy_desc->power_bit = phy_berlin_power_down_bits[phy_id];
264 phy_desc->index = phy_id;
265 phy_set_drvdata(phy, phy_desc);
266
267 priv->phys[i++] = phy_desc;
268
269
270 phy_berlin_sata_power_off(phy);
271 }
272
273 phy_provider =
274 devm_of_phy_provider_register(dev, phy_berlin_sata_phy_xlate);
275 return PTR_ERR_OR_ZERO(phy_provider);
276put_child:
277 of_node_put(child);
278 return ret;
279}
280
281static const struct of_device_id phy_berlin_sata_of_match[] = {
282 { .compatible = "marvell,berlin2-sata-phy" },
283 { .compatible = "marvell,berlin2q-sata-phy" },
284 { },
285};
286MODULE_DEVICE_TABLE(of, phy_berlin_sata_of_match);
287
288static struct platform_driver phy_berlin_sata_driver = {
289 .probe = phy_berlin_sata_probe,
290 .driver = {
291 .name = "phy-berlin-sata",
292 .of_match_table = phy_berlin_sata_of_match,
293 },
294};
295module_platform_driver(phy_berlin_sata_driver);
296
297MODULE_DESCRIPTION("Marvell Berlin SATA PHY driver");
298MODULE_AUTHOR("Antoine Ténart <antoine.tenart@free-electrons.com>");
299MODULE_LICENSE("GPL v2");
300
