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12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/io.h>
15#include <linux/slab.h>
16#include <linux/err.h>
17#include <linux/list.h>
18#include <linux/interrupt.h>
19
20#include <linux/irqchip/chained_irq.h>
21
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/of_address.h>
25#include <linux/of_irq.h>
26
27#include <linux/pinctrl/pinctrl.h>
28#include <linux/pinctrl/pinmux.h>
29#include <linux/pinctrl/pinconf-generic.h>
30
31#include <linux/platform_data/pinctrl-single.h>
32
33#include "core.h"
34#include "devicetree.h"
35#include "pinconf.h"
36#include "pinmux.h"
37
38#define DRIVER_NAME "pinctrl-single"
39#define PCS_OFF_DISABLED ~0U
40
41
42
43
44
45
46struct pcs_func_vals {
47 void __iomem *reg;
48 unsigned val;
49 unsigned mask;
50};
51
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60
61struct pcs_conf_vals {
62 enum pin_config_param param;
63 unsigned val;
64 unsigned enable;
65 unsigned disable;
66 unsigned mask;
67};
68
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72
73
74struct pcs_conf_type {
75 const char *name;
76 enum pin_config_param param;
77};
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86
87
88struct pcs_function {
89 const char *name;
90 struct pcs_func_vals *vals;
91 unsigned nvals;
92 const char **pgnames;
93 int npgnames;
94 struct pcs_conf_vals *conf;
95 int nconfs;
96 struct list_head node;
97};
98
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105
106struct pcs_gpiofunc_range {
107 unsigned offset;
108 unsigned npins;
109 unsigned gpiofunc;
110 struct list_head node;
111};
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121
122struct pcs_data {
123 struct pinctrl_pin_desc *pa;
124 int cur;
125};
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134
135struct pcs_soc_data {
136 unsigned flags;
137 int irq;
138 unsigned irq_enable_mask;
139 unsigned irq_status_mask;
140 void (*rearm)(void);
141};
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171
172struct pcs_device {
173 struct resource *res;
174 void __iomem *base;
175 unsigned size;
176 struct device *dev;
177 struct device_node *np;
178 struct pinctrl_dev *pctl;
179 unsigned flags;
180#define PCS_QUIRK_SHARED_IRQ (1 << 2)
181#define PCS_FEAT_IRQ (1 << 1)
182#define PCS_FEAT_PINCONF (1 << 0)
183 struct property *missing_nr_pinctrl_cells;
184 struct pcs_soc_data socdata;
185 raw_spinlock_t lock;
186 struct mutex mutex;
187 unsigned width;
188 unsigned fmask;
189 unsigned fshift;
190 unsigned foff;
191 unsigned fmax;
192 bool bits_per_mux;
193 unsigned bits_per_pin;
194 struct pcs_data pins;
195 struct list_head gpiofuncs;
196 struct list_head irqs;
197 struct irq_chip chip;
198 struct irq_domain *domain;
199 struct pinctrl_desc desc;
200 unsigned (*read)(void __iomem *reg);
201 void (*write)(unsigned val, void __iomem *reg);
202};
203
204#define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
205#define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
206#define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
207
208static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
209 unsigned long *config);
210static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
211 unsigned long *configs, unsigned num_configs);
212
213static enum pin_config_param pcs_bias[] = {
214 PIN_CONFIG_BIAS_PULL_DOWN,
215 PIN_CONFIG_BIAS_PULL_UP,
216};
217
218
219
220
221
222
223static struct lock_class_key pcs_lock_class;
224
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232
233
234static unsigned __maybe_unused pcs_readb(void __iomem *reg)
235{
236 return readb(reg);
237}
238
239static unsigned __maybe_unused pcs_readw(void __iomem *reg)
240{
241 return readw(reg);
242}
243
244static unsigned __maybe_unused pcs_readl(void __iomem *reg)
245{
246 return readl(reg);
247}
248
249static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
250{
251 writeb(val, reg);
252}
253
254static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
255{
256 writew(val, reg);
257}
258
259static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
260{
261 writel(val, reg);
262}
263
264static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
265 struct seq_file *s,
266 unsigned pin)
267{
268 struct pcs_device *pcs;
269 unsigned val, mux_bytes;
270 unsigned long offset;
271 size_t pa;
272
273 pcs = pinctrl_dev_get_drvdata(pctldev);
274
275 mux_bytes = pcs->width / BITS_PER_BYTE;
276 offset = pin * mux_bytes;
277 val = pcs->read(pcs->base + offset);
278 pa = pcs->res->start + offset;
279
280 seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
281}
282
283static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
284 struct pinctrl_map *map, unsigned num_maps)
285{
286 struct pcs_device *pcs;
287
288 pcs = pinctrl_dev_get_drvdata(pctldev);
289 devm_kfree(pcs->dev, map);
290}
291
292static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
293 struct device_node *np_config,
294 struct pinctrl_map **map, unsigned *num_maps);
295
296static const struct pinctrl_ops pcs_pinctrl_ops = {
297 .get_groups_count = pinctrl_generic_get_group_count,
298 .get_group_name = pinctrl_generic_get_group_name,
299 .get_group_pins = pinctrl_generic_get_group_pins,
300 .pin_dbg_show = pcs_pin_dbg_show,
301 .dt_node_to_map = pcs_dt_node_to_map,
302 .dt_free_map = pcs_dt_free_map,
303};
304
305static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
306 struct pcs_function **func)
307{
308 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
309 struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
310 const struct pinctrl_setting_mux *setting;
311 struct function_desc *function;
312 unsigned fselector;
313
314
315 setting = pdesc->mux_setting;
316 if (!setting)
317 return -ENOTSUPP;
318 fselector = setting->func;
319 function = pinmux_generic_get_function(pctldev, fselector);
320 *func = function->data;
321 if (!(*func)) {
322 dev_err(pcs->dev, "%s could not find function%i\n",
323 __func__, fselector);
324 return -ENOTSUPP;
325 }
326 return 0;
327}
328
329static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
330 unsigned group)
331{
332 struct pcs_device *pcs;
333 struct function_desc *function;
334 struct pcs_function *func;
335 int i;
336
337 pcs = pinctrl_dev_get_drvdata(pctldev);
338
339 if (!pcs->fmask)
340 return 0;
341 function = pinmux_generic_get_function(pctldev, fselector);
342 func = function->data;
343 if (!func)
344 return -EINVAL;
345
346 dev_dbg(pcs->dev, "enabling %s function%i\n",
347 func->name, fselector);
348
349 for (i = 0; i < func->nvals; i++) {
350 struct pcs_func_vals *vals;
351 unsigned long flags;
352 unsigned val, mask;
353
354 vals = &func->vals[i];
355 raw_spin_lock_irqsave(&pcs->lock, flags);
356 val = pcs->read(vals->reg);
357
358 if (pcs->bits_per_mux)
359 mask = vals->mask;
360 else
361 mask = pcs->fmask;
362
363 val &= ~mask;
364 val |= (vals->val & mask);
365 pcs->write(val, vals->reg);
366 raw_spin_unlock_irqrestore(&pcs->lock, flags);
367 }
368
369 return 0;
370}
371
372static int pcs_request_gpio(struct pinctrl_dev *pctldev,
373 struct pinctrl_gpio_range *range, unsigned pin)
374{
375 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
376 struct pcs_gpiofunc_range *frange = NULL;
377 struct list_head *pos, *tmp;
378 int mux_bytes = 0;
379 unsigned data;
380
381
382 if (!pcs->fmask)
383 return -ENOTSUPP;
384
385 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
386 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
387 if (pin >= frange->offset + frange->npins
388 || pin < frange->offset)
389 continue;
390 mux_bytes = pcs->width / BITS_PER_BYTE;
391 data = pcs->read(pcs->base + pin * mux_bytes) & ~pcs->fmask;
392 data |= frange->gpiofunc;
393 pcs->write(data, pcs->base + pin * mux_bytes);
394 break;
395 }
396 return 0;
397}
398
399static const struct pinmux_ops pcs_pinmux_ops = {
400 .get_functions_count = pinmux_generic_get_function_count,
401 .get_function_name = pinmux_generic_get_function_name,
402 .get_function_groups = pinmux_generic_get_function_groups,
403 .set_mux = pcs_set_mux,
404 .gpio_request_enable = pcs_request_gpio,
405};
406
407
408static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
409{
410 unsigned long config;
411 int i;
412 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
413 config = pinconf_to_config_packed(pcs_bias[i], 0);
414 pcs_pinconf_set(pctldev, pin, &config, 1);
415 }
416}
417
418
419
420
421
422static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
423{
424 unsigned long config;
425 int i;
426
427 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
428 config = pinconf_to_config_packed(pcs_bias[i], 0);
429 if (!pcs_pinconf_get(pctldev, pin, &config))
430 goto out;
431 }
432 return true;
433out:
434 return false;
435}
436
437static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
438 unsigned pin, unsigned long *config)
439{
440 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
441 struct pcs_function *func;
442 enum pin_config_param param;
443 unsigned offset = 0, data = 0, i, j, ret;
444
445 ret = pcs_get_function(pctldev, pin, &func);
446 if (ret)
447 return ret;
448
449 for (i = 0; i < func->nconfs; i++) {
450 param = pinconf_to_config_param(*config);
451 if (param == PIN_CONFIG_BIAS_DISABLE) {
452 if (pcs_pinconf_bias_disable(pctldev, pin)) {
453 *config = 0;
454 return 0;
455 } else {
456 return -ENOTSUPP;
457 }
458 } else if (param != func->conf[i].param) {
459 continue;
460 }
461
462 offset = pin * (pcs->width / BITS_PER_BYTE);
463 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
464 switch (func->conf[i].param) {
465
466 case PIN_CONFIG_BIAS_PULL_DOWN:
467 case PIN_CONFIG_BIAS_PULL_UP:
468 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
469 if ((data != func->conf[i].enable) ||
470 (data == func->conf[i].disable))
471 return -ENOTSUPP;
472 *config = 0;
473 break;
474
475 case PIN_CONFIG_INPUT_SCHMITT:
476 for (j = 0; j < func->nconfs; j++) {
477 switch (func->conf[j].param) {
478 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
479 if (data != func->conf[j].enable)
480 return -ENOTSUPP;
481 break;
482 default:
483 break;
484 }
485 }
486 *config = data;
487 break;
488 case PIN_CONFIG_DRIVE_STRENGTH:
489 case PIN_CONFIG_SLEW_RATE:
490 case PIN_CONFIG_LOW_POWER_MODE:
491 default:
492 *config = data;
493 break;
494 }
495 return 0;
496 }
497 return -ENOTSUPP;
498}
499
500static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
501 unsigned pin, unsigned long *configs,
502 unsigned num_configs)
503{
504 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
505 struct pcs_function *func;
506 unsigned offset = 0, shift = 0, i, data, ret;
507 u32 arg;
508 int j;
509
510 ret = pcs_get_function(pctldev, pin, &func);
511 if (ret)
512 return ret;
513
514 for (j = 0; j < num_configs; j++) {
515 for (i = 0; i < func->nconfs; i++) {
516 if (pinconf_to_config_param(configs[j])
517 != func->conf[i].param)
518 continue;
519
520 offset = pin * (pcs->width / BITS_PER_BYTE);
521 data = pcs->read(pcs->base + offset);
522 arg = pinconf_to_config_argument(configs[j]);
523 switch (func->conf[i].param) {
524
525 case PIN_CONFIG_INPUT_SCHMITT:
526 case PIN_CONFIG_DRIVE_STRENGTH:
527 case PIN_CONFIG_SLEW_RATE:
528 case PIN_CONFIG_LOW_POWER_MODE:
529 shift = ffs(func->conf[i].mask) - 1;
530 data &= ~func->conf[i].mask;
531 data |= (arg << shift) & func->conf[i].mask;
532 break;
533
534 case PIN_CONFIG_BIAS_DISABLE:
535 pcs_pinconf_clear_bias(pctldev, pin);
536 break;
537 case PIN_CONFIG_BIAS_PULL_DOWN:
538 case PIN_CONFIG_BIAS_PULL_UP:
539 if (arg)
540 pcs_pinconf_clear_bias(pctldev, pin);
541
542 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
543 data &= ~func->conf[i].mask;
544 if (arg)
545 data |= func->conf[i].enable;
546 else
547 data |= func->conf[i].disable;
548 break;
549 default:
550 return -ENOTSUPP;
551 }
552 pcs->write(data, pcs->base + offset);
553
554 break;
555 }
556 if (i >= func->nconfs)
557 return -ENOTSUPP;
558 }
559
560 return 0;
561}
562
563static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
564 unsigned group, unsigned long *config)
565{
566 const unsigned *pins;
567 unsigned npins, old = 0;
568 int i, ret;
569
570 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
571 if (ret)
572 return ret;
573 for (i = 0; i < npins; i++) {
574 if (pcs_pinconf_get(pctldev, pins[i], config))
575 return -ENOTSUPP;
576
577 if (i && (old != *config))
578 return -ENOTSUPP;
579 old = *config;
580 }
581 return 0;
582}
583
584static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
585 unsigned group, unsigned long *configs,
586 unsigned num_configs)
587{
588 const unsigned *pins;
589 unsigned npins;
590 int i, ret;
591
592 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
593 if (ret)
594 return ret;
595 for (i = 0; i < npins; i++) {
596 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
597 return -ENOTSUPP;
598 }
599 return 0;
600}
601
602static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
603 struct seq_file *s, unsigned pin)
604{
605}
606
607static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
608 struct seq_file *s, unsigned selector)
609{
610}
611
612static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
613 struct seq_file *s,
614 unsigned long config)
615{
616 pinconf_generic_dump_config(pctldev, s, config);
617}
618
619static const struct pinconf_ops pcs_pinconf_ops = {
620 .pin_config_get = pcs_pinconf_get,
621 .pin_config_set = pcs_pinconf_set,
622 .pin_config_group_get = pcs_pinconf_group_get,
623 .pin_config_group_set = pcs_pinconf_group_set,
624 .pin_config_dbg_show = pcs_pinconf_dbg_show,
625 .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
626 .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
627 .is_generic = true,
628};
629
630
631
632
633
634
635static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
636 unsigned pin_pos)
637{
638 struct pcs_soc_data *pcs_soc = &pcs->socdata;
639 struct pinctrl_pin_desc *pin;
640 int i;
641
642 i = pcs->pins.cur;
643 if (i >= pcs->desc.npins) {
644 dev_err(pcs->dev, "too many pins, max %i\n",
645 pcs->desc.npins);
646 return -ENOMEM;
647 }
648
649 if (pcs_soc->irq_enable_mask) {
650 unsigned val;
651
652 val = pcs->read(pcs->base + offset);
653 if (val & pcs_soc->irq_enable_mask) {
654 dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
655 (unsigned long)pcs->res->start + offset, val);
656 val &= ~pcs_soc->irq_enable_mask;
657 pcs->write(val, pcs->base + offset);
658 }
659 }
660
661 pin = &pcs->pins.pa[i];
662 pin->number = i;
663 pcs->pins.cur++;
664
665 return i;
666}
667
668
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675
676
677static int pcs_allocate_pin_table(struct pcs_device *pcs)
678{
679 int mux_bytes, nr_pins, i;
680 int num_pins_in_register = 0;
681
682 mux_bytes = pcs->width / BITS_PER_BYTE;
683
684 if (pcs->bits_per_mux) {
685 pcs->bits_per_pin = fls(pcs->fmask);
686 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
687 num_pins_in_register = pcs->width / pcs->bits_per_pin;
688 } else {
689 nr_pins = pcs->size / mux_bytes;
690 }
691
692 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
693 pcs->pins.pa = devm_kzalloc(pcs->dev,
694 sizeof(*pcs->pins.pa) * nr_pins,
695 GFP_KERNEL);
696 if (!pcs->pins.pa)
697 return -ENOMEM;
698
699 pcs->desc.pins = pcs->pins.pa;
700 pcs->desc.npins = nr_pins;
701
702 for (i = 0; i < pcs->desc.npins; i++) {
703 unsigned offset;
704 int res;
705 int byte_num;
706 int pin_pos = 0;
707
708 if (pcs->bits_per_mux) {
709 byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
710 offset = (byte_num / mux_bytes) * mux_bytes;
711 pin_pos = i % num_pins_in_register;
712 } else {
713 offset = i * mux_bytes;
714 }
715 res = pcs_add_pin(pcs, offset, pin_pos);
716 if (res < 0) {
717 dev_err(pcs->dev, "error adding pins: %i\n", res);
718 return res;
719 }
720 }
721
722 return 0;
723}
724
725
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733
734
735static struct pcs_function *pcs_add_function(struct pcs_device *pcs,
736 struct device_node *np,
737 const char *name,
738 struct pcs_func_vals *vals,
739 unsigned nvals,
740 const char **pgnames,
741 unsigned npgnames)
742{
743 struct pcs_function *function;
744 int res;
745
746 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
747 if (!function)
748 return NULL;
749
750 function->vals = vals;
751 function->nvals = nvals;
752
753 res = pinmux_generic_add_function(pcs->pctl, name,
754 pgnames, npgnames,
755 function);
756 if (res)
757 return NULL;
758
759 return function;
760}
761
762
763
764
765
766
767
768
769static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
770{
771 unsigned index;
772
773 if (offset >= pcs->size) {
774 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
775 offset, pcs->size);
776 return -EINVAL;
777 }
778
779 if (pcs->bits_per_mux)
780 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
781 else
782 index = offset / (pcs->width / BITS_PER_BYTE);
783
784 return index;
785}
786
787
788
789
790
791
792static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
793{
794 int ret = -EINVAL;
795
796 if (data == enable)
797 ret = 1;
798 else if (data == disable)
799 ret = 0;
800 return ret;
801}
802
803static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
804 unsigned value, unsigned enable, unsigned disable,
805 unsigned mask)
806{
807 (*conf)->param = param;
808 (*conf)->val = value;
809 (*conf)->enable = enable;
810 (*conf)->disable = disable;
811 (*conf)->mask = mask;
812 (*conf)++;
813}
814
815static void add_setting(unsigned long **setting, enum pin_config_param param,
816 unsigned arg)
817{
818 **setting = pinconf_to_config_packed(param, arg);
819 (*setting)++;
820}
821
822
823static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
824 const char *name, enum pin_config_param param,
825 struct pcs_conf_vals **conf, unsigned long **settings)
826{
827 unsigned value[2], shift;
828 int ret;
829
830 ret = of_property_read_u32_array(np, name, value, 2);
831 if (ret)
832 return;
833
834 value[0] &= value[1];
835 shift = ffs(value[1]) - 1;
836
837 add_config(conf, param, value[0], 0, 0, value[1]);
838 add_setting(settings, param, value[0] >> shift);
839}
840
841
842static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
843 const char *name, enum pin_config_param param,
844 struct pcs_conf_vals **conf, unsigned long **settings)
845{
846 unsigned value[4];
847 int ret;
848
849
850 ret = of_property_read_u32_array(np, name, value, 4);
851 if (ret)
852 return;
853 if (!value[3]) {
854 dev_err(pcs->dev, "mask field of the property can't be 0\n");
855 return;
856 }
857 value[0] &= value[3];
858 value[1] &= value[3];
859 value[2] &= value[3];
860 ret = pcs_config_match(value[0], value[1], value[2]);
861 if (ret < 0)
862 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
863 add_config(conf, param, value[0], value[1], value[2], value[3]);
864 add_setting(settings, param, ret);
865}
866
867static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
868 struct pcs_function *func,
869 struct pinctrl_map **map)
870
871{
872 struct pinctrl_map *m = *map;
873 int i = 0, nconfs = 0;
874 unsigned long *settings = NULL, *s = NULL;
875 struct pcs_conf_vals *conf = NULL;
876 struct pcs_conf_type prop2[] = {
877 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
878 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
879 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
880 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
881 };
882 struct pcs_conf_type prop4[] = {
883 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
884 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
885 { "pinctrl-single,input-schmitt-enable",
886 PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
887 };
888
889
890 if (!PCS_HAS_PINCONF)
891 return 0;
892
893
894 for (i = 0; i < ARRAY_SIZE(prop2); i++) {
895 if (of_find_property(np, prop2[i].name, NULL))
896 nconfs++;
897 }
898 for (i = 0; i < ARRAY_SIZE(prop4); i++) {
899 if (of_find_property(np, prop4[i].name, NULL))
900 nconfs++;
901 }
902 if (!nconfs)
903 return 0;
904
905 func->conf = devm_kzalloc(pcs->dev,
906 sizeof(struct pcs_conf_vals) * nconfs,
907 GFP_KERNEL);
908 if (!func->conf)
909 return -ENOMEM;
910 func->nconfs = nconfs;
911 conf = &(func->conf[0]);
912 m++;
913 settings = devm_kzalloc(pcs->dev, sizeof(unsigned long) * nconfs,
914 GFP_KERNEL);
915 if (!settings)
916 return -ENOMEM;
917 s = &settings[0];
918
919 for (i = 0; i < ARRAY_SIZE(prop2); i++)
920 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
921 &conf, &s);
922 for (i = 0; i < ARRAY_SIZE(prop4); i++)
923 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
924 &conf, &s);
925 m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
926 m->data.configs.group_or_pin = np->name;
927 m->data.configs.configs = settings;
928 m->data.configs.num_configs = nconfs;
929 return 0;
930}
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
953 struct device_node *np,
954 struct pinctrl_map **map,
955 unsigned *num_maps,
956 const char **pgnames)
957{
958 const char *name = "pinctrl-single,pins";
959 struct pcs_func_vals *vals;
960 int rows, *pins, found = 0, res = -ENOMEM, i;
961 struct pcs_function *function;
962
963 rows = pinctrl_count_index_with_args(np, name);
964 if (rows <= 0) {
965 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
966 return -EINVAL;
967 }
968
969 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL);
970 if (!vals)
971 return -ENOMEM;
972
973 pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows, GFP_KERNEL);
974 if (!pins)
975 goto free_vals;
976
977 for (i = 0; i < rows; i++) {
978 struct of_phandle_args pinctrl_spec;
979 unsigned int offset;
980 int pin;
981
982 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
983 if (res)
984 return res;
985
986 if (pinctrl_spec.args_count < 2) {
987 dev_err(pcs->dev, "invalid args_count for spec: %i\n",
988 pinctrl_spec.args_count);
989 break;
990 }
991
992
993 offset = pinctrl_spec.args[0];
994 vals[found].reg = pcs->base + offset;
995 vals[found].val = pinctrl_spec.args[1];
996
997 dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x\n",
998 pinctrl_spec.np->name, offset, pinctrl_spec.args[1]);
999
1000 pin = pcs_get_pin_by_offset(pcs, offset);
1001 if (pin < 0) {
1002 dev_err(pcs->dev,
1003 "could not add functions for %s %ux\n",
1004 np->name, offset);
1005 break;
1006 }
1007 pins[found++] = pin;
1008 }
1009
1010 pgnames[0] = np->name;
1011 function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1012 if (!function) {
1013 res = -ENOMEM;
1014 goto free_pins;
1015 }
1016
1017 res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1018 if (res < 0)
1019 goto free_function;
1020
1021 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1022 (*map)->data.mux.group = np->name;
1023 (*map)->data.mux.function = np->name;
1024
1025 if (PCS_HAS_PINCONF) {
1026 res = pcs_parse_pinconf(pcs, np, function, map);
1027 if (res)
1028 goto free_pingroups;
1029 *num_maps = 2;
1030 } else {
1031 *num_maps = 1;
1032 }
1033 return 0;
1034
1035free_pingroups:
1036 pinctrl_generic_remove_last_group(pcs->pctl);
1037 *num_maps = 1;
1038free_function:
1039 pinmux_generic_remove_last_function(pcs->pctl);
1040
1041free_pins:
1042 devm_kfree(pcs->dev, pins);
1043
1044free_vals:
1045 devm_kfree(pcs->dev, vals);
1046
1047 return res;
1048}
1049
1050static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1051 struct device_node *np,
1052 struct pinctrl_map **map,
1053 unsigned *num_maps,
1054 const char **pgnames)
1055{
1056 const char *name = "pinctrl-single,bits";
1057 struct pcs_func_vals *vals;
1058 int rows, *pins, found = 0, res = -ENOMEM, i;
1059 int npins_in_row;
1060 struct pcs_function *function;
1061
1062 rows = pinctrl_count_index_with_args(np, name);
1063 if (rows <= 0) {
1064 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1065 return -EINVAL;
1066 }
1067
1068 npins_in_row = pcs->width / pcs->bits_per_pin;
1069
1070 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows * npins_in_row,
1071 GFP_KERNEL);
1072 if (!vals)
1073 return -ENOMEM;
1074
1075 pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows * npins_in_row,
1076 GFP_KERNEL);
1077 if (!pins)
1078 goto free_vals;
1079
1080 for (i = 0; i < rows; i++) {
1081 struct of_phandle_args pinctrl_spec;
1082 unsigned offset, val;
1083 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1084 unsigned pin_num_from_lsb;
1085 int pin;
1086
1087 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1088 if (res)
1089 return res;
1090
1091 if (pinctrl_spec.args_count < 3) {
1092 dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1093 pinctrl_spec.args_count);
1094 break;
1095 }
1096
1097
1098 offset = pinctrl_spec.args[0];
1099 val = pinctrl_spec.args[1];
1100 mask = pinctrl_spec.args[2];
1101
1102 dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x mask: 0x%x\n",
1103 pinctrl_spec.np->name, offset, val, mask);
1104
1105
1106 while (mask) {
1107 bit_pos = __ffs(mask);
1108 pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1109 mask_pos = ((pcs->fmask) << bit_pos);
1110 val_pos = val & mask_pos;
1111 submask = mask & mask_pos;
1112
1113 if ((mask & mask_pos) == 0) {
1114 dev_err(pcs->dev,
1115 "Invalid mask for %s at 0x%x\n",
1116 np->name, offset);
1117 break;
1118 }
1119
1120 mask &= ~mask_pos;
1121
1122 if (submask != mask_pos) {
1123 dev_warn(pcs->dev,
1124 "Invalid submask 0x%x for %s at 0x%x\n",
1125 submask, np->name, offset);
1126 continue;
1127 }
1128
1129 vals[found].mask = submask;
1130 vals[found].reg = pcs->base + offset;
1131 vals[found].val = val_pos;
1132
1133 pin = pcs_get_pin_by_offset(pcs, offset);
1134 if (pin < 0) {
1135 dev_err(pcs->dev,
1136 "could not add functions for %s %ux\n",
1137 np->name, offset);
1138 break;
1139 }
1140 pins[found++] = pin + pin_num_from_lsb;
1141 }
1142 }
1143
1144 pgnames[0] = np->name;
1145 function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1146 if (!function) {
1147 res = -ENOMEM;
1148 goto free_pins;
1149 }
1150
1151 res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1152 if (res < 0)
1153 goto free_function;
1154
1155 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1156 (*map)->data.mux.group = np->name;
1157 (*map)->data.mux.function = np->name;
1158
1159 if (PCS_HAS_PINCONF) {
1160 dev_err(pcs->dev, "pinconf not supported\n");
1161 goto free_pingroups;
1162 }
1163
1164 *num_maps = 1;
1165 return 0;
1166
1167free_pingroups:
1168 pinctrl_generic_remove_last_group(pcs->pctl);
1169 *num_maps = 1;
1170free_function:
1171 pinmux_generic_remove_last_function(pcs->pctl);
1172free_pins:
1173 devm_kfree(pcs->dev, pins);
1174
1175free_vals:
1176 devm_kfree(pcs->dev, vals);
1177
1178 return res;
1179}
1180
1181
1182
1183
1184
1185
1186
1187static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1188 struct device_node *np_config,
1189 struct pinctrl_map **map, unsigned *num_maps)
1190{
1191 struct pcs_device *pcs;
1192 const char **pgnames;
1193 int ret;
1194
1195 pcs = pinctrl_dev_get_drvdata(pctldev);
1196
1197
1198 *map = devm_kzalloc(pcs->dev, sizeof(**map) * 2, GFP_KERNEL);
1199 if (!*map)
1200 return -ENOMEM;
1201
1202 *num_maps = 0;
1203
1204 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1205 if (!pgnames) {
1206 ret = -ENOMEM;
1207 goto free_map;
1208 }
1209
1210 if (pcs->bits_per_mux) {
1211 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1212 num_maps, pgnames);
1213 if (ret < 0) {
1214 dev_err(pcs->dev, "no pins entries for %s\n",
1215 np_config->name);
1216 goto free_pgnames;
1217 }
1218 } else {
1219 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1220 num_maps, pgnames);
1221 if (ret < 0) {
1222 dev_err(pcs->dev, "no pins entries for %s\n",
1223 np_config->name);
1224 goto free_pgnames;
1225 }
1226 }
1227
1228 return 0;
1229
1230free_pgnames:
1231 devm_kfree(pcs->dev, pgnames);
1232free_map:
1233 devm_kfree(pcs->dev, *map);
1234
1235 return ret;
1236}
1237
1238
1239
1240
1241
1242static void pcs_irq_free(struct pcs_device *pcs)
1243{
1244 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1245
1246 if (pcs_soc->irq < 0)
1247 return;
1248
1249 if (pcs->domain)
1250 irq_domain_remove(pcs->domain);
1251
1252 if (PCS_QUIRK_HAS_SHARED_IRQ)
1253 free_irq(pcs_soc->irq, pcs_soc);
1254 else
1255 irq_set_chained_handler(pcs_soc->irq, NULL);
1256}
1257
1258
1259
1260
1261
1262static void pcs_free_resources(struct pcs_device *pcs)
1263{
1264 pcs_irq_free(pcs);
1265 pinctrl_unregister(pcs->pctl);
1266
1267#if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1268 if (pcs->missing_nr_pinctrl_cells)
1269 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
1270#endif
1271}
1272
1273static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1274{
1275 const char *propname = "pinctrl-single,gpio-range";
1276 const char *cellname = "#pinctrl-single,gpio-range-cells";
1277 struct of_phandle_args gpiospec;
1278 struct pcs_gpiofunc_range *range;
1279 int ret, i;
1280
1281 for (i = 0; ; i++) {
1282 ret = of_parse_phandle_with_args(node, propname, cellname,
1283 i, &gpiospec);
1284
1285 if (ret) {
1286 ret = 0;
1287 break;
1288 }
1289 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1290 if (!range) {
1291 ret = -ENOMEM;
1292 break;
1293 }
1294 range->offset = gpiospec.args[0];
1295 range->npins = gpiospec.args[1];
1296 range->gpiofunc = gpiospec.args[2];
1297 mutex_lock(&pcs->mutex);
1298 list_add_tail(&range->node, &pcs->gpiofuncs);
1299 mutex_unlock(&pcs->mutex);
1300 }
1301 return ret;
1302}
1303
1304
1305
1306
1307
1308
1309struct pcs_interrupt {
1310 void __iomem *reg;
1311 irq_hw_number_t hwirq;
1312 unsigned int irq;
1313 struct list_head node;
1314};
1315
1316
1317
1318
1319
1320
1321
1322static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1323 int irq, const bool enable)
1324{
1325 struct pcs_device *pcs;
1326 struct list_head *pos;
1327 unsigned mask;
1328
1329 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1330 list_for_each(pos, &pcs->irqs) {
1331 struct pcs_interrupt *pcswi;
1332 unsigned soc_mask;
1333
1334 pcswi = list_entry(pos, struct pcs_interrupt, node);
1335 if (irq != pcswi->irq)
1336 continue;
1337
1338 soc_mask = pcs_soc->irq_enable_mask;
1339 raw_spin_lock(&pcs->lock);
1340 mask = pcs->read(pcswi->reg);
1341 if (enable)
1342 mask |= soc_mask;
1343 else
1344 mask &= ~soc_mask;
1345 pcs->write(mask, pcswi->reg);
1346
1347
1348 mask = pcs->read(pcswi->reg);
1349 raw_spin_unlock(&pcs->lock);
1350 }
1351
1352 if (pcs_soc->rearm)
1353 pcs_soc->rearm();
1354}
1355
1356
1357
1358
1359
1360static void pcs_irq_mask(struct irq_data *d)
1361{
1362 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1363
1364 pcs_irq_set(pcs_soc, d->irq, false);
1365}
1366
1367
1368
1369
1370
1371static void pcs_irq_unmask(struct irq_data *d)
1372{
1373 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1374
1375 pcs_irq_set(pcs_soc, d->irq, true);
1376}
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1387{
1388 if (state)
1389 pcs_irq_unmask(d);
1390 else
1391 pcs_irq_mask(d);
1392
1393 return 0;
1394}
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1405{
1406 struct pcs_device *pcs;
1407 struct list_head *pos;
1408 int count = 0;
1409
1410 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1411 list_for_each(pos, &pcs->irqs) {
1412 struct pcs_interrupt *pcswi;
1413 unsigned mask;
1414
1415 pcswi = list_entry(pos, struct pcs_interrupt, node);
1416 raw_spin_lock(&pcs->lock);
1417 mask = pcs->read(pcswi->reg);
1418 raw_spin_unlock(&pcs->lock);
1419 if (mask & pcs_soc->irq_status_mask) {
1420 generic_handle_irq(irq_find_mapping(pcs->domain,
1421 pcswi->hwirq));
1422 count++;
1423 }
1424 }
1425
1426 return count;
1427}
1428
1429
1430
1431
1432
1433
1434
1435
1436
1437static irqreturn_t pcs_irq_handler(int irq, void *d)
1438{
1439 struct pcs_soc_data *pcs_soc = d;
1440
1441 return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1442}
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452static void pcs_irq_chain_handler(struct irq_desc *desc)
1453{
1454 struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1455 struct irq_chip *chip;
1456
1457 chip = irq_desc_get_chip(desc);
1458 chained_irq_enter(chip, desc);
1459 pcs_irq_handle(pcs_soc);
1460
1461 chained_irq_exit(chip, desc);
1462
1463 return;
1464}
1465
1466static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1467 irq_hw_number_t hwirq)
1468{
1469 struct pcs_soc_data *pcs_soc = d->host_data;
1470 struct pcs_device *pcs;
1471 struct pcs_interrupt *pcswi;
1472
1473 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1474 pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1475 if (!pcswi)
1476 return -ENOMEM;
1477
1478 pcswi->reg = pcs->base + hwirq;
1479 pcswi->hwirq = hwirq;
1480 pcswi->irq = irq;
1481
1482 mutex_lock(&pcs->mutex);
1483 list_add_tail(&pcswi->node, &pcs->irqs);
1484 mutex_unlock(&pcs->mutex);
1485
1486 irq_set_chip_data(irq, pcs_soc);
1487 irq_set_chip_and_handler(irq, &pcs->chip,
1488 handle_level_irq);
1489 irq_set_lockdep_class(irq, &pcs_lock_class);
1490 irq_set_noprobe(irq);
1491
1492 return 0;
1493}
1494
1495static const struct irq_domain_ops pcs_irqdomain_ops = {
1496 .map = pcs_irqdomain_map,
1497 .xlate = irq_domain_xlate_onecell,
1498};
1499
1500
1501
1502
1503
1504
1505static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1506 struct device_node *np)
1507{
1508 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1509 const char *name = "pinctrl";
1510 int num_irqs;
1511
1512 if (!pcs_soc->irq_enable_mask ||
1513 !pcs_soc->irq_status_mask) {
1514 pcs_soc->irq = -1;
1515 return -EINVAL;
1516 }
1517
1518 INIT_LIST_HEAD(&pcs->irqs);
1519 pcs->chip.name = name;
1520 pcs->chip.irq_ack = pcs_irq_mask;
1521 pcs->chip.irq_mask = pcs_irq_mask;
1522 pcs->chip.irq_unmask = pcs_irq_unmask;
1523 pcs->chip.irq_set_wake = pcs_irq_set_wake;
1524
1525 if (PCS_QUIRK_HAS_SHARED_IRQ) {
1526 int res;
1527
1528 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1529 IRQF_SHARED | IRQF_NO_SUSPEND |
1530 IRQF_NO_THREAD,
1531 name, pcs_soc);
1532 if (res) {
1533 pcs_soc->irq = -1;
1534 return res;
1535 }
1536 } else {
1537 irq_set_chained_handler_and_data(pcs_soc->irq,
1538 pcs_irq_chain_handler,
1539 pcs_soc);
1540 }
1541
1542
1543
1544
1545
1546
1547
1548 num_irqs = pcs->size;
1549
1550 pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1551 &pcs_irqdomain_ops,
1552 pcs_soc);
1553 if (!pcs->domain) {
1554 irq_set_chained_handler(pcs_soc->irq, NULL);
1555 return -EINVAL;
1556 }
1557
1558 return 0;
1559}
1560
1561#ifdef CONFIG_PM
1562static int pinctrl_single_suspend(struct platform_device *pdev,
1563 pm_message_t state)
1564{
1565 struct pcs_device *pcs;
1566
1567 pcs = platform_get_drvdata(pdev);
1568 if (!pcs)
1569 return -EINVAL;
1570
1571 return pinctrl_force_sleep(pcs->pctl);
1572}
1573
1574static int pinctrl_single_resume(struct platform_device *pdev)
1575{
1576 struct pcs_device *pcs;
1577
1578 pcs = platform_get_drvdata(pdev);
1579 if (!pcs)
1580 return -EINVAL;
1581
1582 return pinctrl_force_default(pcs->pctl);
1583}
1584#endif
1585
1586
1587
1588
1589
1590
1591
1592
1593
1594
1595
1596static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
1597 struct device_node *np,
1598 int cells)
1599{
1600 struct property *p;
1601 const char *name = "#pinctrl-cells";
1602 int error;
1603 u32 val;
1604
1605 error = of_property_read_u32(np, name, &val);
1606 if (!error)
1607 return 0;
1608
1609 dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
1610 name, cells);
1611
1612 p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
1613 if (!p)
1614 return -ENOMEM;
1615
1616 p->length = sizeof(__be32);
1617 p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
1618 if (!p->value)
1619 return -ENOMEM;
1620 *(__be32 *)p->value = cpu_to_be32(cells);
1621
1622 p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
1623 if (!p->name)
1624 return -ENOMEM;
1625
1626 pcs->missing_nr_pinctrl_cells = p;
1627
1628#if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1629 error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
1630#endif
1631
1632 return error;
1633}
1634
1635static int pcs_probe(struct platform_device *pdev)
1636{
1637 struct device_node *np = pdev->dev.of_node;
1638 struct pcs_pdata *pdata;
1639 struct resource *res;
1640 struct pcs_device *pcs;
1641 const struct pcs_soc_data *soc;
1642 int ret;
1643
1644 soc = of_device_get_match_data(&pdev->dev);
1645 if (WARN_ON(!soc))
1646 return -EINVAL;
1647
1648 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1649 if (!pcs) {
1650 dev_err(&pdev->dev, "could not allocate\n");
1651 return -ENOMEM;
1652 }
1653 pcs->dev = &pdev->dev;
1654 pcs->np = np;
1655 raw_spin_lock_init(&pcs->lock);
1656 mutex_init(&pcs->mutex);
1657 INIT_LIST_HEAD(&pcs->gpiofuncs);
1658 pcs->flags = soc->flags;
1659 memcpy(&pcs->socdata, soc, sizeof(*soc));
1660
1661 ret = of_property_read_u32(np, "pinctrl-single,register-width",
1662 &pcs->width);
1663 if (ret) {
1664 dev_err(pcs->dev, "register width not specified\n");
1665
1666 return ret;
1667 }
1668
1669 ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1670 &pcs->fmask);
1671 if (!ret) {
1672 pcs->fshift = __ffs(pcs->fmask);
1673 pcs->fmax = pcs->fmask >> pcs->fshift;
1674 } else {
1675
1676 pcs->fmask = 0;
1677 pcs->fshift = 0;
1678 pcs->fmax = 0;
1679 }
1680
1681 ret = of_property_read_u32(np, "pinctrl-single,function-off",
1682 &pcs->foff);
1683 if (ret)
1684 pcs->foff = PCS_OFF_DISABLED;
1685
1686 pcs->bits_per_mux = of_property_read_bool(np,
1687 "pinctrl-single,bit-per-mux");
1688 ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
1689 pcs->bits_per_mux ? 2 : 1);
1690 if (ret) {
1691 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n");
1692
1693 return ret;
1694 }
1695
1696 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1697 if (!res) {
1698 dev_err(pcs->dev, "could not get resource\n");
1699 return -ENODEV;
1700 }
1701
1702 pcs->res = devm_request_mem_region(pcs->dev, res->start,
1703 resource_size(res), DRIVER_NAME);
1704 if (!pcs->res) {
1705 dev_err(pcs->dev, "could not get mem_region\n");
1706 return -EBUSY;
1707 }
1708
1709 pcs->size = resource_size(pcs->res);
1710 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1711 if (!pcs->base) {
1712 dev_err(pcs->dev, "could not ioremap\n");
1713 return -ENODEV;
1714 }
1715
1716 platform_set_drvdata(pdev, pcs);
1717
1718 switch (pcs->width) {
1719 case 8:
1720 pcs->read = pcs_readb;
1721 pcs->write = pcs_writeb;
1722 break;
1723 case 16:
1724 pcs->read = pcs_readw;
1725 pcs->write = pcs_writew;
1726 break;
1727 case 32:
1728 pcs->read = pcs_readl;
1729 pcs->write = pcs_writel;
1730 break;
1731 default:
1732 break;
1733 }
1734
1735 pcs->desc.name = DRIVER_NAME;
1736 pcs->desc.pctlops = &pcs_pinctrl_ops;
1737 pcs->desc.pmxops = &pcs_pinmux_ops;
1738 if (PCS_HAS_PINCONF)
1739 pcs->desc.confops = &pcs_pinconf_ops;
1740 pcs->desc.owner = THIS_MODULE;
1741
1742 ret = pcs_allocate_pin_table(pcs);
1743 if (ret < 0)
1744 goto free;
1745
1746 ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl);
1747 if (ret) {
1748 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1749 goto free;
1750 }
1751
1752 ret = pcs_add_gpio_func(np, pcs);
1753 if (ret < 0)
1754 goto free;
1755
1756 pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1757 if (pcs->socdata.irq)
1758 pcs->flags |= PCS_FEAT_IRQ;
1759
1760
1761 pdata = dev_get_platdata(&pdev->dev);
1762 if (pdata) {
1763 if (pdata->rearm)
1764 pcs->socdata.rearm = pdata->rearm;
1765 if (pdata->irq) {
1766 pcs->socdata.irq = pdata->irq;
1767 pcs->flags |= PCS_FEAT_IRQ;
1768 }
1769 }
1770
1771 if (PCS_HAS_IRQ) {
1772 ret = pcs_irq_init_chained_handler(pcs, np);
1773 if (ret < 0)
1774 dev_warn(pcs->dev, "initialized with no interrupts\n");
1775 }
1776
1777 dev_info(pcs->dev, "%i pins at pa %p size %u\n",
1778 pcs->desc.npins, pcs->base, pcs->size);
1779
1780 return pinctrl_enable(pcs->pctl);
1781
1782free:
1783 pcs_free_resources(pcs);
1784
1785 return ret;
1786}
1787
1788static int pcs_remove(struct platform_device *pdev)
1789{
1790 struct pcs_device *pcs = platform_get_drvdata(pdev);
1791
1792 if (!pcs)
1793 return 0;
1794
1795 pcs_free_resources(pcs);
1796
1797 return 0;
1798}
1799
1800static const struct pcs_soc_data pinctrl_single_omap_wkup = {
1801 .flags = PCS_QUIRK_SHARED_IRQ,
1802 .irq_enable_mask = (1 << 14),
1803 .irq_status_mask = (1 << 15),
1804};
1805
1806static const struct pcs_soc_data pinctrl_single_dra7 = {
1807 .irq_enable_mask = (1 << 24),
1808 .irq_status_mask = (1 << 25),
1809};
1810
1811static const struct pcs_soc_data pinctrl_single_am437x = {
1812 .flags = PCS_QUIRK_SHARED_IRQ,
1813 .irq_enable_mask = (1 << 29),
1814 .irq_status_mask = (1 << 30),
1815};
1816
1817static const struct pcs_soc_data pinctrl_single = {
1818};
1819
1820static const struct pcs_soc_data pinconf_single = {
1821 .flags = PCS_FEAT_PINCONF,
1822};
1823
1824static const struct of_device_id pcs_of_match[] = {
1825 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1826 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1827 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1828 { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1829 { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1830 { .compatible = "pinctrl-single", .data = &pinctrl_single },
1831 { .compatible = "pinconf-single", .data = &pinconf_single },
1832 { },
1833};
1834MODULE_DEVICE_TABLE(of, pcs_of_match);
1835
1836static struct platform_driver pcs_driver = {
1837 .probe = pcs_probe,
1838 .remove = pcs_remove,
1839 .driver = {
1840 .name = DRIVER_NAME,
1841 .of_match_table = pcs_of_match,
1842 },
1843#ifdef CONFIG_PM
1844 .suspend = pinctrl_single_suspend,
1845 .resume = pinctrl_single_resume,
1846#endif
1847};
1848
1849module_platform_driver(pcs_driver);
1850
1851MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
1852MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
1853MODULE_LICENSE("GPL v2");
1854