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21#include <linux/debugfs.h>
22#include <linux/delay.h>
23#include <linux/device.h>
24#include <linux/init.h>
25#include <linux/io.h>
26#include <linux/pci.h>
27#include <linux/uaccess.h>
28
29#include <asm/cpu_device_id.h>
30#include <asm/intel-family.h>
31#include <asm/pmc_core.h>
32
33#include "intel_pmc_core.h"
34
35static struct pmc_dev pmc;
36
37static const struct pmc_bit_map spt_pll_map[] = {
38 {"MIPI PLL", SPT_PMC_BIT_MPHY_CMN_LANE0},
39 {"GEN2 USB2PCIE2 PLL", SPT_PMC_BIT_MPHY_CMN_LANE1},
40 {"DMIPCIE3 PLL", SPT_PMC_BIT_MPHY_CMN_LANE2},
41 {"SATA PLL", SPT_PMC_BIT_MPHY_CMN_LANE3},
42 {},
43};
44
45static const struct pmc_bit_map spt_mphy_map[] = {
46 {"MPHY CORE LANE 0", SPT_PMC_BIT_MPHY_LANE0},
47 {"MPHY CORE LANE 1", SPT_PMC_BIT_MPHY_LANE1},
48 {"MPHY CORE LANE 2", SPT_PMC_BIT_MPHY_LANE2},
49 {"MPHY CORE LANE 3", SPT_PMC_BIT_MPHY_LANE3},
50 {"MPHY CORE LANE 4", SPT_PMC_BIT_MPHY_LANE4},
51 {"MPHY CORE LANE 5", SPT_PMC_BIT_MPHY_LANE5},
52 {"MPHY CORE LANE 6", SPT_PMC_BIT_MPHY_LANE6},
53 {"MPHY CORE LANE 7", SPT_PMC_BIT_MPHY_LANE7},
54 {"MPHY CORE LANE 8", SPT_PMC_BIT_MPHY_LANE8},
55 {"MPHY CORE LANE 9", SPT_PMC_BIT_MPHY_LANE9},
56 {"MPHY CORE LANE 10", SPT_PMC_BIT_MPHY_LANE10},
57 {"MPHY CORE LANE 11", SPT_PMC_BIT_MPHY_LANE11},
58 {"MPHY CORE LANE 12", SPT_PMC_BIT_MPHY_LANE12},
59 {"MPHY CORE LANE 13", SPT_PMC_BIT_MPHY_LANE13},
60 {"MPHY CORE LANE 14", SPT_PMC_BIT_MPHY_LANE14},
61 {"MPHY CORE LANE 15", SPT_PMC_BIT_MPHY_LANE15},
62 {},
63};
64
65static const struct pmc_bit_map spt_pfear_map[] = {
66 {"PMC", SPT_PMC_BIT_PMC},
67 {"OPI-DMI", SPT_PMC_BIT_OPI},
68 {"SPI / eSPI", SPT_PMC_BIT_SPI},
69 {"XHCI", SPT_PMC_BIT_XHCI},
70 {"SPA", SPT_PMC_BIT_SPA},
71 {"SPB", SPT_PMC_BIT_SPB},
72 {"SPC", SPT_PMC_BIT_SPC},
73 {"GBE", SPT_PMC_BIT_GBE},
74 {"SATA", SPT_PMC_BIT_SATA},
75 {"HDA-PGD0", SPT_PMC_BIT_HDA_PGD0},
76 {"HDA-PGD1", SPT_PMC_BIT_HDA_PGD1},
77 {"HDA-PGD2", SPT_PMC_BIT_HDA_PGD2},
78 {"HDA-PGD3", SPT_PMC_BIT_HDA_PGD3},
79 {"RSVD", SPT_PMC_BIT_RSVD_0B},
80 {"LPSS", SPT_PMC_BIT_LPSS},
81 {"LPC", SPT_PMC_BIT_LPC},
82 {"SMB", SPT_PMC_BIT_SMB},
83 {"ISH", SPT_PMC_BIT_ISH},
84 {"P2SB", SPT_PMC_BIT_P2SB},
85 {"DFX", SPT_PMC_BIT_DFX},
86 {"SCC", SPT_PMC_BIT_SCC},
87 {"RSVD", SPT_PMC_BIT_RSVD_0C},
88 {"FUSE", SPT_PMC_BIT_FUSE},
89 {"CAMERA", SPT_PMC_BIT_CAMREA},
90 {"RSVD", SPT_PMC_BIT_RSVD_0D},
91 {"USB3-OTG", SPT_PMC_BIT_USB3_OTG},
92 {"EXI", SPT_PMC_BIT_EXI},
93 {"CSE", SPT_PMC_BIT_CSE},
94 {"CSME_KVM", SPT_PMC_BIT_CSME_KVM},
95 {"CSME_PMT", SPT_PMC_BIT_CSME_PMT},
96 {"CSME_CLINK", SPT_PMC_BIT_CSME_CLINK},
97 {"CSME_PTIO", SPT_PMC_BIT_CSME_PTIO},
98 {"CSME_USBR", SPT_PMC_BIT_CSME_USBR},
99 {"CSME_SUSRAM", SPT_PMC_BIT_CSME_SUSRAM},
100 {"CSME_SMT", SPT_PMC_BIT_CSME_SMT},
101 {"RSVD", SPT_PMC_BIT_RSVD_1A},
102 {"CSME_SMS2", SPT_PMC_BIT_CSME_SMS2},
103 {"CSME_SMS1", SPT_PMC_BIT_CSME_SMS1},
104 {"CSME_RTC", SPT_PMC_BIT_CSME_RTC},
105 {"CSME_PSF", SPT_PMC_BIT_CSME_PSF},
106 {},
107};
108
109static const struct pmc_reg_map spt_reg_map = {
110 .pfear_sts = spt_pfear_map,
111 .mphy_sts = spt_mphy_map,
112 .pll_sts = spt_pll_map,
113};
114
115static const struct pci_device_id pmc_pci_ids[] = {
116 { PCI_VDEVICE(INTEL, SPT_PMC_PCI_DEVICE_ID),
117 (kernel_ulong_t)&spt_reg_map },
118 { 0, },
119};
120
121static inline u8 pmc_core_reg_read_byte(struct pmc_dev *pmcdev, int offset)
122{
123 return readb(pmcdev->regbase + offset);
124}
125
126static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
127{
128 return readl(pmcdev->regbase + reg_offset);
129}
130
131static inline void pmc_core_reg_write(struct pmc_dev *pmcdev, int
132 reg_offset, u32 val)
133{
134 writel(val, pmcdev->regbase + reg_offset);
135}
136
137static inline u32 pmc_core_adjust_slp_s0_step(u32 value)
138{
139 return value * SPT_PMC_SLP_S0_RES_COUNTER_STEP;
140}
141
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155
156
157int intel_pmc_slp_s0_counter_read(u32 *data)
158{
159 struct pmc_dev *pmcdev = &pmc;
160 u32 value;
161
162 if (!pmcdev->has_slp_s0_res)
163 return -EACCES;
164
165 value = pmc_core_reg_read(pmcdev, SPT_PMC_SLP_S0_RES_COUNTER_OFFSET);
166 *data = pmc_core_adjust_slp_s0_step(value);
167
168 return 0;
169}
170EXPORT_SYMBOL_GPL(intel_pmc_slp_s0_counter_read);
171
172static int pmc_core_dev_state_get(void *data, u64 *val)
173{
174 struct pmc_dev *pmcdev = data;
175 u32 value;
176
177 value = pmc_core_reg_read(pmcdev, SPT_PMC_SLP_S0_RES_COUNTER_OFFSET);
178 *val = pmc_core_adjust_slp_s0_step(value);
179
180 return 0;
181}
182
183DEFINE_DEBUGFS_ATTRIBUTE(pmc_core_dev_state, pmc_core_dev_state_get, NULL, "%llu\n");
184
185static int pmc_core_check_read_lock_bit(void)
186{
187 struct pmc_dev *pmcdev = &pmc;
188 u32 value;
189
190 value = pmc_core_reg_read(pmcdev, SPT_PMC_PM_CFG_OFFSET);
191 return value & BIT(SPT_PMC_READ_DISABLE_BIT);
192}
193
194#if IS_ENABLED(CONFIG_DEBUG_FS)
195static void pmc_core_display_map(struct seq_file *s, int index,
196 u8 pf_reg, const struct pmc_bit_map *pf_map)
197{
198 seq_printf(s, "PCH IP: %-2d - %-32s\tState: %s\n",
199 index, pf_map[index].name,
200 pf_map[index].bit_mask & pf_reg ? "Off" : "On");
201}
202
203static int pmc_core_ppfear_sts_show(struct seq_file *s, void *unused)
204{
205 struct pmc_dev *pmcdev = s->private;
206 const struct pmc_bit_map *map = pmcdev->map->pfear_sts;
207 u8 pf_regs[NUM_ENTRIES];
208 int index, iter;
209
210 iter = SPT_PMC_XRAM_PPFEAR0A;
211
212 for (index = 0; index < NUM_ENTRIES; index++, iter++)
213 pf_regs[index] = pmc_core_reg_read_byte(pmcdev, iter);
214
215 for (index = 0; map[index].name; index++)
216 pmc_core_display_map(s, index, pf_regs[index / 8], map);
217
218 return 0;
219}
220
221static int pmc_core_ppfear_sts_open(struct inode *inode, struct file *file)
222{
223 return single_open(file, pmc_core_ppfear_sts_show, inode->i_private);
224}
225
226static const struct file_operations pmc_core_ppfear_ops = {
227 .open = pmc_core_ppfear_sts_open,
228 .read = seq_read,
229 .llseek = seq_lseek,
230 .release = single_release,
231};
232
233
234static int pmc_core_mtpmc_link_status(void)
235{
236 struct pmc_dev *pmcdev = &pmc;
237 u32 value;
238
239 value = pmc_core_reg_read(pmcdev, SPT_PMC_PM_STS_OFFSET);
240 return value & BIT(SPT_PMC_MSG_FULL_STS_BIT);
241}
242
243static int pmc_core_send_msg(u32 *addr_xram)
244{
245 struct pmc_dev *pmcdev = &pmc;
246 u32 dest;
247 int timeout;
248
249 for (timeout = NUM_RETRIES; timeout > 0; timeout--) {
250 if (pmc_core_mtpmc_link_status() == 0)
251 break;
252 msleep(5);
253 }
254
255 if (timeout <= 0 && pmc_core_mtpmc_link_status())
256 return -EBUSY;
257
258 dest = (*addr_xram & MTPMC_MASK) | (1U << 1);
259 pmc_core_reg_write(pmcdev, SPT_PMC_MTPMC_OFFSET, dest);
260 return 0;
261}
262
263static int pmc_core_mphy_pg_sts_show(struct seq_file *s, void *unused)
264{
265 struct pmc_dev *pmcdev = s->private;
266 const struct pmc_bit_map *map = pmcdev->map->mphy_sts;
267 u32 mphy_core_reg_low, mphy_core_reg_high;
268 u32 val_low, val_high;
269 int index, err = 0;
270
271 if (pmcdev->pmc_xram_read_bit) {
272 seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
273 return 0;
274 }
275
276 mphy_core_reg_low = (SPT_PMC_MPHY_CORE_STS_0 << 16);
277 mphy_core_reg_high = (SPT_PMC_MPHY_CORE_STS_1 << 16);
278
279 mutex_lock(&pmcdev->lock);
280
281 if (pmc_core_send_msg(&mphy_core_reg_low) != 0) {
282 err = -EBUSY;
283 goto out_unlock;
284 }
285
286 msleep(10);
287 val_low = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
288
289 if (pmc_core_send_msg(&mphy_core_reg_high) != 0) {
290 err = -EBUSY;
291 goto out_unlock;
292 }
293
294 msleep(10);
295 val_high = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
296
297 for (index = 0; map[index].name && index < 8; index++) {
298 seq_printf(s, "%-32s\tState: %s\n",
299 map[index].name,
300 map[index].bit_mask & val_low ? "Not power gated" :
301 "Power gated");
302 }
303
304 for (index = 8; map[index].name; index++) {
305 seq_printf(s, "%-32s\tState: %s\n",
306 map[index].name,
307 map[index].bit_mask & val_high ? "Not power gated" :
308 "Power gated");
309 }
310
311out_unlock:
312 mutex_unlock(&pmcdev->lock);
313 return err;
314}
315
316static int pmc_core_mphy_pg_sts_open(struct inode *inode, struct file *file)
317{
318 return single_open(file, pmc_core_mphy_pg_sts_show, inode->i_private);
319}
320
321static const struct file_operations pmc_core_mphy_pg_ops = {
322 .open = pmc_core_mphy_pg_sts_open,
323 .read = seq_read,
324 .llseek = seq_lseek,
325 .release = single_release,
326};
327
328static int pmc_core_pll_show(struct seq_file *s, void *unused)
329{
330 struct pmc_dev *pmcdev = s->private;
331 const struct pmc_bit_map *map = pmcdev->map->pll_sts;
332 u32 mphy_common_reg, val;
333 int index, err = 0;
334
335 if (pmcdev->pmc_xram_read_bit) {
336 seq_puts(s, "Access denied: please disable PMC_READ_DISABLE setting in BIOS.");
337 return 0;
338 }
339
340 mphy_common_reg = (SPT_PMC_MPHY_COM_STS_0 << 16);
341 mutex_lock(&pmcdev->lock);
342
343 if (pmc_core_send_msg(&mphy_common_reg) != 0) {
344 err = -EBUSY;
345 goto out_unlock;
346 }
347
348
349 msleep(10);
350 val = pmc_core_reg_read(pmcdev, SPT_PMC_MFPMC_OFFSET);
351
352 for (index = 0; map[index].name ; index++) {
353 seq_printf(s, "%-32s\tState: %s\n",
354 map[index].name,
355 map[index].bit_mask & val ? "Active" : "Idle");
356 }
357
358out_unlock:
359 mutex_unlock(&pmcdev->lock);
360 return err;
361}
362
363static int pmc_core_pll_open(struct inode *inode, struct file *file)
364{
365 return single_open(file, pmc_core_pll_show, inode->i_private);
366}
367
368static const struct file_operations pmc_core_pll_ops = {
369 .open = pmc_core_pll_open,
370 .read = seq_read,
371 .llseek = seq_lseek,
372 .release = single_release,
373};
374
375static ssize_t pmc_core_ltr_ignore_write(struct file *file, const char __user
376*userbuf, size_t count, loff_t *ppos)
377{
378 struct pmc_dev *pmcdev = &pmc;
379 u32 val, buf_size, fd;
380 int err = 0;
381
382 buf_size = count < 64 ? count : 64;
383 mutex_lock(&pmcdev->lock);
384
385 if (kstrtou32_from_user(userbuf, buf_size, 10, &val)) {
386 err = -EFAULT;
387 goto out_unlock;
388 }
389
390 if (val > NUM_IP_IGN_ALLOWED) {
391 err = -EINVAL;
392 goto out_unlock;
393 }
394
395 fd = pmc_core_reg_read(pmcdev, SPT_PMC_LTR_IGNORE_OFFSET);
396 fd |= (1U << val);
397 pmc_core_reg_write(pmcdev, SPT_PMC_LTR_IGNORE_OFFSET, fd);
398
399out_unlock:
400 mutex_unlock(&pmcdev->lock);
401 return err == 0 ? count : err;
402}
403
404static int pmc_core_ltr_ignore_show(struct seq_file *s, void *unused)
405{
406 return 0;
407}
408
409static int pmc_core_ltr_ignore_open(struct inode *inode, struct file *file)
410{
411 return single_open(file, pmc_core_ltr_ignore_show, inode->i_private);
412}
413
414static const struct file_operations pmc_core_ltr_ignore_ops = {
415 .open = pmc_core_ltr_ignore_open,
416 .read = seq_read,
417 .write = pmc_core_ltr_ignore_write,
418 .llseek = seq_lseek,
419 .release = single_release,
420};
421
422static void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
423{
424 debugfs_remove_recursive(pmcdev->dbgfs_dir);
425}
426
427static int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
428{
429 struct dentry *dir, *file;
430
431 dir = debugfs_create_dir("pmc_core", NULL);
432 if (!dir)
433 return -ENOMEM;
434
435 pmcdev->dbgfs_dir = dir;
436 file = debugfs_create_file("slp_s0_residency_usec", S_IFREG | S_IRUGO,
437 dir, pmcdev, &pmc_core_dev_state);
438 if (!file)
439 goto err;
440
441 file = debugfs_create_file("pch_ip_power_gating_status",
442 S_IFREG | S_IRUGO, dir, pmcdev,
443 &pmc_core_ppfear_ops);
444 if (!file)
445 goto err;
446
447 file = debugfs_create_file("mphy_core_lanes_power_gating_status",
448 S_IFREG | S_IRUGO, dir, pmcdev,
449 &pmc_core_mphy_pg_ops);
450 if (!file)
451 goto err;
452
453 file = debugfs_create_file("pll_status",
454 S_IFREG | S_IRUGO, dir, pmcdev,
455 &pmc_core_pll_ops);
456 if (!file)
457 goto err;
458
459 file = debugfs_create_file("ltr_ignore",
460 S_IFREG | S_IRUGO, dir, pmcdev,
461 &pmc_core_ltr_ignore_ops);
462
463 if (!file)
464 goto err;
465
466 return 0;
467err:
468 pmc_core_dbgfs_unregister(pmcdev);
469 return -ENODEV;
470}
471#else
472static inline int pmc_core_dbgfs_register(struct pmc_dev *pmcdev)
473{
474 return 0;
475}
476
477static inline void pmc_core_dbgfs_unregister(struct pmc_dev *pmcdev)
478{
479}
480#endif
481
482static const struct x86_cpu_id intel_pmc_core_ids[] = {
483 { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_MOBILE, X86_FEATURE_MWAIT,
484 (kernel_ulong_t)NULL},
485 { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_DESKTOP, X86_FEATURE_MWAIT,
486 (kernel_ulong_t)NULL},
487 { X86_VENDOR_INTEL, 6, INTEL_FAM6_KABYLAKE_MOBILE, X86_FEATURE_MWAIT,
488 (kernel_ulong_t)NULL},
489 { X86_VENDOR_INTEL, 6, INTEL_FAM6_KABYLAKE_DESKTOP, X86_FEATURE_MWAIT,
490 (kernel_ulong_t)NULL},
491 {}
492};
493
494static int pmc_core_probe(struct pci_dev *dev, const struct pci_device_id *id)
495{
496 struct device *ptr_dev = &dev->dev;
497 struct pmc_dev *pmcdev = &pmc;
498 const struct x86_cpu_id *cpu_id;
499 const struct pmc_reg_map *map = (struct pmc_reg_map *)id->driver_data;
500 int err;
501
502 cpu_id = x86_match_cpu(intel_pmc_core_ids);
503 if (!cpu_id) {
504 dev_dbg(&dev->dev, "PMC Core: cpuid mismatch.\n");
505 return -EINVAL;
506 }
507
508 err = pcim_enable_device(dev);
509 if (err < 0) {
510 dev_dbg(&dev->dev, "PMC Core: failed to enable Power Management Controller.\n");
511 return err;
512 }
513
514 err = pci_read_config_dword(dev,
515 SPT_PMC_BASE_ADDR_OFFSET,
516 &pmcdev->base_addr);
517 if (err < 0) {
518 dev_dbg(&dev->dev, "PMC Core: failed to read PCI config space.\n");
519 return err;
520 }
521 pmcdev->base_addr &= PMC_BASE_ADDR_MASK;
522 dev_dbg(&dev->dev, "PMC Core: PWRMBASE is %#x\n", pmcdev->base_addr);
523
524 pmcdev->regbase = devm_ioremap_nocache(ptr_dev,
525 pmcdev->base_addr,
526 SPT_PMC_MMIO_REG_LEN);
527 if (!pmcdev->regbase) {
528 dev_dbg(&dev->dev, "PMC Core: ioremap failed.\n");
529 return -ENOMEM;
530 }
531
532 mutex_init(&pmcdev->lock);
533 pmcdev->pmc_xram_read_bit = pmc_core_check_read_lock_bit();
534 pmcdev->map = map;
535
536 err = pmc_core_dbgfs_register(pmcdev);
537 if (err < 0)
538 dev_warn(&dev->dev, "PMC Core: debugfs register failed.\n");
539
540 pmc.has_slp_s0_res = true;
541 return 0;
542}
543
544static struct pci_driver intel_pmc_core_driver = {
545 .name = "intel_pmc_core",
546 .id_table = pmc_pci_ids,
547 .probe = pmc_core_probe,
548};
549
550builtin_pci_driver(intel_pmc_core_driver);
551
