LXR linux/drivers/platform/x86/intel_pmc

   1/*
   2 * Intel Core SoC Power Management Controller Header File
   3 *
   4 * Copyright (c) 2016, Intel Corporation.
   5 * All Rights Reserved.
   6 *
   7 * Authors: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
   8 *          Vishwanath Somayaji <vishwanath.somayaji@intel.com>
   9 *
  10 * This program is free software; you can redistribute it and/or modify it
  11 * under the terms and conditions of the GNU General Public License,
  12 * version 2, as published by the Free Software Foundation.
  13 *
  14 * This program is distributed in the hope it will be useful, but WITHOUT
  15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17 * more details.
  18 *
  19 */
  20
  21#ifndef PMC_CORE_H
  22#define PMC_CORE_H
  23
  24/* Sunrise Point Power Management Controller PCI Device ID */
  25#define SPT_PMC_PCI_DEVICE_ID                   0x9d21
  26
  27#define SPT_PMC_BASE_ADDR_OFFSET                0x48
  28#define SPT_PMC_SLP_S0_RES_COUNTER_OFFSET       0x13c
  29#define SPT_PMC_PM_CFG_OFFSET                   0x18
  30#define SPT_PMC_PM_STS_OFFSET                   0x1c
  31#define SPT_PMC_MTPMC_OFFSET                    0x20
  32#define SPT_PMC_MFPMC_OFFSET                    0x38
  33#define SPT_PMC_LTR_IGNORE_OFFSET               0x30C
  34#define SPT_PMC_MPHY_CORE_STS_0                 0x1143
  35#define SPT_PMC_MPHY_CORE_STS_1                 0x1142
  36#define SPT_PMC_MPHY_COM_STS_0                  0x1155
  37#define SPT_PMC_MMIO_REG_LEN                    0x1000
  38#define SPT_PMC_SLP_S0_RES_COUNTER_STEP         0x64
  39#define PMC_BASE_ADDR_MASK                      ~(SPT_PMC_MMIO_REG_LEN - 1)
  40#define MTPMC_MASK                              0xffff0000
  41#define NUM_ENTRIES                             5
  42#define SPT_PMC_READ_DISABLE_BIT                0x16
  43#define SPT_PMC_MSG_FULL_STS_BIT                0x18
  44#define NUM_RETRIES                             100
  45#define NUM_IP_IGN_ALLOWED                      17
  46
  47/* Sunrise Point: PGD PFET Enable Ack Status Registers */
  48enum ppfear_regs {
  49        SPT_PMC_XRAM_PPFEAR0A = 0x590,
  50        SPT_PMC_XRAM_PPFEAR0B,
  51        SPT_PMC_XRAM_PPFEAR0C,
  52        SPT_PMC_XRAM_PPFEAR0D,
  53        SPT_PMC_XRAM_PPFEAR1A,
  54};
  55
  56#define SPT_PMC_BIT_PMC                         BIT(0)
  57#define SPT_PMC_BIT_OPI                         BIT(1)
  58#define SPT_PMC_BIT_SPI                         BIT(2)
  59#define SPT_PMC_BIT_XHCI                        BIT(3)
  60#define SPT_PMC_BIT_SPA                         BIT(4)
  61#define SPT_PMC_BIT_SPB                         BIT(5)
  62#define SPT_PMC_BIT_SPC                         BIT(6)
  63#define SPT_PMC_BIT_GBE                         BIT(7)
  64
  65#define SPT_PMC_BIT_SATA                        BIT(0)
  66#define SPT_PMC_BIT_HDA_PGD0                    BIT(1)
  67#define SPT_PMC_BIT_HDA_PGD1                    BIT(2)
  68#define SPT_PMC_BIT_HDA_PGD2                    BIT(3)
  69#define SPT_PMC_BIT_HDA_PGD3                    BIT(4)
  70#define SPT_PMC_BIT_RSVD_0B                     BIT(5)
  71#define SPT_PMC_BIT_LPSS                        BIT(6)
  72#define SPT_PMC_BIT_LPC                         BIT(7)
  73
  74#define SPT_PMC_BIT_SMB                         BIT(0)
  75#define SPT_PMC_BIT_ISH                         BIT(1)
  76#define SPT_PMC_BIT_P2SB                        BIT(2)
  77#define SPT_PMC_BIT_DFX                         BIT(3)
  78#define SPT_PMC_BIT_SCC                         BIT(4)
  79#define SPT_PMC_BIT_RSVD_0C                     BIT(5)
  80#define SPT_PMC_BIT_FUSE                        BIT(6)
  81#define SPT_PMC_BIT_CAMREA                      BIT(7)
  82
  83#define SPT_PMC_BIT_RSVD_0D                     BIT(0)
  84#define SPT_PMC_BIT_USB3_OTG                    BIT(1)
  85#define SPT_PMC_BIT_EXI                         BIT(2)
  86#define SPT_PMC_BIT_CSE                         BIT(3)
  87#define SPT_PMC_BIT_CSME_KVM                    BIT(4)
  88#define SPT_PMC_BIT_CSME_PMT                    BIT(5)
  89#define SPT_PMC_BIT_CSME_CLINK                  BIT(6)
  90#define SPT_PMC_BIT_CSME_PTIO                   BIT(7)
  91
  92#define SPT_PMC_BIT_CSME_USBR                   BIT(0)
  93#define SPT_PMC_BIT_CSME_SUSRAM                 BIT(1)
  94#define SPT_PMC_BIT_CSME_SMT                    BIT(2)
  95#define SPT_PMC_BIT_RSVD_1A                     BIT(3)
  96#define SPT_PMC_BIT_CSME_SMS2                   BIT(4)
  97#define SPT_PMC_BIT_CSME_SMS1                   BIT(5)
  98#define SPT_PMC_BIT_CSME_RTC                    BIT(6)
  99#define SPT_PMC_BIT_CSME_PSF                    BIT(7)
 100
 101#define SPT_PMC_BIT_MPHY_LANE0                  BIT(0)
 102#define SPT_PMC_BIT_MPHY_LANE1                  BIT(1)
 103#define SPT_PMC_BIT_MPHY_LANE2                  BIT(2)
 104#define SPT_PMC_BIT_MPHY_LANE3                  BIT(3)
 105#define SPT_PMC_BIT_MPHY_LANE4                  BIT(4)
 106#define SPT_PMC_BIT_MPHY_LANE5                  BIT(5)
 107#define SPT_PMC_BIT_MPHY_LANE6                  BIT(6)
 108#define SPT_PMC_BIT_MPHY_LANE7                  BIT(7)
 109
 110#define SPT_PMC_BIT_MPHY_LANE8                  BIT(0)
 111#define SPT_PMC_BIT_MPHY_LANE9                  BIT(1)
 112#define SPT_PMC_BIT_MPHY_LANE10                 BIT(2)
 113#define SPT_PMC_BIT_MPHY_LANE11                 BIT(3)
 114#define SPT_PMC_BIT_MPHY_LANE12                 BIT(4)
 115#define SPT_PMC_BIT_MPHY_LANE13                 BIT(5)
 116#define SPT_PMC_BIT_MPHY_LANE14                 BIT(6)
 117#define SPT_PMC_BIT_MPHY_LANE15                 BIT(7)
 118
 119#define SPT_PMC_BIT_MPHY_CMN_LANE0              BIT(0)
 120#define SPT_PMC_BIT_MPHY_CMN_LANE1              BIT(1)
 121#define SPT_PMC_BIT_MPHY_CMN_LANE2              BIT(2)
 122#define SPT_PMC_BIT_MPHY_CMN_LANE3              BIT(3)
 123
 124struct pmc_bit_map {
 125        const char *name;
 126        u32 bit_mask;
 127};
 128
 129struct pmc_reg_map {
 130        const struct pmc_bit_map *pfear_sts;
 131        const struct pmc_bit_map *mphy_sts;
 132        const struct pmc_bit_map *pll_sts;
 133};
 134
 135/**
 136 * struct pmc_dev - pmc device structure
 137 * @base_addr:          comtains pmc base address
 138 * @regbase:            pointer to io-remapped memory location
 139 * @dbgfs_dir:          path to debug fs interface
 140 * @feature_available:  flag to indicate whether
 141 *                      the feature is available
 142 *                      on a particular platform or not.
 143 *
 144 * pmc_dev contains info about power management controller device.
 145 */
 146struct pmc_dev {
 147        u32 base_addr;
 148        void __iomem *regbase;
 149        const struct pmc_reg_map *map;
 150#if IS_ENABLED(CONFIG_DEBUG_FS)
 151        struct dentry *dbgfs_dir;
 152#endif /* CONFIG_DEBUG_FS */
 153        bool has_slp_s0_res;
 154        int pmc_xram_read_bit;
 155        struct mutex lock; /* generic mutex lock for PMC Core */
 156};
 157
 158#endif /* PMC_CORE_H */
 159