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21#include <linux/slab.h>
22#include <linux/device.h>
23#include <linux/module.h>
24#include <linux/mfd/syscon.h>
25#include <linux/err.h>
26#include <linux/io.h>
27#include <linux/platform_device.h>
28#include <linux/of.h>
29#include <linux/of_address.h>
30#include <linux/regmap.h>
31#include <linux/regulator/driver.h>
32#include <linux/regulator/of_regulator.h>
33#include <linux/regulator/machine.h>
34
35#define LDO_RAMP_UP_UNIT_IN_CYCLES 64
36#define LDO_RAMP_UP_FREQ_IN_MHZ 24
37
38#define LDO_POWER_GATE 0x00
39#define LDO_FET_FULL_ON 0x1f
40
41struct anatop_regulator {
42 u32 control_reg;
43 struct regmap *anatop;
44 int vol_bit_shift;
45 int vol_bit_width;
46 u32 delay_reg;
47 int delay_bit_shift;
48 int delay_bit_width;
49 int min_bit_val;
50 int min_voltage;
51 int max_voltage;
52 struct regulator_desc rdesc;
53 struct regulator_init_data *initdata;
54 bool bypass;
55 int sel;
56};
57
58static int anatop_regmap_set_voltage_time_sel(struct regulator_dev *reg,
59 unsigned int old_sel,
60 unsigned int new_sel)
61{
62 struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
63 u32 val;
64 int ret = 0;
65
66
67 if (anatop_reg->delay_bit_width && new_sel > old_sel) {
68
69
70
71
72
73
74 regmap_read(anatop_reg->anatop, anatop_reg->delay_reg, &val);
75 val = (val >> anatop_reg->delay_bit_shift) &
76 ((1 << anatop_reg->delay_bit_width) - 1);
77 ret = (new_sel - old_sel) * (LDO_RAMP_UP_UNIT_IN_CYCLES <<
78 val) / LDO_RAMP_UP_FREQ_IN_MHZ + 1;
79 }
80
81 return ret;
82}
83
84static int anatop_regmap_enable(struct regulator_dev *reg)
85{
86 struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
87 int sel;
88
89 sel = anatop_reg->bypass ? LDO_FET_FULL_ON : anatop_reg->sel;
90 return regulator_set_voltage_sel_regmap(reg, sel);
91}
92
93static int anatop_regmap_disable(struct regulator_dev *reg)
94{
95 return regulator_set_voltage_sel_regmap(reg, LDO_POWER_GATE);
96}
97
98static int anatop_regmap_is_enabled(struct regulator_dev *reg)
99{
100 return regulator_get_voltage_sel_regmap(reg) != LDO_POWER_GATE;
101}
102
103static int anatop_regmap_core_set_voltage_sel(struct regulator_dev *reg,
104 unsigned selector)
105{
106 struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
107 int ret;
108
109 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg)) {
110 anatop_reg->sel = selector;
111 return 0;
112 }
113
114 ret = regulator_set_voltage_sel_regmap(reg, selector);
115 if (!ret)
116 anatop_reg->sel = selector;
117 return ret;
118}
119
120static int anatop_regmap_core_get_voltage_sel(struct regulator_dev *reg)
121{
122 struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
123
124 if (anatop_reg->bypass || !anatop_regmap_is_enabled(reg))
125 return anatop_reg->sel;
126
127 return regulator_get_voltage_sel_regmap(reg);
128}
129
130static int anatop_regmap_get_bypass(struct regulator_dev *reg, bool *enable)
131{
132 struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
133 int sel;
134
135 sel = regulator_get_voltage_sel_regmap(reg);
136 if (sel == LDO_FET_FULL_ON)
137 WARN_ON(!anatop_reg->bypass);
138 else if (sel != LDO_POWER_GATE)
139 WARN_ON(anatop_reg->bypass);
140
141 *enable = anatop_reg->bypass;
142 return 0;
143}
144
145static int anatop_regmap_set_bypass(struct regulator_dev *reg, bool enable)
146{
147 struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
148 int sel;
149
150 if (enable == anatop_reg->bypass)
151 return 0;
152
153 sel = enable ? LDO_FET_FULL_ON : anatop_reg->sel;
154 anatop_reg->bypass = enable;
155
156 return regulator_set_voltage_sel_regmap(reg, sel);
157}
158
159static struct regulator_ops anatop_rops = {
160 .set_voltage_sel = regulator_set_voltage_sel_regmap,
161 .get_voltage_sel = regulator_get_voltage_sel_regmap,
162 .list_voltage = regulator_list_voltage_linear,
163 .map_voltage = regulator_map_voltage_linear,
164};
165
166static struct regulator_ops anatop_core_rops = {
167 .enable = anatop_regmap_enable,
168 .disable = anatop_regmap_disable,
169 .is_enabled = anatop_regmap_is_enabled,
170 .set_voltage_sel = anatop_regmap_core_set_voltage_sel,
171 .set_voltage_time_sel = anatop_regmap_set_voltage_time_sel,
172 .get_voltage_sel = anatop_regmap_core_get_voltage_sel,
173 .list_voltage = regulator_list_voltage_linear,
174 .map_voltage = regulator_map_voltage_linear,
175 .get_bypass = anatop_regmap_get_bypass,
176 .set_bypass = anatop_regmap_set_bypass,
177};
178
179static int anatop_regulator_probe(struct platform_device *pdev)
180{
181 struct device *dev = &pdev->dev;
182 struct device_node *np = dev->of_node;
183 struct device_node *anatop_np;
184 struct regulator_desc *rdesc;
185 struct regulator_dev *rdev;
186 struct anatop_regulator *sreg;
187 struct regulator_init_data *initdata;
188 struct regulator_config config = { };
189 int ret = 0;
190 u32 val;
191
192 sreg = devm_kzalloc(dev, sizeof(*sreg), GFP_KERNEL);
193 if (!sreg)
194 return -ENOMEM;
195
196 rdesc = &sreg->rdesc;
197 rdesc->type = REGULATOR_VOLTAGE;
198 rdesc->owner = THIS_MODULE;
199
200 of_property_read_string(np, "regulator-name", &rdesc->name);
201 if (!rdesc->name) {
202 dev_err(dev, "failed to get a regulator-name\n");
203 return -EINVAL;
204 }
205
206 initdata = of_get_regulator_init_data(dev, np, rdesc);
207 if (!initdata)
208 return -ENOMEM;
209
210 initdata->supply_regulator = "vin";
211 sreg->initdata = initdata;
212
213 anatop_np = of_get_parent(np);
214 if (!anatop_np)
215 return -ENODEV;
216 sreg->anatop = syscon_node_to_regmap(anatop_np);
217 of_node_put(anatop_np);
218 if (IS_ERR(sreg->anatop))
219 return PTR_ERR(sreg->anatop);
220
221 ret = of_property_read_u32(np, "anatop-reg-offset",
222 &sreg->control_reg);
223 if (ret) {
224 dev_err(dev, "no anatop-reg-offset property set\n");
225 return ret;
226 }
227 ret = of_property_read_u32(np, "anatop-vol-bit-width",
228 &sreg->vol_bit_width);
229 if (ret) {
230 dev_err(dev, "no anatop-vol-bit-width property set\n");
231 return ret;
232 }
233 ret = of_property_read_u32(np, "anatop-vol-bit-shift",
234 &sreg->vol_bit_shift);
235 if (ret) {
236 dev_err(dev, "no anatop-vol-bit-shift property set\n");
237 return ret;
238 }
239 ret = of_property_read_u32(np, "anatop-min-bit-val",
240 &sreg->min_bit_val);
241 if (ret) {
242 dev_err(dev, "no anatop-min-bit-val property set\n");
243 return ret;
244 }
245 ret = of_property_read_u32(np, "anatop-min-voltage",
246 &sreg->min_voltage);
247 if (ret) {
248 dev_err(dev, "no anatop-min-voltage property set\n");
249 return ret;
250 }
251 ret = of_property_read_u32(np, "anatop-max-voltage",
252 &sreg->max_voltage);
253 if (ret) {
254 dev_err(dev, "no anatop-max-voltage property set\n");
255 return ret;
256 }
257
258
259 of_property_read_u32(np, "anatop-delay-reg-offset",
260 &sreg->delay_reg);
261 of_property_read_u32(np, "anatop-delay-bit-width",
262 &sreg->delay_bit_width);
263 of_property_read_u32(np, "anatop-delay-bit-shift",
264 &sreg->delay_bit_shift);
265
266 rdesc->n_voltages = (sreg->max_voltage - sreg->min_voltage) / 25000 + 1
267 + sreg->min_bit_val;
268 rdesc->min_uV = sreg->min_voltage;
269 rdesc->uV_step = 25000;
270 rdesc->linear_min_sel = sreg->min_bit_val;
271 rdesc->vsel_reg = sreg->control_reg;
272 rdesc->vsel_mask = ((1 << sreg->vol_bit_width) - 1) <<
273 sreg->vol_bit_shift;
274 rdesc->min_dropout_uV = 125000;
275
276 config.dev = &pdev->dev;
277 config.init_data = initdata;
278 config.driver_data = sreg;
279 config.of_node = pdev->dev.of_node;
280 config.regmap = sreg->anatop;
281
282
283 if (sreg->control_reg && sreg->delay_bit_width) {
284 rdesc->ops = &anatop_core_rops;
285
286 ret = regmap_read(config.regmap, rdesc->vsel_reg, &val);
287 if (ret) {
288 dev_err(dev, "failed to read initial state\n");
289 return ret;
290 }
291
292 sreg->sel = (val & rdesc->vsel_mask) >> sreg->vol_bit_shift;
293 if (sreg->sel == LDO_FET_FULL_ON) {
294 sreg->sel = 0;
295 sreg->bypass = true;
296 }
297
298
299
300
301
302
303 if (!sreg->sel && !strcmp(rdesc->name, "vddpu"))
304 sreg->sel = 22;
305
306
307 if (!sreg->sel && !strcmp(rdesc->name, "vddpcie"))
308 sreg->sel = 0x10;
309
310 if (!sreg->bypass && !sreg->sel) {
311 dev_err(&pdev->dev, "Failed to read a valid default voltage selector.\n");
312 return -EINVAL;
313 }
314 } else {
315 u32 enable_bit;
316
317 rdesc->ops = &anatop_rops;
318
319 if (!of_property_read_u32(np, "anatop-enable-bit",
320 &enable_bit)) {
321 anatop_rops.enable = regulator_enable_regmap;
322 anatop_rops.disable = regulator_disable_regmap;
323 anatop_rops.is_enabled = regulator_is_enabled_regmap;
324
325 rdesc->enable_reg = sreg->control_reg;
326 rdesc->enable_mask = BIT(enable_bit);
327 }
328 }
329
330
331 rdev = devm_regulator_register(dev, rdesc, &config);
332 if (IS_ERR(rdev)) {
333 dev_err(dev, "failed to register %s\n",
334 rdesc->name);
335 return PTR_ERR(rdev);
336 }
337
338 platform_set_drvdata(pdev, rdev);
339
340 return 0;
341}
342
343static const struct of_device_id of_anatop_regulator_match_tbl[] = {
344 { .compatible = "fsl,anatop-regulator", },
345 { }
346};
347MODULE_DEVICE_TABLE(of, of_anatop_regulator_match_tbl);
348
349static struct platform_driver anatop_regulator_driver = {
350 .driver = {
351 .name = "anatop_regulator",
352 .of_match_table = of_anatop_regulator_match_tbl,
353 },
354 .probe = anatop_regulator_probe,
355};
356
357static int __init anatop_regulator_init(void)
358{
359 return platform_driver_register(&anatop_regulator_driver);
360}
361postcore_initcall(anatop_regulator_init);
362
363static void __exit anatop_regulator_exit(void)
364{
365 platform_driver_unregister(&anatop_regulator_driver);
366}
367module_exit(anatop_regulator_exit);
368
369MODULE_AUTHOR("Nancy Chen <Nancy.Chen@freescale.com>");
370MODULE_AUTHOR("Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>");
371MODULE_DESCRIPTION("ANATOP Regulator driver");
372MODULE_LICENSE("GPL v2");
373MODULE_ALIAS("platform:anatop_regulator");
374
