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164#include <asm/io.h>
165#include <asm/byteorder.h>
166#include <asm/page.h>
167#include <linux/stddef.h>
168#include <linux/string.h>
169#include <linux/errno.h>
170#include <linux/kernel.h>
171#include <linux/ioport.h>
172#include <linux/slab.h>
173#include <linux/delay.h>
174#include <linux/pci.h>
175#include <linux/proc_fs.h>
176#include <linux/reboot.h>
177#include <linux/interrupt.h>
178
179#include <linux/blkdev.h>
180#include <linux/types.h>
181#include <linux/dma-mapping.h>
182
183#include <scsi/sg.h>
184#include "scsi.h"
185#include <scsi/scsi_host.h>
186
187#include "ips.h"
188
189#include <linux/module.h>
190
191#include <linux/stat.h>
192
193#include <linux/spinlock.h>
194#include <linux/init.h>
195
196#include <linux/smp.h>
197
198#ifdef MODULE
199static char *ips = NULL;
200module_param(ips, charp, 0);
201#endif
202
203
204
205
206#define IPS_VERSION_HIGH IPS_VER_MAJOR_STRING "." IPS_VER_MINOR_STRING
207#define IPS_VERSION_LOW "." IPS_VER_BUILD_STRING " "
208
209#define IPS_DMA_DIR(scb) ((!scb->scsi_cmd || ips_is_passthru(scb->scsi_cmd) || \
210 DMA_NONE == scb->scsi_cmd->sc_data_direction) ? \
211 PCI_DMA_BIDIRECTIONAL : \
212 scb->scsi_cmd->sc_data_direction)
213
214#ifdef IPS_DEBUG
215#define METHOD_TRACE(s, i) if (ips_debug >= (i+10)) printk(KERN_NOTICE s "\n");
216#define DEBUG(i, s) if (ips_debug >= i) printk(KERN_NOTICE s "\n");
217#define DEBUG_VAR(i, s, v...) if (ips_debug >= i) printk(KERN_NOTICE s "\n", v);
218#else
219#define METHOD_TRACE(s, i)
220#define DEBUG(i, s)
221#define DEBUG_VAR(i, s, v...)
222#endif
223
224
225
226
227static int ips_detect(struct scsi_host_template *);
228static int ips_release(struct Scsi_Host *);
229static int ips_eh_abort(struct scsi_cmnd *);
230static int ips_eh_reset(struct scsi_cmnd *);
231static int ips_queue(struct Scsi_Host *, struct scsi_cmnd *);
232static const char *ips_info(struct Scsi_Host *);
233static irqreturn_t do_ipsintr(int, void *);
234static int ips_hainit(ips_ha_t *);
235static int ips_map_status(ips_ha_t *, ips_scb_t *, ips_stat_t *);
236static int ips_send_wait(ips_ha_t *, ips_scb_t *, int, int);
237static int ips_send_cmd(ips_ha_t *, ips_scb_t *);
238static int ips_online(ips_ha_t *, ips_scb_t *);
239static int ips_inquiry(ips_ha_t *, ips_scb_t *);
240static int ips_rdcap(ips_ha_t *, ips_scb_t *);
241static int ips_msense(ips_ha_t *, ips_scb_t *);
242static int ips_reqsen(ips_ha_t *, ips_scb_t *);
243static int ips_deallocatescbs(ips_ha_t *, int);
244static int ips_allocatescbs(ips_ha_t *);
245static int ips_reset_copperhead(ips_ha_t *);
246static int ips_reset_copperhead_memio(ips_ha_t *);
247static int ips_reset_morpheus(ips_ha_t *);
248static int ips_issue_copperhead(ips_ha_t *, ips_scb_t *);
249static int ips_issue_copperhead_memio(ips_ha_t *, ips_scb_t *);
250static int ips_issue_i2o(ips_ha_t *, ips_scb_t *);
251static int ips_issue_i2o_memio(ips_ha_t *, ips_scb_t *);
252static int ips_isintr_copperhead(ips_ha_t *);
253static int ips_isintr_copperhead_memio(ips_ha_t *);
254static int ips_isintr_morpheus(ips_ha_t *);
255static int ips_wait(ips_ha_t *, int, int);
256static int ips_write_driver_status(ips_ha_t *, int);
257static int ips_read_adapter_status(ips_ha_t *, int);
258static int ips_read_subsystem_parameters(ips_ha_t *, int);
259static int ips_read_config(ips_ha_t *, int);
260static int ips_clear_adapter(ips_ha_t *, int);
261static int ips_readwrite_page5(ips_ha_t *, int, int);
262static int ips_init_copperhead(ips_ha_t *);
263static int ips_init_copperhead_memio(ips_ha_t *);
264static int ips_init_morpheus(ips_ha_t *);
265static int ips_isinit_copperhead(ips_ha_t *);
266static int ips_isinit_copperhead_memio(ips_ha_t *);
267static int ips_isinit_morpheus(ips_ha_t *);
268static int ips_erase_bios(ips_ha_t *);
269static int ips_program_bios(ips_ha_t *, char *, uint32_t, uint32_t);
270static int ips_verify_bios(ips_ha_t *, char *, uint32_t, uint32_t);
271static int ips_erase_bios_memio(ips_ha_t *);
272static int ips_program_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
273static int ips_verify_bios_memio(ips_ha_t *, char *, uint32_t, uint32_t);
274static int ips_flash_copperhead(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
275static int ips_flash_bios(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
276static int ips_flash_firmware(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
277static void ips_free_flash_copperhead(ips_ha_t * ha);
278static void ips_get_bios_version(ips_ha_t *, int);
279static void ips_identify_controller(ips_ha_t *);
280static void ips_chkstatus(ips_ha_t *, IPS_STATUS *);
281static void ips_enable_int_copperhead(ips_ha_t *);
282static void ips_enable_int_copperhead_memio(ips_ha_t *);
283static void ips_enable_int_morpheus(ips_ha_t *);
284static int ips_intr_copperhead(ips_ha_t *);
285static int ips_intr_morpheus(ips_ha_t *);
286static void ips_next(ips_ha_t *, int);
287static void ipsintr_blocking(ips_ha_t *, struct ips_scb *);
288static void ipsintr_done(ips_ha_t *, struct ips_scb *);
289static void ips_done(ips_ha_t *, ips_scb_t *);
290static void ips_free(ips_ha_t *);
291static void ips_init_scb(ips_ha_t *, ips_scb_t *);
292static void ips_freescb(ips_ha_t *, ips_scb_t *);
293static void ips_setup_funclist(ips_ha_t *);
294static void ips_statinit(ips_ha_t *);
295static void ips_statinit_memio(ips_ha_t *);
296static void ips_fix_ffdc_time(ips_ha_t *, ips_scb_t *, time_t);
297static void ips_ffdc_reset(ips_ha_t *, int);
298static void ips_ffdc_time(ips_ha_t *);
299static uint32_t ips_statupd_copperhead(ips_ha_t *);
300static uint32_t ips_statupd_copperhead_memio(ips_ha_t *);
301static uint32_t ips_statupd_morpheus(ips_ha_t *);
302static ips_scb_t *ips_getscb(ips_ha_t *);
303static void ips_putq_scb_head(ips_scb_queue_t *, ips_scb_t *);
304static void ips_putq_wait_tail(ips_wait_queue_entry_t *, struct scsi_cmnd *);
305static void ips_putq_copp_tail(ips_copp_queue_t *,
306 ips_copp_wait_item_t *);
307static ips_scb_t *ips_removeq_scb_head(ips_scb_queue_t *);
308static ips_scb_t *ips_removeq_scb(ips_scb_queue_t *, ips_scb_t *);
309static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_entry_t *);
310static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_entry_t *,
311 struct scsi_cmnd *);
312static ips_copp_wait_item_t *ips_removeq_copp(ips_copp_queue_t *,
313 ips_copp_wait_item_t *);
314static ips_copp_wait_item_t *ips_removeq_copp_head(ips_copp_queue_t *);
315
316static int ips_is_passthru(struct scsi_cmnd *);
317static int ips_make_passthru(ips_ha_t *, struct scsi_cmnd *, ips_scb_t *, int);
318static int ips_usrcmd(ips_ha_t *, ips_passthru_t *, ips_scb_t *);
319static void ips_cleanup_passthru(ips_ha_t *, ips_scb_t *);
320static void ips_scmd_buf_write(struct scsi_cmnd * scmd, void *data,
321 unsigned int count);
322static void ips_scmd_buf_read(struct scsi_cmnd * scmd, void *data,
323 unsigned int count);
324
325static int ips_write_info(struct Scsi_Host *, char *, int);
326static int ips_show_info(struct seq_file *, struct Scsi_Host *);
327static int ips_host_info(ips_ha_t *, struct seq_file *);
328static int ips_abort_init(ips_ha_t * ha, int index);
329static int ips_init_phase2(int index);
330
331static int ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr);
332static int ips_register_scsi(int index);
333
334static int ips_poll_for_flush_complete(ips_ha_t * ha);
335static void ips_flush_and_reset(ips_ha_t *ha);
336
337
338
339
340static const char ips_name[] = "ips";
341static struct Scsi_Host *ips_sh[IPS_MAX_ADAPTERS];
342static ips_ha_t *ips_ha[IPS_MAX_ADAPTERS];
343static unsigned int ips_next_controller;
344static unsigned int ips_num_controllers;
345static unsigned int ips_released_controllers;
346static int ips_hotplug;
347static int ips_cmd_timeout = 60;
348static int ips_reset_timeout = 60 * 5;
349static int ips_force_memio = 1;
350static int ips_force_i2o = 1;
351static int ips_ioctlsize = IPS_IOCTL_SIZE;
352static int ips_cd_boot;
353static char *ips_FlashData = NULL;
354static dma_addr_t ips_flashbusaddr;
355static long ips_FlashDataInUse;
356static uint32_t MaxLiteCmds = 32;
357static struct scsi_host_template ips_driver_template = {
358 .detect = ips_detect,
359 .release = ips_release,
360 .info = ips_info,
361 .queuecommand = ips_queue,
362 .eh_abort_handler = ips_eh_abort,
363 .eh_host_reset_handler = ips_eh_reset,
364 .proc_name = "ips",
365 .show_info = ips_show_info,
366 .write_info = ips_write_info,
367 .slave_configure = ips_slave_configure,
368 .bios_param = ips_biosparam,
369 .this_id = -1,
370 .sg_tablesize = IPS_MAX_SG,
371 .cmd_per_lun = 3,
372 .use_clustering = ENABLE_CLUSTERING,
373 .no_write_same = 1,
374};
375
376
377
378static struct pci_device_id ips_pci_table[] = {
379 { 0x1014, 0x002E, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
380 { 0x1014, 0x01BD, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
381 { 0x9005, 0x0250, PCI_ANY_ID, PCI_ANY_ID, 0, 0 },
382 { 0, }
383};
384
385MODULE_DEVICE_TABLE( pci, ips_pci_table );
386
387static char ips_hot_plug_name[] = "ips";
388
389static int ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent);
390static void ips_remove_device(struct pci_dev *pci_dev);
391
392static struct pci_driver ips_pci_driver = {
393 .name = ips_hot_plug_name,
394 .id_table = ips_pci_table,
395 .probe = ips_insert_device,
396 .remove = ips_remove_device,
397};
398
399
400
401
402
403static int ips_halt(struct notifier_block *nb, ulong event, void *buf);
404
405#define MAX_ADAPTER_NAME 15
406
407static char ips_adapter_name[][30] = {
408 "ServeRAID",
409 "ServeRAID II",
410 "ServeRAID on motherboard",
411 "ServeRAID on motherboard",
412 "ServeRAID 3H",
413 "ServeRAID 3L",
414 "ServeRAID 4H",
415 "ServeRAID 4M",
416 "ServeRAID 4L",
417 "ServeRAID 4Mx",
418 "ServeRAID 4Lx",
419 "ServeRAID 5i",
420 "ServeRAID 5i",
421 "ServeRAID 6M",
422 "ServeRAID 6i",
423 "ServeRAID 7t",
424 "ServeRAID 7k",
425 "ServeRAID 7M"
426};
427
428static struct notifier_block ips_notifier = {
429 ips_halt, NULL, 0
430};
431
432
433
434
435static char ips_command_direction[] = {
436 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT,
437 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK,
438 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
439 IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
440 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_OUT,
441 IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_OUT,
442 IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_IN,
443 IPS_DATA_UNK, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
444 IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_UNK,
445 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
446 IPS_DATA_OUT, IPS_DATA_NONE, IPS_DATA_IN, IPS_DATA_NONE, IPS_DATA_NONE,
447 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT,
448 IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_OUT,
449 IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_IN, IPS_DATA_NONE,
450 IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK,
451 IPS_DATA_NONE, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK,
452 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
453 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
454 IPS_DATA_IN, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
455 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
456 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
457 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
458 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
459 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
460 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
461 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
462 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
463 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
464 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
465 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
466 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
467 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
468 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
469 IPS_DATA_NONE, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_NONE,
470 IPS_DATA_OUT, IPS_DATA_UNK, IPS_DATA_NONE, IPS_DATA_UNK, IPS_DATA_OUT,
471 IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_OUT, IPS_DATA_NONE,
472 IPS_DATA_UNK, IPS_DATA_IN, IPS_DATA_OUT, IPS_DATA_IN, IPS_DATA_IN,
473 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
474 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
475 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
476 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
477 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
478 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
479 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
480 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
481 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
482 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_OUT,
483 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
484 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
485 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK,
486 IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK, IPS_DATA_UNK
487};
488
489
490
491
492
493
494
495
496
497
498
499static int
500ips_setup(char *ips_str)
501{
502
503 int i;
504 char *key;
505 char *value;
506 IPS_OPTION options[] = {
507 {"noi2o", &ips_force_i2o, 0},
508 {"nommap", &ips_force_memio, 0},
509 {"ioctlsize", &ips_ioctlsize, IPS_IOCTL_SIZE},
510 {"cdboot", &ips_cd_boot, 0},
511 {"maxcmds", &MaxLiteCmds, 32},
512 };
513
514
515
516 while ((key = strsep(&ips_str, ",."))) {
517 if (!*key)
518 continue;
519 value = strchr(key, ':');
520 if (value)
521 *value++ = '\0';
522
523
524
525
526 for (i = 0; i < ARRAY_SIZE(options); i++) {
527 if (strncasecmp
528 (key, options[i].option_name,
529 strlen(options[i].option_name)) == 0) {
530 if (value)
531 *options[i].option_flag =
532 simple_strtoul(value, NULL, 0);
533 else
534 *options[i].option_flag =
535 options[i].option_value;
536 break;
537 }
538 }
539 }
540
541 return (1);
542}
543
544__setup("ips=", ips_setup);
545
546
547
548
549
550
551
552
553
554
555
556
557static int
558ips_detect(struct scsi_host_template * SHT)
559{
560 int i;
561
562 METHOD_TRACE("ips_detect", 1);
563
564#ifdef MODULE
565 if (ips)
566 ips_setup(ips);
567#endif
568
569 for (i = 0; i < ips_num_controllers; i++) {
570 if (ips_register_scsi(i))
571 ips_free(ips_ha[i]);
572 ips_released_controllers++;
573 }
574 ips_hotplug = 1;
575 return (ips_num_controllers);
576}
577
578
579
580
581
582static void
583ips_setup_funclist(ips_ha_t * ha)
584{
585
586
587
588
589 if (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha)) {
590
591 ha->func.isintr = ips_isintr_morpheus;
592 ha->func.isinit = ips_isinit_morpheus;
593 ha->func.issue = ips_issue_i2o_memio;
594 ha->func.init = ips_init_morpheus;
595 ha->func.statupd = ips_statupd_morpheus;
596 ha->func.reset = ips_reset_morpheus;
597 ha->func.intr = ips_intr_morpheus;
598 ha->func.enableint = ips_enable_int_morpheus;
599 } else if (IPS_USE_MEMIO(ha)) {
600
601 ha->func.isintr = ips_isintr_copperhead_memio;
602 ha->func.isinit = ips_isinit_copperhead_memio;
603 ha->func.init = ips_init_copperhead_memio;
604 ha->func.statupd = ips_statupd_copperhead_memio;
605 ha->func.statinit = ips_statinit_memio;
606 ha->func.reset = ips_reset_copperhead_memio;
607 ha->func.intr = ips_intr_copperhead;
608 ha->func.erasebios = ips_erase_bios_memio;
609 ha->func.programbios = ips_program_bios_memio;
610 ha->func.verifybios = ips_verify_bios_memio;
611 ha->func.enableint = ips_enable_int_copperhead_memio;
612 if (IPS_USE_I2O_DELIVER(ha))
613 ha->func.issue = ips_issue_i2o_memio;
614 else
615 ha->func.issue = ips_issue_copperhead_memio;
616 } else {
617
618 ha->func.isintr = ips_isintr_copperhead;
619 ha->func.isinit = ips_isinit_copperhead;
620 ha->func.init = ips_init_copperhead;
621 ha->func.statupd = ips_statupd_copperhead;
622 ha->func.statinit = ips_statinit;
623 ha->func.reset = ips_reset_copperhead;
624 ha->func.intr = ips_intr_copperhead;
625 ha->func.erasebios = ips_erase_bios;
626 ha->func.programbios = ips_program_bios;
627 ha->func.verifybios = ips_verify_bios;
628 ha->func.enableint = ips_enable_int_copperhead;
629
630 if (IPS_USE_I2O_DELIVER(ha))
631 ha->func.issue = ips_issue_i2o;
632 else
633 ha->func.issue = ips_issue_copperhead;
634 }
635}
636
637
638
639
640
641
642
643
644
645
646static int
647ips_release(struct Scsi_Host *sh)
648{
649 ips_scb_t *scb;
650 ips_ha_t *ha;
651 int i;
652
653 METHOD_TRACE("ips_release", 1);
654
655 scsi_remove_host(sh);
656
657 for (i = 0; i < IPS_MAX_ADAPTERS && ips_sh[i] != sh; i++) ;
658
659 if (i == IPS_MAX_ADAPTERS) {
660 printk(KERN_WARNING
661 "(%s) release, invalid Scsi_Host pointer.\n", ips_name);
662 BUG();
663 return (FALSE);
664 }
665
666 ha = IPS_HA(sh);
667
668 if (!ha)
669 return (FALSE);
670
671
672 scb = &ha->scbs[ha->max_cmds - 1];
673
674 ips_init_scb(ha, scb);
675
676 scb->timeout = ips_cmd_timeout;
677 scb->cdb[0] = IPS_CMD_FLUSH;
678
679 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
680 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
681 scb->cmd.flush_cache.state = IPS_NORM_STATE;
682 scb->cmd.flush_cache.reserved = 0;
683 scb->cmd.flush_cache.reserved2 = 0;
684 scb->cmd.flush_cache.reserved3 = 0;
685 scb->cmd.flush_cache.reserved4 = 0;
686
687 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
688
689
690 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) == IPS_FAILURE)
691 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Incomplete Flush.\n");
692
693 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Complete.\n");
694
695 ips_sh[i] = NULL;
696 ips_ha[i] = NULL;
697
698
699 ips_free(ha);
700
701
702 free_irq(ha->pcidev->irq, ha);
703
704 scsi_host_put(sh);
705
706 ips_released_controllers++;
707
708 return (FALSE);
709}
710
711
712
713
714
715
716
717
718
719
720static int
721ips_halt(struct notifier_block *nb, ulong event, void *buf)
722{
723 ips_scb_t *scb;
724 ips_ha_t *ha;
725 int i;
726
727 if ((event != SYS_RESTART) && (event != SYS_HALT) &&
728 (event != SYS_POWER_OFF))
729 return (NOTIFY_DONE);
730
731 for (i = 0; i < ips_next_controller; i++) {
732 ha = (ips_ha_t *) ips_ha[i];
733
734 if (!ha)
735 continue;
736
737 if (!ha->active)
738 continue;
739
740
741 scb = &ha->scbs[ha->max_cmds - 1];
742
743 ips_init_scb(ha, scb);
744
745 scb->timeout = ips_cmd_timeout;
746 scb->cdb[0] = IPS_CMD_FLUSH;
747
748 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
749 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
750 scb->cmd.flush_cache.state = IPS_NORM_STATE;
751 scb->cmd.flush_cache.reserved = 0;
752 scb->cmd.flush_cache.reserved2 = 0;
753 scb->cmd.flush_cache.reserved3 = 0;
754 scb->cmd.flush_cache.reserved4 = 0;
755
756 IPS_PRINTK(KERN_WARNING, ha->pcidev, "Flushing Cache.\n");
757
758
759 if (ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_ON) ==
760 IPS_FAILURE)
761 IPS_PRINTK(KERN_WARNING, ha->pcidev,
762 "Incomplete Flush.\n");
763 else
764 IPS_PRINTK(KERN_WARNING, ha->pcidev,
765 "Flushing Complete.\n");
766 }
767
768 return (NOTIFY_OK);
769}
770
771
772
773
774
775
776
777
778
779
780int ips_eh_abort(struct scsi_cmnd *SC)
781{
782 ips_ha_t *ha;
783 ips_copp_wait_item_t *item;
784 int ret;
785 struct Scsi_Host *host;
786
787 METHOD_TRACE("ips_eh_abort", 1);
788
789 if (!SC)
790 return (FAILED);
791
792 host = SC->device->host;
793 ha = (ips_ha_t *) SC->device->host->hostdata;
794
795 if (!ha)
796 return (FAILED);
797
798 if (!ha->active)
799 return (FAILED);
800
801 spin_lock(host->host_lock);
802
803
804 item = ha->copp_waitlist.head;
805 while ((item) && (item->scsi_cmd != SC))
806 item = item->next;
807
808 if (item) {
809
810 ips_removeq_copp(&ha->copp_waitlist, item);
811 ret = (SUCCESS);
812
813
814 } else if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
815
816 ret = (SUCCESS);
817 } else {
818
819 ret = (FAILED);
820 }
821
822 spin_unlock(host->host_lock);
823 return ret;
824}
825
826
827
828
829
830
831
832
833
834
835
836
837static int __ips_eh_reset(struct scsi_cmnd *SC)
838{
839 int ret;
840 int i;
841 ips_ha_t *ha;
842 ips_scb_t *scb;
843 ips_copp_wait_item_t *item;
844
845 METHOD_TRACE("ips_eh_reset", 1);
846
847#ifdef NO_IPS_RESET
848 return (FAILED);
849#else
850
851 if (!SC) {
852 DEBUG(1, "Reset called with NULL scsi command");
853
854 return (FAILED);
855 }
856
857 ha = (ips_ha_t *) SC->device->host->hostdata;
858
859 if (!ha) {
860 DEBUG(1, "Reset called with NULL ha struct");
861
862 return (FAILED);
863 }
864
865 if (!ha->active)
866 return (FAILED);
867
868
869 item = ha->copp_waitlist.head;
870 while ((item) && (item->scsi_cmd != SC))
871 item = item->next;
872
873 if (item) {
874
875 ips_removeq_copp(&ha->copp_waitlist, item);
876 return (SUCCESS);
877 }
878
879
880 if (ips_removeq_wait(&ha->scb_waitlist, SC)) {
881
882 return (SUCCESS);
883 }
884
885
886
887
888
889
890
891
892
893
894
895 if (ha->ioctl_reset == 0) {
896 scb = &ha->scbs[ha->max_cmds - 1];
897
898 ips_init_scb(ha, scb);
899
900 scb->timeout = ips_cmd_timeout;
901 scb->cdb[0] = IPS_CMD_FLUSH;
902
903 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
904 scb->cmd.flush_cache.command_id = IPS_COMMAND_ID(ha, scb);
905 scb->cmd.flush_cache.state = IPS_NORM_STATE;
906 scb->cmd.flush_cache.reserved = 0;
907 scb->cmd.flush_cache.reserved2 = 0;
908 scb->cmd.flush_cache.reserved3 = 0;
909 scb->cmd.flush_cache.reserved4 = 0;
910
911
912 ret = ips_send_wait(ha, scb, ips_cmd_timeout, IPS_INTR_IORL);
913 if (ret == IPS_SUCCESS) {
914 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
915 "Reset Request - Flushed Cache\n");
916 return (SUCCESS);
917 }
918 }
919
920
921
922
923 ha->ioctl_reset = 0;
924
925
926
927
928
929 IPS_PRINTK(KERN_NOTICE, ha->pcidev, "Resetting controller.\n");
930 ret = (*ha->func.reset) (ha);
931
932 if (!ret) {
933 struct scsi_cmnd *scsi_cmd;
934
935 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
936 "Controller reset failed - controller now offline.\n");
937
938
939 DEBUG_VAR(1, "(%s%d) Failing active commands",
940 ips_name, ha->host_num);
941
942 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
943 scb->scsi_cmd->result = DID_ERROR << 16;
944 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
945 ips_freescb(ha, scb);
946 }
947
948
949 DEBUG_VAR(1, "(%s%d) Failing pending commands",
950 ips_name, ha->host_num);
951
952 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
953 scsi_cmd->result = DID_ERROR;
954 scsi_cmd->scsi_done(scsi_cmd);
955 }
956
957 ha->active = FALSE;
958 return (FAILED);
959 }
960
961 if (!ips_clear_adapter(ha, IPS_INTR_IORL)) {
962 struct scsi_cmnd *scsi_cmd;
963
964 IPS_PRINTK(KERN_NOTICE, ha->pcidev,
965 "Controller reset failed - controller now offline.\n");
966
967
968 DEBUG_VAR(1, "(%s%d) Failing active commands",
969 ips_name, ha->host_num);
970
971 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
972 scb->scsi_cmd->result = DID_ERROR << 16;
973 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
974 ips_freescb(ha, scb);
975 }
976
977
978 DEBUG_VAR(1, "(%s%d) Failing pending commands",
979 ips_name, ha->host_num);
980
981 while ((scsi_cmd = ips_removeq_wait_head(&ha->scb_waitlist))) {
982 scsi_cmd->result = DID_ERROR << 16;
983 scsi_cmd->scsi_done(scsi_cmd);
984 }
985
986 ha->active = FALSE;
987 return (FAILED);
988 }
989
990
991 if (le32_to_cpu(ha->subsys->param[3]) & 0x300000) {
992 struct timeval tv;
993
994 do_gettimeofday(&tv);
995 ha->last_ffdc = tv.tv_sec;
996 ha->reset_count++;
997 ips_ffdc_reset(ha, IPS_INTR_IORL);
998 }
999
1000
1001 DEBUG_VAR(1, "(%s%d) Failing active commands", ips_name, ha->host_num);
1002
1003 while ((scb = ips_removeq_scb_head(&ha->scb_activelist))) {
1004 scb->scsi_cmd->result = DID_RESET << 16;
1005 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
1006 ips_freescb(ha, scb);
1007 }
1008
1009
1010 for (i = 1; i < ha->nbus; i++)
1011 ha->dcdb_active[i - 1] = 0;
1012
1013
1014 ha->num_ioctl = 0;
1015
1016 ips_next(ha, IPS_INTR_IORL);
1017
1018 return (SUCCESS);
1019#endif
1020
1021}
1022
1023static int ips_eh_reset(struct scsi_cmnd *SC)
1024{
1025 int rc;
1026
1027 spin_lock_irq(SC->device->host->host_lock);
1028 rc = __ips_eh_reset(SC);
1029 spin_unlock_irq(SC->device->host->host_lock);
1030
1031 return rc;
1032}
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046static int ips_queue_lck(struct scsi_cmnd *SC, void (*done) (struct scsi_cmnd *))
1047{
1048 ips_ha_t *ha;
1049 ips_passthru_t *pt;
1050
1051 METHOD_TRACE("ips_queue", 1);
1052
1053 ha = (ips_ha_t *) SC->device->host->hostdata;
1054
1055 if (!ha)
1056 return (1);
1057
1058 if (!ha->active)
1059 return (DID_ERROR);
1060
1061 if (ips_is_passthru(SC)) {
1062 if (ha->copp_waitlist.count == IPS_MAX_IOCTL_QUEUE) {
1063 SC->result = DID_BUS_BUSY << 16;
1064 done(SC);
1065
1066 return (0);
1067 }
1068 } else if (ha->scb_waitlist.count == IPS_MAX_QUEUE) {
1069 SC->result = DID_BUS_BUSY << 16;
1070 done(SC);
1071
1072 return (0);
1073 }
1074
1075 SC->scsi_done = done;
1076
1077 DEBUG_VAR(2, "(%s%d): ips_queue: cmd 0x%X (%d %d %d)",
1078 ips_name,
1079 ha->host_num,
1080 SC->cmnd[0],
1081 SC->device->channel, SC->device->id, SC->device->lun);
1082
1083
1084 if ((scmd_channel(SC) > 0)
1085 && (scmd_id(SC) == ha->ha_id[scmd_channel(SC)])) {
1086 SC->result = DID_NO_CONNECT << 16;
1087 done(SC);
1088
1089 return (0);
1090 }
1091
1092 if (ips_is_passthru(SC)) {
1093
1094 ips_copp_wait_item_t *scratch;
1095
1096
1097
1098
1099 pt = (ips_passthru_t *) scsi_sglist(SC);
1100 if ((pt->CoppCP.cmd.reset.op_code == IPS_CMD_RESET_CHANNEL) &&
1101 (pt->CoppCP.cmd.reset.adapter_flag == 1)) {
1102 if (ha->scb_activelist.count != 0) {
1103 SC->result = DID_BUS_BUSY << 16;
1104 done(SC);
1105 return (0);
1106 }
1107 ha->ioctl_reset = 1;
1108 __ips_eh_reset(SC);
1109 SC->result = DID_OK << 16;
1110 SC->scsi_done(SC);
1111 return (0);
1112 }
1113
1114
1115 scratch = kmalloc(sizeof (ips_copp_wait_item_t), GFP_ATOMIC);
1116
1117 if (!scratch) {
1118 SC->result = DID_ERROR << 16;
1119 done(SC);
1120
1121 return (0);
1122 }
1123
1124 scratch->scsi_cmd = SC;
1125 scratch->next = NULL;
1126
1127 ips_putq_copp_tail(&ha->copp_waitlist, scratch);
1128 } else {
1129 ips_putq_wait_tail(&ha->scb_waitlist, SC);
1130 }
1131
1132 ips_next(ha, IPS_INTR_IORL);
1133
1134 return (0);
1135}
1136
1137static DEF_SCSI_QCMD(ips_queue)
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev,
1149 sector_t capacity, int geom[])
1150{
1151 ips_ha_t *ha = (ips_ha_t *) sdev->host->hostdata;
1152 int heads;
1153 int sectors;
1154 int cylinders;
1155
1156 METHOD_TRACE("ips_biosparam", 1);
1157
1158 if (!ha)
1159
1160 return (0);
1161
1162 if (!ha->active)
1163 return (0);
1164
1165 if (!ips_read_adapter_status(ha, IPS_INTR_ON))
1166
1167 return (0);
1168
1169 if ((capacity > 0x400000) && ((ha->enq->ucMiscFlag & 0x8) == 0)) {
1170 heads = IPS_NORM_HEADS;
1171 sectors = IPS_NORM_SECTORS;
1172 } else {
1173 heads = IPS_COMP_HEADS;
1174 sectors = IPS_COMP_SECTORS;
1175 }
1176
1177 cylinders = (unsigned long) capacity / (heads * sectors);
1178
1179 DEBUG_VAR(2, "Geometry: heads: %d, sectors: %d, cylinders: %d",
1180 heads, sectors, cylinders);
1181
1182 geom[0] = heads;
1183 geom[1] = sectors;
1184 geom[2] = cylinders;
1185
1186 return (0);
1187}
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198static int
1199ips_slave_configure(struct scsi_device * SDptr)
1200{
1201 ips_ha_t *ha;
1202 int min;
1203
1204 ha = IPS_HA(SDptr->host);
1205 if (SDptr->tagged_supported && SDptr->type == TYPE_DISK) {
1206 min = ha->max_cmds / 2;
1207 if (ha->enq->ucLogDriveCount <= 2)
1208 min = ha->max_cmds - 1;
1209 scsi_change_queue_depth(SDptr, min);
1210 }
1211
1212 SDptr->skip_ms_page_8 = 1;
1213 SDptr->skip_ms_page_3f = 1;
1214 return 0;
1215}
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226static irqreturn_t
1227do_ipsintr(int irq, void *dev_id)
1228{
1229 ips_ha_t *ha;
1230 struct Scsi_Host *host;
1231 int irqstatus;
1232
1233 METHOD_TRACE("do_ipsintr", 2);
1234
1235 ha = (ips_ha_t *) dev_id;
1236 if (!ha)
1237 return IRQ_NONE;
1238 host = ips_sh[ha->host_num];
1239
1240 if (!host) {
1241 (*ha->func.intr) (ha);
1242 return IRQ_HANDLED;
1243 }
1244
1245 spin_lock(host->host_lock);
1246
1247 if (!ha->active) {
1248 spin_unlock(host->host_lock);
1249 return IRQ_HANDLED;
1250 }
1251
1252 irqstatus = (*ha->func.intr) (ha);
1253
1254 spin_unlock(host->host_lock);
1255
1256
1257 ips_next(ha, IPS_INTR_ON);
1258 return IRQ_RETVAL(irqstatus);
1259}
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272int
1273ips_intr_copperhead(ips_ha_t * ha)
1274{
1275 ips_stat_t *sp;
1276 ips_scb_t *scb;
1277 IPS_STATUS cstatus;
1278 int intrstatus;
1279
1280 METHOD_TRACE("ips_intr", 2);
1281
1282 if (!ha)
1283 return 0;
1284
1285 if (!ha->active)
1286 return 0;
1287
1288 intrstatus = (*ha->func.isintr) (ha);
1289
1290 if (!intrstatus) {
1291
1292
1293
1294
1295 return 0;
1296 }
1297
1298 while (TRUE) {
1299 sp = &ha->sp;
1300
1301 intrstatus = (*ha->func.isintr) (ha);
1302
1303 if (!intrstatus)
1304 break;
1305 else
1306 cstatus.value = (*ha->func.statupd) (ha);
1307
1308 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1309
1310 continue;
1311 }
1312
1313 ips_chkstatus(ha, &cstatus);
1314 scb = (ips_scb_t *) sp->scb_addr;
1315
1316
1317
1318
1319
1320 (*scb->callback) (ha, scb);
1321 }
1322 return 1;
1323}
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336int
1337ips_intr_morpheus(ips_ha_t * ha)
1338{
1339 ips_stat_t *sp;
1340 ips_scb_t *scb;
1341 IPS_STATUS cstatus;
1342 int intrstatus;
1343
1344 METHOD_TRACE("ips_intr_morpheus", 2);
1345
1346 if (!ha)
1347 return 0;
1348
1349 if (!ha->active)
1350 return 0;
1351
1352 intrstatus = (*ha->func.isintr) (ha);
1353
1354 if (!intrstatus) {
1355
1356
1357
1358
1359 return 0;
1360 }
1361
1362 while (TRUE) {
1363 sp = &ha->sp;
1364
1365 intrstatus = (*ha->func.isintr) (ha);
1366
1367 if (!intrstatus)
1368 break;
1369 else
1370 cstatus.value = (*ha->func.statupd) (ha);
1371
1372 if (cstatus.value == 0xffffffff)
1373
1374 break;
1375
1376 if (cstatus.fields.command_id > (IPS_MAX_CMDS - 1)) {
1377 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1378 "Spurious interrupt; no ccb.\n");
1379
1380 continue;
1381 }
1382
1383 ips_chkstatus(ha, &cstatus);
1384 scb = (ips_scb_t *) sp->scb_addr;
1385
1386
1387
1388
1389
1390 (*scb->callback) (ha, scb);
1391 }
1392 return 1;
1393}
1394
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404static const char *
1405ips_info(struct Scsi_Host *SH)
1406{
1407 static char buffer[256];
1408 char *bp;
1409 ips_ha_t *ha;
1410
1411 METHOD_TRACE("ips_info", 1);
1412
1413 ha = IPS_HA(SH);
1414
1415 if (!ha)
1416 return (NULL);
1417
1418 bp = &buffer[0];
1419 memset(bp, 0, sizeof (buffer));
1420
1421 sprintf(bp, "%s%s%s Build %d", "IBM PCI ServeRAID ",
1422 IPS_VERSION_HIGH, IPS_VERSION_LOW, IPS_BUILD_IDENT);
1423
1424 if (ha->ad_type > 0 && ha->ad_type <= MAX_ADAPTER_NAME) {
1425 strcat(bp, " <");
1426 strcat(bp, ips_adapter_name[ha->ad_type - 1]);
1427 strcat(bp, ">");
1428 }
1429
1430 return (bp);
1431}
1432
1433static int
1434ips_write_info(struct Scsi_Host *host, char *buffer, int length)
1435{
1436 int i;
1437 ips_ha_t *ha = NULL;
1438
1439
1440 for (i = 0; i < ips_next_controller; i++) {
1441 if (ips_sh[i]) {
1442 if (ips_sh[i] == host) {
1443 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1444 break;
1445 }
1446 }
1447 }
1448
1449 if (!ha)
1450 return (-EINVAL);
1451
1452 return 0;
1453}
1454
1455static int
1456ips_show_info(struct seq_file *m, struct Scsi_Host *host)
1457{
1458 int i;
1459 ips_ha_t *ha = NULL;
1460
1461
1462 for (i = 0; i < ips_next_controller; i++) {
1463 if (ips_sh[i]) {
1464 if (ips_sh[i] == host) {
1465 ha = (ips_ha_t *) ips_sh[i]->hostdata;
1466 break;
1467 }
1468 }
1469 }
1470
1471 if (!ha)
1472 return (-EINVAL);
1473
1474 return ips_host_info(ha, m);
1475}
1476
1477
1478
1479
1480
1481
1482
1483
1484
1485
1486
1487
1488
1489
1490static int ips_is_passthru(struct scsi_cmnd *SC)
1491{
1492 unsigned long flags;
1493
1494 METHOD_TRACE("ips_is_passthru", 1);
1495
1496 if (!SC)
1497 return (0);
1498
1499 if ((SC->cmnd[0] == IPS_IOCTL_COMMAND) &&
1500 (SC->device->channel == 0) &&
1501 (SC->device->id == IPS_ADAPTER_ID) &&
1502 (SC->device->lun == 0) && scsi_sglist(SC)) {
1503 struct scatterlist *sg = scsi_sglist(SC);
1504 char *buffer;
1505
1506
1507
1508 local_irq_save(flags);
1509 buffer = kmap_atomic(sg_page(sg)) + sg->offset;
1510 if (buffer && buffer[0] == 'C' && buffer[1] == 'O' &&
1511 buffer[2] == 'P' && buffer[3] == 'P') {
1512 kunmap_atomic(buffer - sg->offset);
1513 local_irq_restore(flags);
1514 return 1;
1515 }
1516 kunmap_atomic(buffer - sg->offset);
1517 local_irq_restore(flags);
1518 }
1519 return 0;
1520}
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530static int
1531ips_alloc_passthru_buffer(ips_ha_t * ha, int length)
1532{
1533 void *bigger_buf;
1534 dma_addr_t dma_busaddr;
1535
1536 if (ha->ioctl_data && length <= ha->ioctl_len)
1537 return 0;
1538
1539 bigger_buf = pci_alloc_consistent(ha->pcidev, length, &dma_busaddr);
1540 if (bigger_buf) {
1541
1542 pci_free_consistent(ha->pcidev, ha->ioctl_len, ha->ioctl_data,
1543 ha->ioctl_busaddr);
1544
1545 ha->ioctl_data = (char *) bigger_buf;
1546 ha->ioctl_len = length;
1547 ha->ioctl_busaddr = dma_busaddr;
1548 } else {
1549 return -1;
1550 }
1551 return 0;
1552}
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563static int
1564ips_make_passthru(ips_ha_t *ha, struct scsi_cmnd *SC, ips_scb_t *scb, int intr)
1565{
1566 ips_passthru_t *pt;
1567 int length = 0;
1568 int i, ret;
1569 struct scatterlist *sg = scsi_sglist(SC);
1570
1571 METHOD_TRACE("ips_make_passthru", 1);
1572
1573 scsi_for_each_sg(SC, sg, scsi_sg_count(SC), i)
1574 length += sg->length;
1575
1576 if (length < sizeof (ips_passthru_t)) {
1577
1578 DEBUG_VAR(1, "(%s%d) Passthru structure wrong size",
1579 ips_name, ha->host_num);
1580 return (IPS_FAILURE);
1581 }
1582 if (ips_alloc_passthru_buffer(ha, length)) {
1583
1584
1585 if (ha->ioctl_data) {
1586 pt = (ips_passthru_t *) ha->ioctl_data;
1587 ips_scmd_buf_read(SC, pt, sizeof (ips_passthru_t));
1588 pt->BasicStatus = 0x0B;
1589 pt->ExtendedStatus = 0x00;
1590 ips_scmd_buf_write(SC, pt, sizeof (ips_passthru_t));
1591 }
1592 return IPS_FAILURE;
1593 }
1594 ha->ioctl_datasize = length;
1595
1596 ips_scmd_buf_read(SC, ha->ioctl_data, ha->ioctl_datasize);
1597 pt = (ips_passthru_t *) ha->ioctl_data;
1598
1599
1600
1601
1602
1603
1604
1605
1606
1607
1608
1609 switch (pt->CoppCmd) {
1610 case IPS_NUMCTRLS:
1611 memcpy(ha->ioctl_data + sizeof (ips_passthru_t),
1612 &ips_num_controllers, sizeof (int));
1613 ips_scmd_buf_write(SC, ha->ioctl_data,
1614 sizeof (ips_passthru_t) + sizeof (int));
1615 SC->result = DID_OK << 16;
1616
1617 return (IPS_SUCCESS_IMM);
1618
1619 case IPS_COPPUSRCMD:
1620 case IPS_COPPIOCCMD:
1621 if (SC->cmnd[0] == IPS_IOCTL_COMMAND) {
1622 if (length < (sizeof (ips_passthru_t) + pt->CmdBSize)) {
1623
1624 DEBUG_VAR(1,
1625 "(%s%d) Passthru structure wrong size",
1626 ips_name, ha->host_num);
1627
1628 return (IPS_FAILURE);
1629 }
1630
1631 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD &&
1632 pt->CoppCP.cmd.flashfw.op_code ==
1633 IPS_CMD_RW_BIOSFW) {
1634 ret = ips_flash_copperhead(ha, pt, scb);
1635 ips_scmd_buf_write(SC, ha->ioctl_data,
1636 sizeof (ips_passthru_t));
1637 return ret;
1638 }
1639 if (ips_usrcmd(ha, pt, scb))
1640 return (IPS_SUCCESS);
1641 else
1642 return (IPS_FAILURE);
1643 }
1644
1645 break;
1646
1647 }
1648
1649 return (IPS_FAILURE);
1650}
1651
1652
1653
1654
1655
1656
1657static int
1658ips_flash_copperhead(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1659{
1660 int datasize;
1661
1662
1663
1664 if (IPS_IS_TROMBONE(ha) && pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE) {
1665 if (ips_usrcmd(ha, pt, scb))
1666 return IPS_SUCCESS;
1667 else
1668 return IPS_FAILURE;
1669 }
1670 pt->BasicStatus = 0x0B;
1671 pt->ExtendedStatus = 0;
1672 scb->scsi_cmd->result = DID_OK << 16;
1673
1674
1675 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1676 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1677 pt->BasicStatus = 0;
1678 return ips_flash_bios(ha, pt, scb);
1679 } else if (pt->CoppCP.cmd.flashfw.packet_num == 0) {
1680 if (ips_FlashData && !test_and_set_bit(0, &ips_FlashDataInUse)){
1681 ha->flash_data = ips_FlashData;
1682 ha->flash_busaddr = ips_flashbusaddr;
1683 ha->flash_len = PAGE_SIZE << 7;
1684 ha->flash_datasize = 0;
1685 } else if (!ha->flash_data) {
1686 datasize = pt->CoppCP.cmd.flashfw.total_packets *
1687 pt->CoppCP.cmd.flashfw.count;
1688 ha->flash_data = pci_alloc_consistent(ha->pcidev,
1689 datasize,
1690 &ha->flash_busaddr);
1691 if (!ha->flash_data){
1692 printk(KERN_WARNING "Unable to allocate a flash buffer\n");
1693 return IPS_FAILURE;
1694 }
1695 ha->flash_datasize = 0;
1696 ha->flash_len = datasize;
1697 } else
1698 return IPS_FAILURE;
1699 } else {
1700 if (pt->CoppCP.cmd.flashfw.count + ha->flash_datasize >
1701 ha->flash_len) {
1702 ips_free_flash_copperhead(ha);
1703 IPS_PRINTK(KERN_WARNING, ha->pcidev,
1704 "failed size sanity check\n");
1705 return IPS_FAILURE;
1706 }
1707 }
1708 if (!ha->flash_data)
1709 return IPS_FAILURE;
1710 pt->BasicStatus = 0;
1711 memcpy(&ha->flash_data[ha->flash_datasize], pt + 1,
1712 pt->CoppCP.cmd.flashfw.count);
1713 ha->flash_datasize += pt->CoppCP.cmd.flashfw.count;
1714 if (pt->CoppCP.cmd.flashfw.packet_num ==
1715 pt->CoppCP.cmd.flashfw.total_packets - 1) {
1716 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE)
1717 return ips_flash_bios(ha, pt, scb);
1718 else if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE)
1719 return ips_flash_firmware(ha, pt, scb);
1720 }
1721 return IPS_SUCCESS_IMM;
1722}
1723
1724
1725
1726
1727
1728
1729static int
1730ips_flash_bios(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1731{
1732
1733 if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1734 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_BIOS) {
1735 if ((!ha->func.programbios) || (!ha->func.erasebios) ||
1736 (!ha->func.verifybios))
1737 goto error;
1738 if ((*ha->func.erasebios) (ha)) {
1739 DEBUG_VAR(1,
1740 "(%s%d) flash bios failed - unable to erase flash",
1741 ips_name, ha->host_num);
1742 goto error;
1743 } else
1744 if ((*ha->func.programbios) (ha,
1745 ha->flash_data +
1746 IPS_BIOS_HEADER,
1747 ha->flash_datasize -
1748 IPS_BIOS_HEADER, 0)) {
1749 DEBUG_VAR(1,
1750 "(%s%d) flash bios failed - unable to flash",
1751 ips_name, ha->host_num);
1752 goto error;
1753 } else
1754 if ((*ha->func.verifybios) (ha,
1755 ha->flash_data +
1756 IPS_BIOS_HEADER,
1757 ha->flash_datasize -
1758 IPS_BIOS_HEADER, 0)) {
1759 DEBUG_VAR(1,
1760 "(%s%d) flash bios failed - unable to verify flash",
1761 ips_name, ha->host_num);
1762 goto error;
1763 }
1764 ips_free_flash_copperhead(ha);
1765 return IPS_SUCCESS_IMM;
1766 } else if (pt->CoppCP.cmd.flashfw.type == IPS_BIOS_IMAGE &&
1767 pt->CoppCP.cmd.flashfw.direction == IPS_ERASE_BIOS) {
1768 if (!ha->func.erasebios)
1769 goto error;
1770 if ((*ha->func.erasebios) (ha)) {
1771 DEBUG_VAR(1,
1772 "(%s%d) flash bios failed - unable to erase flash",
1773 ips_name, ha->host_num);
1774 goto error;
1775 }
1776 return IPS_SUCCESS_IMM;
1777 }
1778 error:
1779 pt->BasicStatus = 0x0B;
1780 pt->ExtendedStatus = 0x00;
1781 ips_free_flash_copperhead(ha);
1782 return IPS_FAILURE;
1783}
1784
1785
1786
1787
1788
1789
1790
1791
1792
1793static int
1794ips_fill_scb_sg_single(ips_ha_t * ha, dma_addr_t busaddr,
1795 ips_scb_t * scb, int indx, unsigned int e_len)
1796{
1797
1798 int ret_val = 0;
1799
1800 if ((scb->data_len + e_len) > ha->max_xfer) {
1801 e_len = ha->max_xfer - scb->data_len;
1802 scb->breakup = indx;
1803 ++scb->sg_break;
1804 ret_val = -1;
1805 } else {
1806 scb->breakup = 0;
1807 scb->sg_break = 0;
1808 }
1809 if (IPS_USE_ENH_SGLIST(ha)) {
1810 scb->sg_list.enh_list[indx].address_lo =
1811 cpu_to_le32(pci_dma_lo32(busaddr));
1812 scb->sg_list.enh_list[indx].address_hi =
1813 cpu_to_le32(pci_dma_hi32(busaddr));
1814 scb->sg_list.enh_list[indx].length = cpu_to_le32(e_len);
1815 } else {
1816 scb->sg_list.std_list[indx].address =
1817 cpu_to_le32(pci_dma_lo32(busaddr));
1818 scb->sg_list.std_list[indx].length = cpu_to_le32(e_len);
1819 }
1820
1821 ++scb->sg_len;
1822 scb->data_len += e_len;
1823 return ret_val;
1824}
1825
1826
1827
1828
1829
1830
1831static int
1832ips_flash_firmware(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1833{
1834 IPS_SG_LIST sg_list;
1835 uint32_t cmd_busaddr;
1836
1837 if (pt->CoppCP.cmd.flashfw.type == IPS_FW_IMAGE &&
1838 pt->CoppCP.cmd.flashfw.direction == IPS_WRITE_FW) {
1839 memset(&pt->CoppCP.cmd, 0, sizeof (IPS_HOST_COMMAND));
1840 pt->CoppCP.cmd.flashfw.op_code = IPS_CMD_DOWNLOAD;
1841 pt->CoppCP.cmd.flashfw.count = cpu_to_le32(ha->flash_datasize);
1842 } else {
1843 pt->BasicStatus = 0x0B;
1844 pt->ExtendedStatus = 0x00;
1845 ips_free_flash_copperhead(ha);
1846 return IPS_FAILURE;
1847 }
1848
1849 sg_list.list = scb->sg_list.list;
1850 cmd_busaddr = scb->scb_busaddr;
1851
1852 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1853
1854 scb->sg_list.list = sg_list.list;
1855 scb->scb_busaddr = cmd_busaddr;
1856 scb->bus = scb->scsi_cmd->device->channel;
1857 scb->target_id = scb->scsi_cmd->device->id;
1858 scb->lun = scb->scsi_cmd->device->lun;
1859 scb->sg_len = 0;
1860 scb->data_len = 0;
1861 scb->flags = 0;
1862 scb->op_code = 0;
1863 scb->callback = ipsintr_done;
1864 scb->timeout = ips_cmd_timeout;
1865
1866 scb->data_len = ha->flash_datasize;
1867 scb->data_busaddr =
1868 pci_map_single(ha->pcidev, ha->flash_data, scb->data_len,
1869 IPS_DMA_DIR(scb));
1870 scb->flags |= IPS_SCB_MAP_SINGLE;
1871 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
1872 scb->cmd.flashfw.buffer_addr = cpu_to_le32(scb->data_busaddr);
1873 if (pt->TimeOut)
1874 scb->timeout = pt->TimeOut;
1875 scb->scsi_cmd->result = DID_OK << 16;
1876 return IPS_SUCCESS;
1877}
1878
1879
1880
1881
1882
1883
1884static void
1885ips_free_flash_copperhead(ips_ha_t * ha)
1886{
1887 if (ha->flash_data == ips_FlashData)
1888 test_and_clear_bit(0, &ips_FlashDataInUse);
1889 else if (ha->flash_data)
1890 pci_free_consistent(ha->pcidev, ha->flash_len, ha->flash_data,
1891 ha->flash_busaddr);
1892 ha->flash_data = NULL;
1893}
1894
1895
1896
1897
1898
1899
1900
1901
1902
1903
1904static int
1905ips_usrcmd(ips_ha_t * ha, ips_passthru_t * pt, ips_scb_t * scb)
1906{
1907 IPS_SG_LIST sg_list;
1908 uint32_t cmd_busaddr;
1909
1910 METHOD_TRACE("ips_usrcmd", 1);
1911
1912 if ((!scb) || (!pt) || (!ha))
1913 return (0);
1914
1915
1916 sg_list.list = scb->sg_list.list;
1917 cmd_busaddr = scb->scb_busaddr;
1918
1919 memcpy(&scb->cmd, &pt->CoppCP.cmd, sizeof (IPS_IOCTL_CMD));
1920 memcpy(&scb->dcdb, &pt->CoppCP.dcdb, sizeof (IPS_DCDB_TABLE));
1921
1922
1923 scb->sg_list.list = sg_list.list;
1924 scb->scb_busaddr = cmd_busaddr;
1925 scb->bus = scb->scsi_cmd->device->channel;
1926 scb->target_id = scb->scsi_cmd->device->id;
1927 scb->lun = scb->scsi_cmd->device->lun;
1928 scb->sg_len = 0;
1929 scb->data_len = 0;
1930 scb->flags = 0;
1931 scb->op_code = 0;
1932 scb->callback = ipsintr_done;
1933 scb->timeout = ips_cmd_timeout;
1934 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
1935
1936
1937 if ((scb->cmd.basic_io.op_code == IPS_CMD_READ_SG) ||
1938 (scb->cmd.basic_io.op_code == IPS_CMD_WRITE_SG) ||
1939 (scb->cmd.basic_io.op_code == IPS_CMD_DCDB_SG))
1940 return (0);
1941
1942 if (pt->CmdBSize) {
1943 scb->data_len = pt->CmdBSize;
1944 scb->data_busaddr = ha->ioctl_busaddr + sizeof (ips_passthru_t);
1945 } else {
1946 scb->data_busaddr = 0L;
1947 }
1948
1949 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
1950 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
1951 (unsigned long) &scb->
1952 dcdb -
1953 (unsigned long) scb);
1954
1955 if (pt->CmdBSize) {
1956 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
1957 scb->dcdb.buffer_pointer =
1958 cpu_to_le32(scb->data_busaddr);
1959 else
1960 scb->cmd.basic_io.sg_addr =
1961 cpu_to_le32(scb->data_busaddr);
1962 }
1963
1964
1965 if (pt->TimeOut) {
1966 scb->timeout = pt->TimeOut;
1967
1968 if (pt->TimeOut <= 10)
1969 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10;
1970 else if (pt->TimeOut <= 60)
1971 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60;
1972 else
1973 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M;
1974 }
1975
1976
1977 scb->scsi_cmd->result = DID_OK << 16;
1978
1979
1980 return (1);
1981}
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992static void
1993ips_cleanup_passthru(ips_ha_t * ha, ips_scb_t * scb)
1994{
1995 ips_passthru_t *pt;
1996
1997 METHOD_TRACE("ips_cleanup_passthru", 1);
1998
1999 if ((!scb) || (!scb->scsi_cmd) || (!scsi_sglist(scb->scsi_cmd))) {
2000 DEBUG_VAR(1, "(%s%d) couldn't cleanup after passthru",
2001 ips_name, ha->host_num);
2002
2003 return;
2004 }
2005 pt = (ips_passthru_t *) ha->ioctl_data;
2006
2007
2008 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB)
2009 memcpy(&pt->CoppCP.dcdb, &scb->dcdb, sizeof (IPS_DCDB_TABLE));
2010
2011 pt->BasicStatus = scb->basic_status;
2012 pt->ExtendedStatus = scb->extended_status;
2013 pt->AdapterType = ha->ad_type;
2014
2015 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD &&
2016 (scb->cmd.flashfw.op_code == IPS_CMD_DOWNLOAD ||
2017 scb->cmd.flashfw.op_code == IPS_CMD_RW_BIOSFW))
2018 ips_free_flash_copperhead(ha);
2019
2020 ips_scmd_buf_write(scb->scsi_cmd, ha->ioctl_data, ha->ioctl_datasize);
2021}
2022
2023
2024
2025
2026
2027
2028
2029
2030
2031
2032static int
2033ips_host_info(ips_ha_t *ha, struct seq_file *m)
2034{
2035 METHOD_TRACE("ips_host_info", 1);
2036
2037 seq_puts(m, "\nIBM ServeRAID General Information:\n\n");
2038
2039 if ((le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) &&
2040 (le16_to_cpu(ha->nvram->adapter_type) != 0))
2041 seq_printf(m, "\tController Type : %s\n",
2042 ips_adapter_name[ha->ad_type - 1]);
2043 else
2044 seq_puts(m, "\tController Type : Unknown\n");
2045
2046 if (ha->io_addr)
2047 seq_printf(m,
2048 "\tIO region : 0x%x (%d bytes)\n",
2049 ha->io_addr, ha->io_len);
2050
2051 if (ha->mem_addr) {
2052 seq_printf(m,
2053 "\tMemory region : 0x%x (%d bytes)\n",
2054 ha->mem_addr, ha->mem_len);
2055 seq_printf(m,
2056 "\tShared memory address : 0x%lx\n",
2057 (unsigned long)ha->mem_ptr);
2058 }
2059
2060 seq_printf(m, "\tIRQ number : %d\n", ha->pcidev->irq);
2061
2062
2063
2064
2065 if (le32_to_cpu(ha->nvram->signature) == IPS_NVRAM_P5_SIG) {
2066 if (ha->nvram->bios_low[3] == 0) {
2067 seq_printf(m,
2068 "\tBIOS Version : %c%c%c%c%c%c%c\n",
2069 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2070 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2071 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2072 ha->nvram->bios_low[2]);
2073
2074 } else {
2075 seq_printf(m,
2076 "\tBIOS Version : %c%c%c%c%c%c%c%c\n",
2077 ha->nvram->bios_high[0], ha->nvram->bios_high[1],
2078 ha->nvram->bios_high[2], ha->nvram->bios_high[3],
2079 ha->nvram->bios_low[0], ha->nvram->bios_low[1],
2080 ha->nvram->bios_low[2], ha->nvram->bios_low[3]);
2081 }
2082
2083 }
2084
2085 if (ha->enq->CodeBlkVersion[7] == 0) {
2086 seq_printf(m,
2087 "\tFirmware Version : %c%c%c%c%c%c%c\n",
2088 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2089 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2090 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2091 ha->enq->CodeBlkVersion[6]);
2092 } else {
2093 seq_printf(m,
2094 "\tFirmware Version : %c%c%c%c%c%c%c%c\n",
2095 ha->enq->CodeBlkVersion[0], ha->enq->CodeBlkVersion[1],
2096 ha->enq->CodeBlkVersion[2], ha->enq->CodeBlkVersion[3],
2097 ha->enq->CodeBlkVersion[4], ha->enq->CodeBlkVersion[5],
2098 ha->enq->CodeBlkVersion[6], ha->enq->CodeBlkVersion[7]);
2099 }
2100
2101 if (ha->enq->BootBlkVersion[7] == 0) {
2102 seq_printf(m,
2103 "\tBoot Block Version : %c%c%c%c%c%c%c\n",
2104 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2105 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2106 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2107 ha->enq->BootBlkVersion[6]);
2108 } else {
2109 seq_printf(m,
2110 "\tBoot Block Version : %c%c%c%c%c%c%c%c\n",
2111 ha->enq->BootBlkVersion[0], ha->enq->BootBlkVersion[1],
2112 ha->enq->BootBlkVersion[2], ha->enq->BootBlkVersion[3],
2113 ha->enq->BootBlkVersion[4], ha->enq->BootBlkVersion[5],
2114 ha->enq->BootBlkVersion[6], ha->enq->BootBlkVersion[7]);
2115 }
2116
2117 seq_printf(m, "\tDriver Version : %s%s\n",
2118 IPS_VERSION_HIGH, IPS_VERSION_LOW);
2119
2120 seq_printf(m, "\tDriver Build : %d\n",
2121 IPS_BUILD_IDENT);
2122
2123 seq_printf(m, "\tMax Physical Devices : %d\n",
2124 ha->enq->ucMaxPhysicalDevices);
2125 seq_printf(m, "\tMax Active Commands : %d\n",
2126 ha->max_cmds);
2127 seq_printf(m, "\tCurrent Queued Commands : %d\n",
2128 ha->scb_waitlist.count);
2129 seq_printf(m, "\tCurrent Active Commands : %d\n",
2130 ha->scb_activelist.count - ha->num_ioctl);
2131 seq_printf(m, "\tCurrent Queued PT Commands : %d\n",
2132 ha->copp_waitlist.count);
2133 seq_printf(m, "\tCurrent Active PT Commands : %d\n",
2134 ha->num_ioctl);
2135
2136 seq_putc(m, '\n');
2137
2138 return 0;
2139}
2140
2141
2142
2143
2144
2145
2146
2147
2148
2149
2150static void
2151ips_identify_controller(ips_ha_t * ha)
2152{
2153 METHOD_TRACE("ips_identify_controller", 1);
2154
2155 switch (ha->pcidev->device) {
2156 case IPS_DEVICEID_COPPERHEAD:
2157 if (ha->pcidev->revision <= IPS_REVID_SERVERAID) {
2158 ha->ad_type = IPS_ADTYPE_SERVERAID;
2159 } else if (ha->pcidev->revision == IPS_REVID_SERVERAID2) {
2160 ha->ad_type = IPS_ADTYPE_SERVERAID2;
2161 } else if (ha->pcidev->revision == IPS_REVID_NAVAJO) {
2162 ha->ad_type = IPS_ADTYPE_NAVAJO;
2163 } else if ((ha->pcidev->revision == IPS_REVID_SERVERAID2)
2164 && (ha->slot_num == 0)) {
2165 ha->ad_type = IPS_ADTYPE_KIOWA;
2166 } else if ((ha->pcidev->revision >= IPS_REVID_CLARINETP1) &&
2167 (ha->pcidev->revision <= IPS_REVID_CLARINETP3)) {
2168 if (ha->enq->ucMaxPhysicalDevices == 15)
2169 ha->ad_type = IPS_ADTYPE_SERVERAID3L;
2170 else
2171 ha->ad_type = IPS_ADTYPE_SERVERAID3;
2172 } else if ((ha->pcidev->revision >= IPS_REVID_TROMBONE32) &&
2173 (ha->pcidev->revision <= IPS_REVID_TROMBONE64)) {
2174 ha->ad_type = IPS_ADTYPE_SERVERAID4H;
2175 }
2176 break;
2177
2178 case IPS_DEVICEID_MORPHEUS:
2179 switch (ha->pcidev->subsystem_device) {
2180 case IPS_SUBDEVICEID_4L:
2181 ha->ad_type = IPS_ADTYPE_SERVERAID4L;
2182 break;
2183
2184 case IPS_SUBDEVICEID_4M:
2185 ha->ad_type = IPS_ADTYPE_SERVERAID4M;
2186 break;
2187
2188 case IPS_SUBDEVICEID_4MX:
2189 ha->ad_type = IPS_ADTYPE_SERVERAID4MX;
2190 break;
2191
2192 case IPS_SUBDEVICEID_4LX:
2193 ha->ad_type = IPS_ADTYPE_SERVERAID4LX;
2194 break;
2195
2196 case IPS_SUBDEVICEID_5I2:
2197 ha->ad_type = IPS_ADTYPE_SERVERAID5I2;
2198 break;
2199
2200 case IPS_SUBDEVICEID_5I1:
2201 ha->ad_type = IPS_ADTYPE_SERVERAID5I1;
2202 break;
2203 }
2204
2205 break;
2206
2207 case IPS_DEVICEID_MARCO:
2208 switch (ha->pcidev->subsystem_device) {
2209 case IPS_SUBDEVICEID_6M:
2210 ha->ad_type = IPS_ADTYPE_SERVERAID6M;
2211 break;
2212 case IPS_SUBDEVICEID_6I:
2213 ha->ad_type = IPS_ADTYPE_SERVERAID6I;
2214 break;
2215 case IPS_SUBDEVICEID_7k:
2216 ha->ad_type = IPS_ADTYPE_SERVERAID7k;
2217 break;
2218 case IPS_SUBDEVICEID_7M:
2219 ha->ad_type = IPS_ADTYPE_SERVERAID7M;
2220 break;
2221 }
2222 break;
2223 }
2224}
2225
2226
2227
2228
2229
2230
2231
2232
2233
2234
2235static void
2236ips_get_bios_version(ips_ha_t * ha, int intr)
2237{
2238 ips_scb_t *scb;
2239 int ret;
2240 uint8_t major;
2241 uint8_t minor;
2242 uint8_t subminor;
2243 uint8_t *buffer;
2244
2245 METHOD_TRACE("ips_get_bios_version", 1);
2246
2247 major = 0;
2248 minor = 0;
2249
2250 strncpy(ha->bios_version, " ?", 8);
2251
2252 if (ha->pcidev->device == IPS_DEVICEID_COPPERHEAD) {
2253 if (IPS_USE_MEMIO(ha)) {
2254
2255
2256
2257 writel(0, ha->mem_ptr + IPS_REG_FLAP);
2258 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2259 udelay(25);
2260
2261 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
2262 return;
2263
2264 writel(1, ha->mem_ptr + IPS_REG_FLAP);
2265 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2266 udelay(25);
2267
2268 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
2269 return;
2270
2271
2272 writel(0x1FF, ha->mem_ptr + IPS_REG_FLAP);
2273 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2274 udelay(25);
2275
2276 major = readb(ha->mem_ptr + IPS_REG_FLDP);
2277
2278
2279 writel(0x1FE, ha->mem_ptr + IPS_REG_FLAP);
2280 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2281 udelay(25);
2282 minor = readb(ha->mem_ptr + IPS_REG_FLDP);
2283
2284
2285 writel(0x1FD, ha->mem_ptr + IPS_REG_FLAP);
2286 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2287 udelay(25);
2288 subminor = readb(ha->mem_ptr + IPS_REG_FLDP);
2289
2290 } else {
2291
2292
2293
2294 outl(0, ha->io_addr + IPS_REG_FLAP);
2295 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2296 udelay(25);
2297
2298 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
2299 return;
2300
2301 outl(1, ha->io_addr + IPS_REG_FLAP);
2302 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2303 udelay(25);
2304
2305 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
2306 return;
2307
2308
2309 outl(0x1FF, ha->io_addr + IPS_REG_FLAP);
2310 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2311 udelay(25);
2312
2313 major = inb(ha->io_addr + IPS_REG_FLDP);
2314
2315
2316 outl(0x1FE, ha->io_addr + IPS_REG_FLAP);
2317 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2318 udelay(25);
2319
2320 minor = inb(ha->io_addr + IPS_REG_FLDP);
2321
2322
2323 outl(0x1FD, ha->io_addr + IPS_REG_FLAP);
2324 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
2325 udelay(25);
2326
2327 subminor = inb(ha->io_addr + IPS_REG_FLDP);
2328
2329 }
2330 } else {
2331
2332
2333 buffer = ha->ioctl_data;
2334
2335 memset(buffer, 0, 0x1000);
2336
2337 scb = &ha->scbs[ha->max_cmds - 1];
2338
2339 ips_init_scb(ha, scb);
2340
2341 scb->timeout = ips_cmd_timeout;
2342 scb->cdb[0] = IPS_CMD_RW_BIOSFW;
2343
2344 scb->cmd.flashfw.op_code = IPS_CMD_RW_BIOSFW;
2345 scb->cmd.flashfw.command_id = IPS_COMMAND_ID(ha, scb);
2346 scb->cmd.flashfw.type = 1;
2347 scb->cmd.flashfw.direction = 0;
2348 scb->cmd.flashfw.count = cpu_to_le32(0x800);
2349 scb->cmd.flashfw.total_packets = 1;
2350 scb->cmd.flashfw.packet_num = 0;
2351 scb->data_len = 0x1000;
2352 scb->cmd.flashfw.buffer_addr = ha->ioctl_busaddr;
2353
2354
2355 if (((ret =
2356 ips_send_wait(ha, scb, ips_cmd_timeout,
2357 intr)) == IPS_FAILURE)
2358 || (ret == IPS_SUCCESS_IMM)
2359 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
2360
2361
2362 return;
2363 }
2364
2365 if ((buffer[0xC0] == 0x55) && (buffer[0xC1] == 0xAA)) {
2366 major = buffer[0x1ff + 0xC0];
2367 minor = buffer[0x1fe + 0xC0];
2368 subminor = buffer[0x1fd + 0xC0];
2369 } else {
2370 return;
2371 }
2372 }
2373
2374 ha->bios_version[0] = hex_asc_upper_hi(major);
2375 ha->bios_version[1] = '.';
2376 ha->bios_version[2] = hex_asc_upper_lo(major);
2377 ha->bios_version[3] = hex_asc_upper_lo(subminor);
2378 ha->bios_version[4] = '.';
2379 ha->bios_version[5] = hex_asc_upper_hi(minor);
2380 ha->bios_version[6] = hex_asc_upper_lo(minor);
2381 ha->bios_version[7] = 0;
2382}
2383
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395static int
2396ips_hainit(ips_ha_t * ha)
2397{
2398 int i;
2399 struct timeval tv;
2400
2401 METHOD_TRACE("ips_hainit", 1);
2402
2403 if (!ha)
2404 return (0);
2405
2406 if (ha->func.statinit)
2407 (*ha->func.statinit) (ha);
2408
2409 if (ha->func.enableint)
2410 (*ha->func.enableint) (ha);
2411
2412
2413 ha->reset_count = 1;
2414 do_gettimeofday(&tv);
2415 ha->last_ffdc = tv.tv_sec;
2416 ips_ffdc_reset(ha, IPS_INTR_IORL);
2417
2418 if (!ips_read_config(ha, IPS_INTR_IORL)) {
2419 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2420 "unable to read config from controller.\n");
2421
2422 return (0);
2423 }
2424
2425 if (!ips_read_adapter_status(ha, IPS_INTR_IORL)) {
2426 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2427 "unable to read controller status.\n");
2428
2429 return (0);
2430 }
2431
2432
2433 ips_identify_controller(ha);
2434
2435 if (!ips_read_subsystem_parameters(ha, IPS_INTR_IORL)) {
2436 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2437 "unable to read subsystem parameters.\n");
2438
2439 return (0);
2440 }
2441
2442
2443 if (!ips_write_driver_status(ha, IPS_INTR_IORL)) {
2444 IPS_PRINTK(KERN_WARNING, ha->pcidev,
2445 "unable to write driver info to controller.\n");
2446
2447 return (0);
2448 }
2449
2450
2451 if ((ha->conf->ucLogDriveCount > 0) && (ha->requires_esl == 1))
2452 ips_clear_adapter(ha, IPS_INTR_IORL);
2453
2454
2455 ha->ntargets = IPS_MAX_TARGETS + 1;
2456 ha->nlun = 1;
2457 ha->nbus = (ha->enq->ucMaxPhysicalDevices / IPS_MAX_TARGETS) + 1;
2458
2459 switch (ha->conf->logical_drive[0].ucStripeSize) {
2460 case 4:
2461 ha->max_xfer = 0x10000;
2462 break;
2463
2464 case 5:
2465 ha->max_xfer = 0x20000;
2466 break;
2467
2468 case 6:
2469 ha->max_xfer = 0x40000;
2470 break;
2471
2472 case 7:
2473 default:
2474 ha->max_xfer = 0x80000;
2475 break;
2476 }
2477
2478
2479 if (le32_to_cpu(ha->subsys->param[4]) & 0x1) {
2480
2481 ha->max_cmds = ha->enq->ucConcurrentCmdCount;
2482 } else {
2483
2484 switch (ha->conf->logical_drive[0].ucStripeSize) {
2485 case 4:
2486 ha->max_cmds = 32;
2487 break;
2488
2489 case 5:
2490 ha->max_cmds = 16;
2491 break;
2492
2493 case 6:
2494 ha->max_cmds = 8;
2495 break;
2496
2497 case 7:
2498 default:
2499 ha->max_cmds = 4;
2500 break;
2501 }
2502 }
2503
2504
2505 if ((ha->ad_type == IPS_ADTYPE_SERVERAID3L) ||
2506 (ha->ad_type == IPS_ADTYPE_SERVERAID4L) ||
2507 (ha->ad_type == IPS_ADTYPE_SERVERAID4LX)) {
2508 if ((ha->max_cmds > MaxLiteCmds) && (MaxLiteCmds))
2509 ha->max_cmds = MaxLiteCmds;
2510 }
2511
2512
2513 ha->ha_id[0] = IPS_ADAPTER_ID;
2514 for (i = 1; i < ha->nbus; i++) {
2515 ha->ha_id[i] = ha->conf->init_id[i - 1] & 0x1f;
2516 ha->dcdb_active[i - 1] = 0;
2517 }
2518
2519 return (1);
2520}
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530
2531static void
2532ips_next(ips_ha_t * ha, int intr)
2533{
2534 ips_scb_t *scb;
2535 struct scsi_cmnd *SC;
2536 struct scsi_cmnd *p;
2537 struct scsi_cmnd *q;
2538 ips_copp_wait_item_t *item;
2539 int ret;
2540 struct Scsi_Host *host;
2541 METHOD_TRACE("ips_next", 1);
2542
2543 if (!ha)
2544 return;
2545 host = ips_sh[ha->host_num];
2546
2547
2548
2549
2550 if (intr == IPS_INTR_ON)
2551 spin_lock(host->host_lock);
2552
2553 if ((ha->subsys->param[3] & 0x300000)
2554 && (ha->scb_activelist.count == 0)) {
2555 struct timeval tv;
2556
2557 do_gettimeofday(&tv);
2558
2559 if (tv.tv_sec - ha->last_ffdc > IPS_SECS_8HOURS) {
2560 ha->last_ffdc = tv.tv_sec;
2561 ips_ffdc_time(ha);
2562 }
2563 }
2564
2565
2566
2567
2568
2569
2570
2571
2572 while ((ha->num_ioctl < IPS_MAX_IOCTL) &&
2573 (ha->copp_waitlist.head) && (scb = ips_getscb(ha))) {
2574
2575 item = ips_removeq_copp_head(&ha->copp_waitlist);
2576 ha->num_ioctl++;
2577 if (intr == IPS_INTR_ON)
2578 spin_unlock(host->host_lock);
2579 scb->scsi_cmd = item->scsi_cmd;
2580 kfree(item);
2581
2582 ret = ips_make_passthru(ha, scb->scsi_cmd, scb, intr);
2583
2584 if (intr == IPS_INTR_ON)
2585 spin_lock(host->host_lock);
2586 switch (ret) {
2587 case IPS_FAILURE:
2588 if (scb->scsi_cmd) {
2589 scb->scsi_cmd->result = DID_ERROR << 16;
2590 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2591 }
2592
2593 ips_freescb(ha, scb);
2594 break;
2595 case IPS_SUCCESS_IMM:
2596 if (scb->scsi_cmd) {
2597 scb->scsi_cmd->result = DID_OK << 16;
2598 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2599 }
2600
2601 ips_freescb(ha, scb);
2602 break;
2603 default:
2604 break;
2605 }
2606
2607 if (ret != IPS_SUCCESS) {
2608 ha->num_ioctl--;
2609 continue;
2610 }
2611
2612 ret = ips_send_cmd(ha, scb);
2613
2614 if (ret == IPS_SUCCESS)
2615 ips_putq_scb_head(&ha->scb_activelist, scb);
2616 else
2617 ha->num_ioctl--;
2618
2619 switch (ret) {
2620 case IPS_FAILURE:
2621 if (scb->scsi_cmd) {
2622 scb->scsi_cmd->result = DID_ERROR << 16;
2623 }
2624
2625 ips_freescb(ha, scb);
2626 break;
2627 case IPS_SUCCESS_IMM:
2628 ips_freescb(ha, scb);
2629 break;
2630 default:
2631 break;
2632 }
2633
2634 }
2635
2636
2637
2638
2639
2640 p = ha->scb_waitlist.head;
2641 while ((p) && (scb = ips_getscb(ha))) {
2642 if ((scmd_channel(p) > 0)
2643 && (ha->
2644 dcdb_active[scmd_channel(p) -
2645 1] & (1 << scmd_id(p)))) {
2646 ips_freescb(ha, scb);
2647 p = (struct scsi_cmnd *) p->host_scribble;
2648 continue;
2649 }
2650
2651 q = p;
2652 SC = ips_removeq_wait(&ha->scb_waitlist, q);
2653
2654 if (intr == IPS_INTR_ON)
2655 spin_unlock(host->host_lock);
2656
2657 SC->result = DID_OK;
2658 SC->host_scribble = NULL;
2659
2660 scb->target_id = SC->device->id;
2661 scb->lun = SC->device->lun;
2662 scb->bus = SC->device->channel;
2663 scb->scsi_cmd = SC;
2664 scb->breakup = 0;
2665 scb->data_len = 0;
2666 scb->callback = ipsintr_done;
2667 scb->timeout = ips_cmd_timeout;
2668 memset(&scb->cmd, 0, 16);
2669
2670
2671 memcpy(scb->cdb, SC->cmnd, SC->cmd_len);
2672
2673 scb->sg_count = scsi_dma_map(SC);
2674 BUG_ON(scb->sg_count < 0);
2675 if (scb->sg_count) {
2676 struct scatterlist *sg;
2677 int i;
2678
2679 scb->flags |= IPS_SCB_MAP_SG;
2680
2681 scsi_for_each_sg(SC, sg, scb->sg_count, i) {
2682 if (ips_fill_scb_sg_single
2683 (ha, sg_dma_address(sg), scb, i,
2684 sg_dma_len(sg)) < 0)
2685 break;
2686 }
2687 scb->dcdb.transfer_length = scb->data_len;
2688 } else {
2689 scb->data_busaddr = 0L;
2690 scb->sg_len = 0;
2691 scb->data_len = 0;
2692 scb->dcdb.transfer_length = 0;
2693 }
2694
2695 scb->dcdb.cmd_attribute =
2696 ips_command_direction[scb->scsi_cmd->cmnd[0]];
2697
2698
2699
2700 if ((scb->scsi_cmd->cmnd[0] == WRITE_BUFFER) &&
2701 (scb->data_len == 0))
2702 scb->dcdb.cmd_attribute = 0;
2703
2704 if (!(scb->dcdb.cmd_attribute & 0x3))
2705 scb->dcdb.transfer_length = 0;
2706
2707 if (scb->data_len >= IPS_MAX_XFER) {
2708 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
2709 scb->dcdb.transfer_length = 0;
2710 }
2711 if (intr == IPS_INTR_ON)
2712 spin_lock(host->host_lock);
2713
2714 ret = ips_send_cmd(ha, scb);
2715
2716 switch (ret) {
2717 case IPS_SUCCESS:
2718 ips_putq_scb_head(&ha->scb_activelist, scb);
2719 break;
2720 case IPS_FAILURE:
2721 if (scb->scsi_cmd) {
2722 scb->scsi_cmd->result = DID_ERROR << 16;
2723 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2724 }
2725
2726 if (scb->bus)
2727 ha->dcdb_active[scb->bus - 1] &=
2728 ~(1 << scb->target_id);
2729
2730 ips_freescb(ha, scb);
2731 break;
2732 case IPS_SUCCESS_IMM:
2733 if (scb->scsi_cmd)
2734 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
2735
2736 if (scb->bus)
2737 ha->dcdb_active[scb->bus - 1] &=
2738 ~(1 << scb->target_id);
2739
2740 ips_freescb(ha, scb);
2741 break;
2742 default:
2743 break;
2744 }
2745
2746 p = (struct scsi_cmnd *) p->host_scribble;
2747
2748 }
2749
2750 if (intr == IPS_INTR_ON)
2751 spin_unlock(host->host_lock);
2752}
2753
2754
2755
2756
2757
2758
2759
2760
2761
2762
2763
2764
2765static void
2766ips_putq_scb_head(ips_scb_queue_t * queue, ips_scb_t * item)
2767{
2768 METHOD_TRACE("ips_putq_scb_head", 1);
2769
2770 if (!item)
2771 return;
2772
2773 item->q_next = queue->head;
2774 queue->head = item;
2775
2776 if (!queue->tail)
2777 queue->tail = item;
2778
2779 queue->count++;
2780}
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793static ips_scb_t *
2794ips_removeq_scb_head(ips_scb_queue_t * queue)
2795{
2796 ips_scb_t *item;
2797
2798 METHOD_TRACE("ips_removeq_scb_head", 1);
2799
2800 item = queue->head;
2801
2802 if (!item) {
2803 return (NULL);
2804 }
2805
2806 queue->head = item->q_next;
2807 item->q_next = NULL;
2808
2809 if (queue->tail == item)
2810 queue->tail = NULL;
2811
2812 queue->count--;
2813
2814 return (item);
2815}
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828static ips_scb_t *
2829ips_removeq_scb(ips_scb_queue_t * queue, ips_scb_t * item)
2830{
2831 ips_scb_t *p;
2832
2833 METHOD_TRACE("ips_removeq_scb", 1);
2834
2835 if (!item)
2836 return (NULL);
2837
2838 if (item == queue->head) {
2839 return (ips_removeq_scb_head(queue));
2840 }
2841
2842 p = queue->head;
2843
2844 while ((p) && (item != p->q_next))
2845 p = p->q_next;
2846
2847 if (p) {
2848
2849 p->q_next = item->q_next;
2850
2851 if (!item->q_next)
2852 queue->tail = p;
2853
2854 item->q_next = NULL;
2855 queue->count--;
2856
2857 return (item);
2858 }
2859
2860 return (NULL);
2861}
2862
2863
2864
2865
2866
2867
2868
2869
2870
2871
2872
2873
2874static void ips_putq_wait_tail(ips_wait_queue_entry_t *queue, struct scsi_cmnd *item)
2875{
2876 METHOD_TRACE("ips_putq_wait_tail", 1);
2877
2878 if (!item)
2879 return;
2880
2881 item->host_scribble = NULL;
2882
2883 if (queue->tail)
2884 queue->tail->host_scribble = (char *) item;
2885
2886 queue->tail = item;
2887
2888 if (!queue->head)
2889 queue->head = item;
2890
2891 queue->count++;
2892}
2893
2894
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904
2905static struct scsi_cmnd *ips_removeq_wait_head(ips_wait_queue_entry_t *queue)
2906{
2907 struct scsi_cmnd *item;
2908
2909 METHOD_TRACE("ips_removeq_wait_head", 1);
2910
2911 item = queue->head;
2912
2913 if (!item) {
2914 return (NULL);
2915 }
2916
2917 queue->head = (struct scsi_cmnd *) item->host_scribble;
2918 item->host_scribble = NULL;
2919
2920 if (queue->tail == item)
2921 queue->tail = NULL;
2922
2923 queue->count--;
2924
2925 return (item);
2926}
2927
2928
2929
2930
2931
2932
2933
2934
2935
2936
2937
2938
2939static struct scsi_cmnd *ips_removeq_wait(ips_wait_queue_entry_t *queue,
2940 struct scsi_cmnd *item)
2941{
2942 struct scsi_cmnd *p;
2943
2944 METHOD_TRACE("ips_removeq_wait", 1);
2945
2946 if (!item)
2947 return (NULL);
2948
2949 if (item == queue->head) {
2950 return (ips_removeq_wait_head(queue));
2951 }
2952
2953 p = queue->head;
2954
2955 while ((p) && (item != (struct scsi_cmnd *) p->host_scribble))
2956 p = (struct scsi_cmnd *) p->host_scribble;
2957
2958 if (p) {
2959
2960 p->host_scribble = item->host_scribble;
2961
2962 if (!item->host_scribble)
2963 queue->tail = p;
2964
2965 item->host_scribble = NULL;
2966 queue->count--;
2967
2968 return (item);
2969 }
2970
2971 return (NULL);
2972}
2973
2974
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985static void
2986ips_putq_copp_tail(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
2987{
2988 METHOD_TRACE("ips_putq_copp_tail", 1);
2989
2990 if (!item)
2991 return;
2992
2993 item->next = NULL;
2994
2995 if (queue->tail)
2996 queue->tail->next = item;
2997
2998 queue->tail = item;
2999
3000 if (!queue->head)
3001 queue->head = item;
3002
3003 queue->count++;
3004}
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017static ips_copp_wait_item_t *
3018ips_removeq_copp_head(ips_copp_queue_t * queue)
3019{
3020 ips_copp_wait_item_t *item;
3021
3022 METHOD_TRACE("ips_removeq_copp_head", 1);
3023
3024 item = queue->head;
3025
3026 if (!item) {
3027 return (NULL);
3028 }
3029
3030 queue->head = item->next;
3031 item->next = NULL;
3032
3033 if (queue->tail == item)
3034 queue->tail = NULL;
3035
3036 queue->count--;
3037
3038 return (item);
3039}
3040
3041
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052static ips_copp_wait_item_t *
3053ips_removeq_copp(ips_copp_queue_t * queue, ips_copp_wait_item_t * item)
3054{
3055 ips_copp_wait_item_t *p;
3056
3057 METHOD_TRACE("ips_removeq_copp", 1);
3058
3059 if (!item)
3060 return (NULL);
3061
3062 if (item == queue->head) {
3063 return (ips_removeq_copp_head(queue));
3064 }
3065
3066 p = queue->head;
3067
3068 while ((p) && (item != p->next))
3069 p = p->next;
3070
3071 if (p) {
3072
3073 p->next = item->next;
3074
3075 if (!item->next)
3076 queue->tail = p;
3077
3078 item->next = NULL;
3079 queue->count--;
3080
3081 return (item);
3082 }
3083
3084 return (NULL);
3085}
3086
3087
3088
3089
3090
3091
3092
3093
3094
3095
3096static void
3097ipsintr_blocking(ips_ha_t * ha, ips_scb_t * scb)
3098{
3099 METHOD_TRACE("ipsintr_blocking", 2);
3100
3101 ips_freescb(ha, scb);
3102 if ((ha->waitflag == TRUE) && (ha->cmd_in_progress == scb->cdb[0])) {
3103 ha->waitflag = FALSE;
3104
3105 return;
3106 }
3107}
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118static void
3119ipsintr_done(ips_ha_t * ha, ips_scb_t * scb)
3120{
3121 METHOD_TRACE("ipsintr_done", 2);
3122
3123 if (!scb) {
3124 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3125 "Spurious interrupt; scb NULL.\n");
3126
3127 return;
3128 }
3129
3130 if (scb->scsi_cmd == NULL) {
3131
3132 IPS_PRINTK(KERN_WARNING, ha->pcidev,
3133 "Spurious interrupt; scsi_cmd not set.\n");
3134
3135 return;
3136 }
3137
3138 ips_done(ha, scb);
3139}
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150static void
3151ips_done(ips_ha_t * ha, ips_scb_t * scb)
3152{
3153 int ret;
3154
3155 METHOD_TRACE("ips_done", 1);
3156
3157 if (!scb)
3158 return;
3159
3160 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd))) {
3161 ips_cleanup_passthru(ha, scb);
3162 ha->num_ioctl--;
3163 } else {
3164
3165
3166
3167
3168
3169 if ((scb->breakup) || (scb->sg_break)) {
3170 struct scatterlist *sg;
3171 int i, sg_dma_index, ips_sg_index = 0;
3172
3173
3174 scb->data_len = 0;
3175
3176 sg = scsi_sglist(scb->scsi_cmd);
3177
3178
3179 sg_dma_index = scb->breakup;
3180 for (i = 0; i < scb->breakup; i++)
3181 sg = sg_next(sg);
3182
3183
3184 ips_fill_scb_sg_single(ha,
3185 sg_dma_address(sg),
3186 scb, ips_sg_index++,
3187 sg_dma_len(sg));
3188
3189 for (; sg_dma_index < scsi_sg_count(scb->scsi_cmd);
3190 sg_dma_index++, sg = sg_next(sg)) {
3191 if (ips_fill_scb_sg_single
3192 (ha,
3193 sg_dma_address(sg),
3194 scb, ips_sg_index++,
3195 sg_dma_len(sg)) < 0)
3196 break;
3197 }
3198
3199 scb->dcdb.transfer_length = scb->data_len;
3200 scb->dcdb.cmd_attribute |=
3201 ips_command_direction[scb->scsi_cmd->cmnd[0]];
3202
3203 if (!(scb->dcdb.cmd_attribute & 0x3))
3204 scb->dcdb.transfer_length = 0;
3205
3206 if (scb->data_len >= IPS_MAX_XFER) {
3207 scb->dcdb.cmd_attribute |= IPS_TRANSFER64K;
3208 scb->dcdb.transfer_length = 0;
3209 }
3210
3211 ret = ips_send_cmd(ha, scb);
3212
3213 switch (ret) {
3214 case IPS_FAILURE:
3215 if (scb->scsi_cmd) {
3216 scb->scsi_cmd->result = DID_ERROR << 16;
3217 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3218 }
3219
3220 ips_freescb(ha, scb);
3221 break;
3222 case IPS_SUCCESS_IMM:
3223 if (scb->scsi_cmd) {
3224 scb->scsi_cmd->result = DID_ERROR << 16;
3225 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3226 }
3227
3228 ips_freescb(ha, scb);
3229 break;
3230 default:
3231 break;
3232 }
3233
3234 return;
3235 }
3236 }
3237
3238 if (scb->bus) {
3239 ha->dcdb_active[scb->bus - 1] &= ~(1 << scb->target_id);
3240 }
3241
3242 scb->scsi_cmd->scsi_done(scb->scsi_cmd);
3243
3244 ips_freescb(ha, scb);
3245}
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255
3256static int
3257ips_map_status(ips_ha_t * ha, ips_scb_t * scb, ips_stat_t * sp)
3258{
3259 int errcode;
3260 int device_error;
3261 uint32_t transfer_len;
3262 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3263 IPS_SCSI_INQ_DATA inquiryData;
3264
3265 METHOD_TRACE("ips_map_status", 1);
3266
3267 if (scb->bus) {
3268 DEBUG_VAR(2,
3269 "(%s%d) Physical device error (%d %d %d): %x %x, Sense Key: %x, ASC: %x, ASCQ: %x",
3270 ips_name, ha->host_num,
3271 scb->scsi_cmd->device->channel,
3272 scb->scsi_cmd->device->id, scb->scsi_cmd->device->lun,
3273 scb->basic_status, scb->extended_status,
3274 scb->extended_status ==
3275 IPS_ERR_CKCOND ? scb->dcdb.sense_info[2] & 0xf : 0,
3276 scb->extended_status ==
3277 IPS_ERR_CKCOND ? scb->dcdb.sense_info[12] : 0,
3278 scb->extended_status ==
3279 IPS_ERR_CKCOND ? scb->dcdb.sense_info[13] : 0);
3280 }
3281
3282
3283 errcode = DID_ERROR;
3284 device_error = 0;
3285
3286 switch (scb->basic_status & IPS_GSC_STATUS_MASK) {
3287 case IPS_CMD_TIMEOUT:
3288 errcode = DID_TIME_OUT;
3289 break;
3290
3291 case IPS_INVAL_OPCO:
3292 case IPS_INVAL_CMD_BLK:
3293 case IPS_INVAL_PARM_BLK:
3294 case IPS_LD_ERROR:
3295 case IPS_CMD_CMPLT_WERROR:
3296 break;
3297
3298 case IPS_PHYS_DRV_ERROR:
3299 switch (scb->extended_status) {
3300 case IPS_ERR_SEL_TO:
3301 if (scb->bus)
3302 errcode = DID_NO_CONNECT;
3303
3304 break;
3305
3306 case IPS_ERR_OU_RUN:
3307 if ((scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB) ||
3308 (scb->cmd.dcdb.op_code ==
3309 IPS_CMD_EXTENDED_DCDB_SG)) {
3310 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3311 transfer_len = tapeDCDB->transfer_length;
3312 } else {
3313 transfer_len =
3314 (uint32_t) scb->dcdb.transfer_length;
3315 }
3316
3317 if ((scb->bus) && (transfer_len < scb->data_len)) {
3318
3319 errcode = DID_OK;
3320
3321
3322 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3323 ips_scmd_buf_read(scb->scsi_cmd,
3324 &inquiryData, sizeof (inquiryData));
3325 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK) {
3326 errcode = DID_TIME_OUT;
3327 break;
3328 }
3329 }
3330 } else
3331 errcode = DID_ERROR;
3332
3333 break;
3334
3335 case IPS_ERR_RECOVERY:
3336
3337 if (scb->bus)
3338 errcode = DID_OK;
3339
3340 break;
3341
3342 case IPS_ERR_HOST_RESET:
3343 case IPS_ERR_DEV_RESET:
3344 errcode = DID_RESET;
3345 break;
3346
3347 case IPS_ERR_CKCOND:
3348 if (scb->bus) {
3349 if ((scb->cmd.dcdb.op_code ==
3350 IPS_CMD_EXTENDED_DCDB)
3351 || (scb->cmd.dcdb.op_code ==
3352 IPS_CMD_EXTENDED_DCDB_SG)) {
3353 tapeDCDB =
3354 (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3355 memcpy(scb->scsi_cmd->sense_buffer,
3356 tapeDCDB->sense_info,
3357 SCSI_SENSE_BUFFERSIZE);
3358 } else {
3359 memcpy(scb->scsi_cmd->sense_buffer,
3360 scb->dcdb.sense_info,
3361 SCSI_SENSE_BUFFERSIZE);
3362 }
3363 device_error = 2;
3364 }
3365
3366 errcode = DID_OK;
3367
3368 break;
3369
3370 default:
3371 errcode = DID_ERROR;
3372 break;
3373
3374 }
3375 }
3376
3377 scb->scsi_cmd->result = device_error | (errcode << 16);
3378
3379 return (1);
3380}
3381
3382
3383
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393static int
3394ips_send_wait(ips_ha_t * ha, ips_scb_t * scb, int timeout, int intr)
3395{
3396 int ret;
3397
3398 METHOD_TRACE("ips_send_wait", 1);
3399
3400 if (intr != IPS_FFDC) {
3401 ha->waitflag = TRUE;
3402 ha->cmd_in_progress = scb->cdb[0];
3403 }
3404 scb->callback = ipsintr_blocking;
3405 ret = ips_send_cmd(ha, scb);
3406
3407 if ((ret == IPS_FAILURE) || (ret == IPS_SUCCESS_IMM))
3408 return (ret);
3409
3410 if (intr != IPS_FFDC)
3411 ret = ips_wait(ha, timeout, intr);
3412
3413 return (ret);
3414}
3415
3416
3417
3418
3419
3420
3421
3422
3423static void
3424ips_scmd_buf_write(struct scsi_cmnd *scmd, void *data, unsigned int count)
3425{
3426 unsigned long flags;
3427
3428 local_irq_save(flags);
3429 scsi_sg_copy_from_buffer(scmd, data, count);
3430 local_irq_restore(flags);
3431}
3432
3433
3434
3435
3436
3437
3438
3439
3440static void
3441ips_scmd_buf_read(struct scsi_cmnd *scmd, void *data, unsigned int count)
3442{
3443 unsigned long flags;
3444
3445 local_irq_save(flags);
3446 scsi_sg_copy_to_buffer(scmd, data, count);
3447 local_irq_restore(flags);
3448}
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459static int
3460ips_send_cmd(ips_ha_t * ha, ips_scb_t * scb)
3461{
3462 int ret;
3463 char *sp;
3464 int device_error;
3465 IPS_DCDB_TABLE_TAPE *tapeDCDB;
3466 int TimeOut;
3467
3468 METHOD_TRACE("ips_send_cmd", 1);
3469
3470 ret = IPS_SUCCESS;
3471
3472 if (!scb->scsi_cmd) {
3473
3474
3475 if (scb->bus > 0) {
3476
3477
3478 if ((ha->waitflag == TRUE) &&
3479 (ha->cmd_in_progress == scb->cdb[0])) {
3480 ha->waitflag = FALSE;
3481 }
3482
3483 return (1);
3484 }
3485 } else if ((scb->bus == 0) && (!ips_is_passthru(scb->scsi_cmd))) {
3486
3487 ret = IPS_SUCCESS_IMM;
3488
3489 switch (scb->scsi_cmd->cmnd[0]) {
3490 case ALLOW_MEDIUM_REMOVAL:
3491 case REZERO_UNIT:
3492 case ERASE:
3493 case WRITE_FILEMARKS:
3494 case SPACE:
3495 scb->scsi_cmd->result = DID_ERROR << 16;
3496 break;
3497
3498 case START_STOP:
3499 scb->scsi_cmd->result = DID_OK << 16;
3500
3501 case TEST_UNIT_READY:
3502 case INQUIRY:
3503 if (scb->target_id == IPS_ADAPTER_ID) {
3504
3505
3506
3507
3508 if (scb->scsi_cmd->cmnd[0] == TEST_UNIT_READY)
3509 scb->scsi_cmd->result = DID_OK << 16;
3510
3511 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3512 IPS_SCSI_INQ_DATA inquiry;
3513
3514 memset(&inquiry, 0,
3515 sizeof (IPS_SCSI_INQ_DATA));
3516
3517 inquiry.DeviceType =
3518 IPS_SCSI_INQ_TYPE_PROCESSOR;
3519 inquiry.DeviceTypeQualifier =
3520 IPS_SCSI_INQ_LU_CONNECTED;
3521 inquiry.Version = IPS_SCSI_INQ_REV2;
3522 inquiry.ResponseDataFormat =
3523 IPS_SCSI_INQ_RD_REV2;
3524 inquiry.AdditionalLength = 31;
3525 inquiry.Flags[0] =
3526 IPS_SCSI_INQ_Address16;
3527 inquiry.Flags[1] =
3528 IPS_SCSI_INQ_WBus16 |
3529 IPS_SCSI_INQ_Sync;
3530 strncpy(inquiry.VendorId, "IBM ",
3531 8);
3532 strncpy(inquiry.ProductId,
3533 "SERVERAID ", 16);
3534 strncpy(inquiry.ProductRevisionLevel,
3535 "1.00", 4);
3536
3537 ips_scmd_buf_write(scb->scsi_cmd,
3538 &inquiry,
3539 sizeof (inquiry));
3540
3541 scb->scsi_cmd->result = DID_OK << 16;
3542 }
3543 } else {
3544 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3545 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3546 scb->cmd.logical_info.reserved = 0;
3547 scb->cmd.logical_info.reserved2 = 0;
3548 scb->data_len = sizeof (IPS_LD_INFO);
3549 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3550 scb->flags = 0;
3551 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3552 ret = IPS_SUCCESS;
3553 }
3554
3555 break;
3556
3557 case REQUEST_SENSE:
3558 ips_reqsen(ha, scb);
3559 scb->scsi_cmd->result = DID_OK << 16;
3560 break;
3561
3562 case READ_6:
3563 case WRITE_6:
3564 if (!scb->sg_len) {
3565 scb->cmd.basic_io.op_code =
3566 (scb->scsi_cmd->cmnd[0] ==
3567 READ_6) ? IPS_CMD_READ : IPS_CMD_WRITE;
3568 scb->cmd.basic_io.enhanced_sg = 0;
3569 scb->cmd.basic_io.sg_addr =
3570 cpu_to_le32(scb->data_busaddr);
3571 } else {
3572 scb->cmd.basic_io.op_code =
3573 (scb->scsi_cmd->cmnd[0] ==
3574 READ_6) ? IPS_CMD_READ_SG :
3575 IPS_CMD_WRITE_SG;
3576 scb->cmd.basic_io.enhanced_sg =
3577 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3578 scb->cmd.basic_io.sg_addr =
3579 cpu_to_le32(scb->sg_busaddr);
3580 }
3581
3582 scb->cmd.basic_io.segment_4G = 0;
3583 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3584 scb->cmd.basic_io.log_drv = scb->target_id;
3585 scb->cmd.basic_io.sg_count = scb->sg_len;
3586
3587 if (scb->cmd.basic_io.lba)
3588 le32_add_cpu(&scb->cmd.basic_io.lba,
3589 le16_to_cpu(scb->cmd.basic_io.
3590 sector_count));
3591 else
3592 scb->cmd.basic_io.lba =
3593 (((scb->scsi_cmd->
3594 cmnd[1] & 0x1f) << 16) | (scb->scsi_cmd->
3595 cmnd[2] << 8) |
3596 (scb->scsi_cmd->cmnd[3]));
3597
3598 scb->cmd.basic_io.sector_count =
3599 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3600
3601 if (le16_to_cpu(scb->cmd.basic_io.sector_count) == 0)
3602 scb->cmd.basic_io.sector_count =
3603 cpu_to_le16(256);
3604
3605 ret = IPS_SUCCESS;
3606 break;
3607
3608 case READ_10:
3609 case WRITE_10:
3610 if (!scb->sg_len) {
3611 scb->cmd.basic_io.op_code =
3612 (scb->scsi_cmd->cmnd[0] ==
3613 READ_10) ? IPS_CMD_READ : IPS_CMD_WRITE;
3614 scb->cmd.basic_io.enhanced_sg = 0;
3615 scb->cmd.basic_io.sg_addr =
3616 cpu_to_le32(scb->data_busaddr);
3617 } else {
3618 scb->cmd.basic_io.op_code =
3619 (scb->scsi_cmd->cmnd[0] ==
3620 READ_10) ? IPS_CMD_READ_SG :
3621 IPS_CMD_WRITE_SG;
3622 scb->cmd.basic_io.enhanced_sg =
3623 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3624 scb->cmd.basic_io.sg_addr =
3625 cpu_to_le32(scb->sg_busaddr);
3626 }
3627
3628 scb->cmd.basic_io.segment_4G = 0;
3629 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3630 scb->cmd.basic_io.log_drv = scb->target_id;
3631 scb->cmd.basic_io.sg_count = scb->sg_len;
3632
3633 if (scb->cmd.basic_io.lba)
3634 le32_add_cpu(&scb->cmd.basic_io.lba,
3635 le16_to_cpu(scb->cmd.basic_io.
3636 sector_count));
3637 else
3638 scb->cmd.basic_io.lba =
3639 ((scb->scsi_cmd->cmnd[2] << 24) | (scb->
3640 scsi_cmd->
3641 cmnd[3]
3642 << 16) |
3643 (scb->scsi_cmd->cmnd[4] << 8) | scb->
3644 scsi_cmd->cmnd[5]);
3645
3646 scb->cmd.basic_io.sector_count =
3647 cpu_to_le16(scb->data_len / IPS_BLKSIZE);
3648
3649 if (cpu_to_le16(scb->cmd.basic_io.sector_count) == 0) {
3650
3651
3652
3653
3654
3655 scb->scsi_cmd->result = DID_OK << 16;
3656 } else
3657 ret = IPS_SUCCESS;
3658
3659 break;
3660
3661 case RESERVE:
3662 case RELEASE:
3663 scb->scsi_cmd->result = DID_OK << 16;
3664 break;
3665
3666 case MODE_SENSE:
3667 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
3668 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
3669 scb->cmd.basic_io.segment_4G = 0;
3670 scb->cmd.basic_io.enhanced_sg = 0;
3671 scb->data_len = sizeof (*ha->enq);
3672 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
3673 ret = IPS_SUCCESS;
3674 break;
3675
3676 case READ_CAPACITY:
3677 scb->cmd.logical_info.op_code = IPS_CMD_GET_LD_INFO;
3678 scb->cmd.logical_info.command_id = IPS_COMMAND_ID(ha, scb);
3679 scb->cmd.logical_info.reserved = 0;
3680 scb->cmd.logical_info.reserved2 = 0;
3681 scb->cmd.logical_info.reserved3 = 0;
3682 scb->data_len = sizeof (IPS_LD_INFO);
3683 scb->data_busaddr = ha->logical_drive_info_dma_addr;
3684 scb->flags = 0;
3685 scb->cmd.logical_info.buffer_addr = scb->data_busaddr;
3686 ret = IPS_SUCCESS;
3687 break;
3688
3689 case SEND_DIAGNOSTIC:
3690 case REASSIGN_BLOCKS:
3691 case FORMAT_UNIT:
3692 case SEEK_10:
3693 case VERIFY:
3694 case READ_DEFECT_DATA:
3695 case READ_BUFFER:
3696 case WRITE_BUFFER:
3697 scb->scsi_cmd->result = DID_OK << 16;
3698 break;
3699
3700 default:
3701
3702
3703
3704 sp = (char *) scb->scsi_cmd->sense_buffer;
3705
3706 sp[0] = 0x70;
3707 sp[2] = ILLEGAL_REQUEST;
3708 sp[7] = 0x0A;
3709 sp[12] = 0x20;
3710 sp[13] = 0x00;
3711
3712 device_error = 2;
3713 scb->scsi_cmd->result = device_error | (DID_OK << 16);
3714 break;
3715 }
3716 }
3717
3718 if (ret == IPS_SUCCESS_IMM)
3719 return (ret);
3720
3721
3722 if (scb->bus > 0) {
3723
3724
3725
3726 if (ha->conf->dev[scb->bus - 1][scb->target_id].ucState == 0) {
3727 scb->scsi_cmd->result = DID_NO_CONNECT << 16;
3728 return (IPS_SUCCESS_IMM);
3729 }
3730
3731 ha->dcdb_active[scb->bus - 1] |= (1 << scb->target_id);
3732 scb->cmd.dcdb.command_id = IPS_COMMAND_ID(ha, scb);
3733 scb->cmd.dcdb.dcdb_address = cpu_to_le32(scb->scb_busaddr +
3734 (unsigned long) &scb->
3735 dcdb -
3736 (unsigned long) scb);
3737 scb->cmd.dcdb.reserved = 0;
3738 scb->cmd.dcdb.reserved2 = 0;
3739 scb->cmd.dcdb.reserved3 = 0;
3740 scb->cmd.dcdb.segment_4G = 0;
3741 scb->cmd.dcdb.enhanced_sg = 0;
3742
3743 TimeOut = scb->scsi_cmd->request->timeout;
3744
3745 if (ha->subsys->param[4] & 0x00100000) {
3746 if (!scb->sg_len) {
3747 scb->cmd.dcdb.op_code = IPS_CMD_EXTENDED_DCDB;
3748 } else {
3749 scb->cmd.dcdb.op_code =
3750 IPS_CMD_EXTENDED_DCDB_SG;
3751 scb->cmd.dcdb.enhanced_sg =
3752 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3753 }
3754
3755 tapeDCDB = (IPS_DCDB_TABLE_TAPE *) & scb->dcdb;
3756 tapeDCDB->device_address =
3757 ((scb->bus - 1) << 4) | scb->target_id;
3758 tapeDCDB->cmd_attribute |= IPS_DISCONNECT_ALLOWED;
3759 tapeDCDB->cmd_attribute &= ~IPS_TRANSFER64K;
3760
3761 if (TimeOut) {
3762 if (TimeOut < (10 * HZ))
3763 tapeDCDB->cmd_attribute |= IPS_TIMEOUT10;
3764 else if (TimeOut < (60 * HZ))
3765 tapeDCDB->cmd_attribute |= IPS_TIMEOUT60;
3766 else if (TimeOut < (1200 * HZ))
3767 tapeDCDB->cmd_attribute |= IPS_TIMEOUT20M;
3768 }
3769
3770 tapeDCDB->cdb_length = scb->scsi_cmd->cmd_len;
3771 tapeDCDB->reserved_for_LUN = 0;
3772 tapeDCDB->transfer_length = scb->data_len;
3773 if (scb->cmd.dcdb.op_code == IPS_CMD_EXTENDED_DCDB_SG)
3774 tapeDCDB->buffer_pointer =
3775 cpu_to_le32(scb->sg_busaddr);
3776 else
3777 tapeDCDB->buffer_pointer =
3778 cpu_to_le32(scb->data_busaddr);
3779 tapeDCDB->sg_count = scb->sg_len;
3780 tapeDCDB->sense_length = sizeof (tapeDCDB->sense_info);
3781 tapeDCDB->scsi_status = 0;
3782 tapeDCDB->reserved = 0;
3783 memcpy(tapeDCDB->scsi_cdb, scb->scsi_cmd->cmnd,
3784 scb->scsi_cmd->cmd_len);
3785 } else {
3786 if (!scb->sg_len) {
3787 scb->cmd.dcdb.op_code = IPS_CMD_DCDB;
3788 } else {
3789 scb->cmd.dcdb.op_code = IPS_CMD_DCDB_SG;
3790 scb->cmd.dcdb.enhanced_sg =
3791 IPS_USE_ENH_SGLIST(ha) ? 0xFF : 0;
3792 }
3793
3794 scb->dcdb.device_address =
3795 ((scb->bus - 1) << 4) | scb->target_id;
3796 scb->dcdb.cmd_attribute |= IPS_DISCONNECT_ALLOWED;
3797
3798 if (TimeOut) {
3799 if (TimeOut < (10 * HZ))
3800 scb->dcdb.cmd_attribute |= IPS_TIMEOUT10;
3801 else if (TimeOut < (60 * HZ))
3802 scb->dcdb.cmd_attribute |= IPS_TIMEOUT60;
3803 else if (TimeOut < (1200 * HZ))
3804 scb->dcdb.cmd_attribute |= IPS_TIMEOUT20M;
3805 }
3806
3807 scb->dcdb.transfer_length = scb->data_len;
3808 if (scb->dcdb.cmd_attribute & IPS_TRANSFER64K)
3809 scb->dcdb.transfer_length = 0;
3810 if (scb->cmd.dcdb.op_code == IPS_CMD_DCDB_SG)
3811 scb->dcdb.buffer_pointer =
3812 cpu_to_le32(scb->sg_busaddr);
3813 else
3814 scb->dcdb.buffer_pointer =
3815 cpu_to_le32(scb->data_busaddr);
3816 scb->dcdb.cdb_length = scb->scsi_cmd->cmd_len;
3817 scb->dcdb.sense_length = sizeof (scb->dcdb.sense_info);
3818 scb->dcdb.sg_count = scb->sg_len;
3819 scb->dcdb.reserved = 0;
3820 memcpy(scb->dcdb.scsi_cdb, scb->scsi_cmd->cmnd,
3821 scb->scsi_cmd->cmd_len);
3822 scb->dcdb.scsi_status = 0;
3823 scb->dcdb.reserved2[0] = 0;
3824 scb->dcdb.reserved2[1] = 0;
3825 scb->dcdb.reserved2[2] = 0;
3826 }
3827 }
3828
3829 return ((*ha->func.issue) (ha, scb));
3830}
3831
3832
3833
3834
3835
3836
3837
3838
3839
3840
3841static void
3842ips_chkstatus(ips_ha_t * ha, IPS_STATUS * pstatus)
3843{
3844 ips_scb_t *scb;
3845 ips_stat_t *sp;
3846 uint8_t basic_status;
3847 uint8_t ext_status;
3848 int errcode;
3849 IPS_SCSI_INQ_DATA inquiryData;
3850
3851 METHOD_TRACE("ips_chkstatus", 1);
3852
3853 scb = &ha->scbs[pstatus->fields.command_id];
3854 scb->basic_status = basic_status =
3855 pstatus->fields.basic_status & IPS_BASIC_STATUS_MASK;
3856 scb->extended_status = ext_status = pstatus->fields.extended_status;
3857
3858 sp = &ha->sp;
3859 sp->residue_len = 0;
3860 sp->scb_addr = (void *) scb;
3861
3862
3863 ips_removeq_scb(&ha->scb_activelist, scb);
3864
3865 if (!scb->scsi_cmd)
3866
3867 return;
3868
3869 DEBUG_VAR(2, "(%s%d) ips_chkstatus: cmd 0x%X id %d (%d %d %d)",
3870 ips_name,
3871 ha->host_num,
3872 scb->cdb[0],
3873 scb->cmd.basic_io.command_id,
3874 scb->bus, scb->target_id, scb->lun);
3875
3876 if ((scb->scsi_cmd) && (ips_is_passthru(scb->scsi_cmd)))
3877
3878 return;
3879
3880 errcode = DID_OK;
3881
3882 if (((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_SUCCESS) ||
3883 ((basic_status & IPS_GSC_STATUS_MASK) == IPS_CMD_RECOVERED_ERROR)) {
3884
3885 if (scb->bus == 0) {
3886 if ((basic_status & IPS_GSC_STATUS_MASK) ==
3887 IPS_CMD_RECOVERED_ERROR) {
3888 DEBUG_VAR(1,
3889 "(%s%d) Recovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
3890 ips_name, ha->host_num,
3891 scb->cmd.basic_io.op_code,
3892 basic_status, ext_status);
3893 }
3894
3895 switch (scb->scsi_cmd->cmnd[0]) {
3896 case ALLOW_MEDIUM_REMOVAL:
3897 case REZERO_UNIT:
3898 case ERASE:
3899 case WRITE_FILEMARKS:
3900 case SPACE:
3901 errcode = DID_ERROR;
3902 break;
3903
3904 case START_STOP:
3905 break;
3906
3907 case TEST_UNIT_READY:
3908 if (!ips_online(ha, scb)) {
3909 errcode = DID_TIME_OUT;
3910 }
3911 break;
3912
3913 case INQUIRY:
3914 if (ips_online(ha, scb)) {
3915 ips_inquiry(ha, scb);
3916 } else {
3917 errcode = DID_TIME_OUT;
3918 }
3919 break;
3920
3921 case REQUEST_SENSE:
3922 ips_reqsen(ha, scb);
3923 break;
3924
3925 case READ_6:
3926 case WRITE_6:
3927 case READ_10:
3928 case WRITE_10:
3929 case RESERVE:
3930 case RELEASE:
3931 break;
3932
3933 case MODE_SENSE:
3934 if (!ips_online(ha, scb)
3935 || !ips_msense(ha, scb)) {
3936 errcode = DID_ERROR;
3937 }
3938 break;
3939
3940 case READ_CAPACITY:
3941 if (ips_online(ha, scb))
3942 ips_rdcap(ha, scb);
3943 else {
3944 errcode = DID_TIME_OUT;
3945 }
3946 break;
3947
3948 case SEND_DIAGNOSTIC:
3949 case REASSIGN_BLOCKS:
3950 break;
3951
3952 case FORMAT_UNIT:
3953 errcode = DID_ERROR;
3954 break;
3955
3956 case SEEK_10:
3957 case VERIFY:
3958 case READ_DEFECT_DATA:
3959 case READ_BUFFER:
3960 case WRITE_BUFFER:
3961 break;
3962
3963 default:
3964 errcode = DID_ERROR;
3965 }
3966
3967 scb->scsi_cmd->result = errcode << 16;
3968 } else {
3969
3970 if (scb->scsi_cmd->cmnd[0] == INQUIRY) {
3971 ips_scmd_buf_read(scb->scsi_cmd,
3972 &inquiryData, sizeof (inquiryData));
3973 if ((inquiryData.DeviceType & 0x1f) == TYPE_DISK)
3974 scb->scsi_cmd->result = DID_TIME_OUT << 16;
3975 }
3976 }
3977 } else {
3978 if (scb->bus == 0) {
3979 DEBUG_VAR(1,
3980 "(%s%d) Unrecovered Logical Drive Error OpCode: %x, BSB: %x, ESB: %x",
3981 ips_name, ha->host_num,
3982 scb->cmd.basic_io.op_code, basic_status,
3983 ext_status);
3984 }
3985
3986 ips_map_status(ha, scb, sp);
3987 }
3988}
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999static int
4000ips_online(ips_ha_t * ha, ips_scb_t * scb)
4001{
4002 METHOD_TRACE("ips_online", 1);
4003
4004 if (scb->target_id >= IPS_MAX_LD)
4005 return (0);
4006
4007 if ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1) {
4008 memset(ha->logical_drive_info, 0, sizeof (IPS_LD_INFO));
4009 return (0);
4010 }
4011
4012 if (ha->logical_drive_info->drive_info[scb->target_id].state !=
4013 IPS_LD_OFFLINE
4014 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4015 IPS_LD_FREE
4016 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4017 IPS_LD_CRS
4018 && ha->logical_drive_info->drive_info[scb->target_id].state !=
4019 IPS_LD_SYS)
4020 return (1);
4021 else
4022 return (0);
4023}
4024
4025
4026
4027
4028
4029
4030
4031
4032
4033
4034static int
4035ips_inquiry(ips_ha_t * ha, ips_scb_t * scb)
4036{
4037 IPS_SCSI_INQ_DATA inquiry;
4038
4039 METHOD_TRACE("ips_inquiry", 1);
4040
4041 memset(&inquiry, 0, sizeof (IPS_SCSI_INQ_DATA));
4042
4043 inquiry.DeviceType = IPS_SCSI_INQ_TYPE_DASD;
4044 inquiry.DeviceTypeQualifier = IPS_SCSI_INQ_LU_CONNECTED;
4045 inquiry.Version = IPS_SCSI_INQ_REV2;
4046 inquiry.ResponseDataFormat = IPS_SCSI_INQ_RD_REV2;
4047 inquiry.AdditionalLength = 31;
4048 inquiry.Flags[0] = IPS_SCSI_INQ_Address16;
4049 inquiry.Flags[1] =
4050 IPS_SCSI_INQ_WBus16 | IPS_SCSI_INQ_Sync | IPS_SCSI_INQ_CmdQue;
4051 strncpy(inquiry.VendorId, "IBM ", 8);
4052 strncpy(inquiry.ProductId, "SERVERAID ", 16);
4053 strncpy(inquiry.ProductRevisionLevel, "1.00", 4);
4054
4055 ips_scmd_buf_write(scb->scsi_cmd, &inquiry, sizeof (inquiry));
4056
4057 return (1);
4058}
4059
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069static int
4070ips_rdcap(ips_ha_t * ha, ips_scb_t * scb)
4071{
4072 IPS_SCSI_CAPACITY cap;
4073
4074 METHOD_TRACE("ips_rdcap", 1);
4075
4076 if (scsi_bufflen(scb->scsi_cmd) < 8)
4077 return (0);
4078
4079 cap.lba =
4080 cpu_to_be32(le32_to_cpu
4081 (ha->logical_drive_info->
4082 drive_info[scb->target_id].sector_count) - 1);
4083 cap.len = cpu_to_be32((uint32_t) IPS_BLKSIZE);
4084
4085 ips_scmd_buf_write(scb->scsi_cmd, &cap, sizeof (cap));
4086
4087 return (1);
4088}
4089
4090
4091
4092
4093
4094
4095
4096
4097
4098
4099static int
4100ips_msense(ips_ha_t * ha, ips_scb_t * scb)
4101{
4102 uint16_t heads;
4103 uint16_t sectors;
4104 uint32_t cylinders;
4105 IPS_SCSI_MODE_PAGE_DATA mdata;
4106
4107 METHOD_TRACE("ips_msense", 1);
4108
4109 if (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) > 0x400000 &&
4110 (ha->enq->ucMiscFlag & 0x8) == 0) {
4111 heads = IPS_NORM_HEADS;
4112 sectors = IPS_NORM_SECTORS;
4113 } else {
4114 heads = IPS_COMP_HEADS;
4115 sectors = IPS_COMP_SECTORS;
4116 }
4117
4118 cylinders =
4119 (le32_to_cpu(ha->enq->ulDriveSize[scb->target_id]) -
4120 1) / (heads * sectors);
4121
4122 memset(&mdata, 0, sizeof (IPS_SCSI_MODE_PAGE_DATA));
4123
4124 mdata.hdr.BlockDescLength = 8;
4125
4126 switch (scb->scsi_cmd->cmnd[2] & 0x3f) {
4127 case 0x03:
4128 mdata.pdata.pg3.PageCode = 3;
4129 mdata.pdata.pg3.PageLength = sizeof (IPS_SCSI_MODE_PAGE3);
4130 mdata.hdr.DataLength =
4131 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg3.PageLength;
4132 mdata.pdata.pg3.TracksPerZone = 0;
4133 mdata.pdata.pg3.AltSectorsPerZone = 0;
4134 mdata.pdata.pg3.AltTracksPerZone = 0;
4135 mdata.pdata.pg3.AltTracksPerVolume = 0;
4136 mdata.pdata.pg3.SectorsPerTrack = cpu_to_be16(sectors);
4137 mdata.pdata.pg3.BytesPerSector = cpu_to_be16(IPS_BLKSIZE);
4138 mdata.pdata.pg3.Interleave = cpu_to_be16(1);
4139 mdata.pdata.pg3.TrackSkew = 0;
4140 mdata.pdata.pg3.CylinderSkew = 0;
4141 mdata.pdata.pg3.flags = IPS_SCSI_MP3_SoftSector;
4142 break;
4143
4144 case 0x4:
4145 mdata.pdata.pg4.PageCode = 4;
4146 mdata.pdata.pg4.PageLength = sizeof (IPS_SCSI_MODE_PAGE4);
4147 mdata.hdr.DataLength =
4148 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg4.PageLength;
4149 mdata.pdata.pg4.CylindersHigh =
4150 cpu_to_be16((cylinders >> 8) & 0xFFFF);
4151 mdata.pdata.pg4.CylindersLow = (cylinders & 0xFF);
4152 mdata.pdata.pg4.Heads = heads;
4153 mdata.pdata.pg4.WritePrecompHigh = 0;
4154 mdata.pdata.pg4.WritePrecompLow = 0;
4155 mdata.pdata.pg4.ReducedWriteCurrentHigh = 0;
4156 mdata.pdata.pg4.ReducedWriteCurrentLow = 0;
4157 mdata.pdata.pg4.StepRate = cpu_to_be16(1);
4158 mdata.pdata.pg4.LandingZoneHigh = 0;
4159 mdata.pdata.pg4.LandingZoneLow = 0;
4160 mdata.pdata.pg4.flags = 0;
4161 mdata.pdata.pg4.RotationalOffset = 0;
4162 mdata.pdata.pg4.MediumRotationRate = 0;
4163 break;
4164 case 0x8:
4165 mdata.pdata.pg8.PageCode = 8;
4166 mdata.pdata.pg8.PageLength = sizeof (IPS_SCSI_MODE_PAGE8);
4167 mdata.hdr.DataLength =
4168 3 + mdata.hdr.BlockDescLength + mdata.pdata.pg8.PageLength;
4169
4170 break;
4171
4172 default:
4173 return (0);
4174 }
4175
4176 ips_scmd_buf_write(scb->scsi_cmd, &mdata, sizeof (mdata));
4177
4178 return (1);
4179}
4180
4181
4182
4183
4184
4185
4186
4187
4188
4189
4190static int
4191ips_reqsen(ips_ha_t * ha, ips_scb_t * scb)
4192{
4193 IPS_SCSI_REQSEN reqsen;
4194
4195 METHOD_TRACE("ips_reqsen", 1);
4196
4197 memset(&reqsen, 0, sizeof (IPS_SCSI_REQSEN));
4198
4199 reqsen.ResponseCode =
4200 IPS_SCSI_REQSEN_VALID | IPS_SCSI_REQSEN_CURRENT_ERR;
4201 reqsen.AdditionalLength = 10;
4202 reqsen.AdditionalSenseCode = IPS_SCSI_REQSEN_NO_SENSE;
4203 reqsen.AdditionalSenseCodeQual = IPS_SCSI_REQSEN_NO_SENSE;
4204
4205 ips_scmd_buf_write(scb->scsi_cmd, &reqsen, sizeof (reqsen));
4206
4207 return (1);
4208}
4209
4210
4211
4212
4213
4214
4215
4216
4217
4218
4219static void
4220ips_free(ips_ha_t * ha)
4221{
4222
4223 METHOD_TRACE("ips_free", 1);
4224
4225 if (ha) {
4226 if (ha->enq) {
4227 pci_free_consistent(ha->pcidev, sizeof(IPS_ENQ),
4228 ha->enq, ha->enq_busaddr);
4229 ha->enq = NULL;
4230 }
4231
4232 kfree(ha->conf);
4233 ha->conf = NULL;
4234
4235 if (ha->adapt) {
4236 pci_free_consistent(ha->pcidev,
4237 sizeof (IPS_ADAPTER) +
4238 sizeof (IPS_IO_CMD), ha->adapt,
4239 ha->adapt->hw_status_start);
4240 ha->adapt = NULL;
4241 }
4242
4243 if (ha->logical_drive_info) {
4244 pci_free_consistent(ha->pcidev,
4245 sizeof (IPS_LD_INFO),
4246 ha->logical_drive_info,
4247 ha->logical_drive_info_dma_addr);
4248 ha->logical_drive_info = NULL;
4249 }
4250
4251 kfree(ha->nvram);
4252 ha->nvram = NULL;
4253
4254 kfree(ha->subsys);
4255 ha->subsys = NULL;
4256
4257 if (ha->ioctl_data) {
4258 pci_free_consistent(ha->pcidev, ha->ioctl_len,
4259 ha->ioctl_data, ha->ioctl_busaddr);
4260 ha->ioctl_data = NULL;
4261 ha->ioctl_datasize = 0;
4262 ha->ioctl_len = 0;
4263 }
4264 ips_deallocatescbs(ha, ha->max_cmds);
4265
4266
4267 if (ha->mem_ptr) {
4268 iounmap(ha->ioremap_ptr);
4269 ha->ioremap_ptr = NULL;
4270 ha->mem_ptr = NULL;
4271 }
4272
4273 ha->mem_addr = 0;
4274
4275 }
4276}
4277
4278
4279
4280
4281
4282
4283
4284
4285
4286
4287static int
4288ips_deallocatescbs(ips_ha_t * ha, int cmds)
4289{
4290 if (ha->scbs) {
4291 pci_free_consistent(ha->pcidev,
4292 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * cmds,
4293 ha->scbs->sg_list.list,
4294 ha->scbs->sg_busaddr);
4295 pci_free_consistent(ha->pcidev, sizeof (ips_scb_t) * cmds,
4296 ha->scbs, ha->scbs->scb_busaddr);
4297 ha->scbs = NULL;
4298 }
4299 return 1;
4300}
4301
4302
4303
4304
4305
4306
4307
4308
4309
4310
4311static int
4312ips_allocatescbs(ips_ha_t * ha)
4313{
4314 ips_scb_t *scb_p;
4315 IPS_SG_LIST ips_sg;
4316 int i;
4317 dma_addr_t command_dma, sg_dma;
4318
4319 METHOD_TRACE("ips_allocatescbs", 1);
4320
4321
4322 ha->scbs =
4323 pci_alloc_consistent(ha->pcidev, ha->max_cmds * sizeof (ips_scb_t),
4324 &command_dma);
4325 if (ha->scbs == NULL)
4326 return 0;
4327 ips_sg.list =
4328 pci_alloc_consistent(ha->pcidev,
4329 IPS_SGLIST_SIZE(ha) * IPS_MAX_SG *
4330 ha->max_cmds, &sg_dma);
4331 if (ips_sg.list == NULL) {
4332 pci_free_consistent(ha->pcidev,
4333 ha->max_cmds * sizeof (ips_scb_t), ha->scbs,
4334 command_dma);
4335 return 0;
4336 }
4337
4338 memset(ha->scbs, 0, ha->max_cmds * sizeof (ips_scb_t));
4339
4340 for (i = 0; i < ha->max_cmds; i++) {
4341 scb_p = &ha->scbs[i];
4342 scb_p->scb_busaddr = command_dma + sizeof (ips_scb_t) * i;
4343
4344 if (IPS_USE_ENH_SGLIST(ha)) {
4345 scb_p->sg_list.enh_list =
4346 ips_sg.enh_list + i * IPS_MAX_SG;
4347 scb_p->sg_busaddr =
4348 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4349 } else {
4350 scb_p->sg_list.std_list =
4351 ips_sg.std_list + i * IPS_MAX_SG;
4352 scb_p->sg_busaddr =
4353 sg_dma + IPS_SGLIST_SIZE(ha) * IPS_MAX_SG * i;
4354 }
4355
4356
4357 if (i < ha->max_cmds - 1) {
4358 scb_p->q_next = ha->scb_freelist;
4359 ha->scb_freelist = scb_p;
4360 }
4361 }
4362
4363
4364 return (1);
4365}
4366
4367
4368
4369
4370
4371
4372
4373
4374
4375
4376static void
4377ips_init_scb(ips_ha_t * ha, ips_scb_t * scb)
4378{
4379 IPS_SG_LIST sg_list;
4380 uint32_t cmd_busaddr, sg_busaddr;
4381 METHOD_TRACE("ips_init_scb", 1);
4382
4383 if (scb == NULL)
4384 return;
4385
4386 sg_list.list = scb->sg_list.list;
4387 cmd_busaddr = scb->scb_busaddr;
4388 sg_busaddr = scb->sg_busaddr;
4389
4390 memset(scb, 0, sizeof (ips_scb_t));
4391 memset(ha->dummy, 0, sizeof (IPS_IO_CMD));
4392
4393
4394 ha->dummy->op_code = 0xFF;
4395 ha->dummy->ccsar = cpu_to_le32(ha->adapt->hw_status_start
4396 + sizeof (IPS_ADAPTER));
4397 ha->dummy->command_id = IPS_MAX_CMDS;
4398
4399
4400 scb->scb_busaddr = cmd_busaddr;
4401 scb->sg_busaddr = sg_busaddr;
4402 scb->sg_list.list = sg_list.list;
4403
4404
4405 scb->cmd.basic_io.cccr = cpu_to_le32((uint32_t) IPS_BIT_ILE);
4406 scb->cmd.basic_io.ccsar = cpu_to_le32(ha->adapt->hw_status_start
4407 + sizeof (IPS_ADAPTER));
4408}
4409
4410
4411
4412
4413
4414
4415
4416
4417
4418
4419
4420
4421static ips_scb_t *
4422ips_getscb(ips_ha_t * ha)
4423{
4424 ips_scb_t *scb;
4425
4426 METHOD_TRACE("ips_getscb", 1);
4427
4428 if ((scb = ha->scb_freelist) == NULL) {
4429
4430 return (NULL);
4431 }
4432
4433 ha->scb_freelist = scb->q_next;
4434 scb->flags = 0;
4435 scb->q_next = NULL;
4436
4437 ips_init_scb(ha, scb);
4438
4439 return (scb);
4440}
4441
4442
4443
4444
4445
4446
4447
4448
4449
4450
4451
4452
4453static void
4454ips_freescb(ips_ha_t * ha, ips_scb_t * scb)
4455{
4456
4457 METHOD_TRACE("ips_freescb", 1);
4458 if (scb->flags & IPS_SCB_MAP_SG)
4459 scsi_dma_unmap(scb->scsi_cmd);
4460 else if (scb->flags & IPS_SCB_MAP_SINGLE)
4461 pci_unmap_single(ha->pcidev, scb->data_busaddr, scb->data_len,
4462 IPS_DMA_DIR(scb));
4463
4464
4465 if (IPS_COMMAND_ID(ha, scb) < (ha->max_cmds - 1)) {
4466 scb->q_next = ha->scb_freelist;
4467 ha->scb_freelist = scb;
4468 }
4469}
4470
4471
4472
4473
4474
4475
4476
4477
4478
4479
4480static int
4481ips_isinit_copperhead(ips_ha_t * ha)
4482{
4483 uint8_t scpr;
4484 uint8_t isr;
4485
4486 METHOD_TRACE("ips_isinit_copperhead", 1);
4487
4488 isr = inb(ha->io_addr + IPS_REG_HISR);
4489 scpr = inb(ha->io_addr + IPS_REG_SCPR);
4490
4491 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4492 return (0);
4493 else
4494 return (1);
4495}
4496
4497
4498
4499
4500
4501
4502
4503
4504
4505
4506static int
4507ips_isinit_copperhead_memio(ips_ha_t * ha)
4508{
4509 uint8_t isr = 0;
4510 uint8_t scpr;
4511
4512 METHOD_TRACE("ips_is_init_copperhead_memio", 1);
4513
4514 isr = readb(ha->mem_ptr + IPS_REG_HISR);
4515 scpr = readb(ha->mem_ptr + IPS_REG_SCPR);
4516
4517 if (((isr & IPS_BIT_EI) == 0) && ((scpr & IPS_BIT_EBM) == 0))
4518 return (0);
4519 else
4520 return (1);
4521}
4522
4523
4524
4525
4526
4527
4528
4529
4530
4531
4532static int
4533ips_isinit_morpheus(ips_ha_t * ha)
4534{
4535 uint32_t post;
4536 uint32_t bits;
4537
4538 METHOD_TRACE("ips_is_init_morpheus", 1);
4539
4540 if (ips_isintr_morpheus(ha))
4541 ips_flush_and_reset(ha);
4542
4543 post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4544 bits = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4545
4546 if (post == 0)
4547 return (0);
4548 else if (bits & 0x3)
4549 return (0);
4550 else
4551 return (1);
4552}
4553
4554
4555
4556
4557
4558
4559
4560
4561
4562
4563
4564static void
4565ips_flush_and_reset(ips_ha_t *ha)
4566{
4567 ips_scb_t *scb;
4568 int ret;
4569 int time;
4570 int done;
4571 dma_addr_t command_dma;
4572
4573
4574 scb = pci_alloc_consistent(ha->pcidev, sizeof(ips_scb_t), &command_dma);
4575 if (scb) {
4576 memset(scb, 0, sizeof(ips_scb_t));
4577 ips_init_scb(ha, scb);
4578 scb->scb_busaddr = command_dma;
4579
4580 scb->timeout = ips_cmd_timeout;
4581 scb->cdb[0] = IPS_CMD_FLUSH;
4582
4583 scb->cmd.flush_cache.op_code = IPS_CMD_FLUSH;
4584 scb->cmd.flush_cache.command_id = IPS_MAX_CMDS;
4585 scb->cmd.flush_cache.state = IPS_NORM_STATE;
4586 scb->cmd.flush_cache.reserved = 0;
4587 scb->cmd.flush_cache.reserved2 = 0;
4588 scb->cmd.flush_cache.reserved3 = 0;
4589 scb->cmd.flush_cache.reserved4 = 0;
4590
4591 ret = ips_send_cmd(ha, scb);
4592
4593 if (ret == IPS_SUCCESS) {
4594 time = 60 * IPS_ONE_SEC;
4595 done = 0;
4596
4597 while ((time > 0) && (!done)) {
4598 done = ips_poll_for_flush_complete(ha);
4599
4600 udelay(1000);
4601 time--;
4602 }
4603 }
4604 }
4605
4606
4607 (*ha->func.reset) (ha);
4608
4609 pci_free_consistent(ha->pcidev, sizeof(ips_scb_t), scb, command_dma);
4610 return;
4611}
4612
4613
4614
4615
4616
4617
4618
4619
4620
4621
4622
4623static int
4624ips_poll_for_flush_complete(ips_ha_t * ha)
4625{
4626 IPS_STATUS cstatus;
4627
4628 while (TRUE) {
4629 cstatus.value = (*ha->func.statupd) (ha);
4630
4631 if (cstatus.value == 0xffffffff)
4632 break;
4633
4634
4635 if (cstatus.fields.command_id == IPS_MAX_CMDS)
4636 return 1;
4637 }
4638
4639 return 0;
4640}
4641
4642
4643
4644
4645
4646
4647
4648
4649
4650static void
4651ips_enable_int_copperhead(ips_ha_t * ha)
4652{
4653 METHOD_TRACE("ips_enable_int_copperhead", 1);
4654
4655 outb(ha->io_addr + IPS_REG_HISR, IPS_BIT_EI);
4656 inb(ha->io_addr + IPS_REG_HISR);
4657}
4658
4659
4660
4661
4662
4663
4664
4665
4666
4667static void
4668ips_enable_int_copperhead_memio(ips_ha_t * ha)
4669{
4670 METHOD_TRACE("ips_enable_int_copperhead_memio", 1);
4671
4672 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4673 readb(ha->mem_ptr + IPS_REG_HISR);
4674}
4675
4676
4677
4678
4679
4680
4681
4682
4683
4684static void
4685ips_enable_int_morpheus(ips_ha_t * ha)
4686{
4687 uint32_t Oimr;
4688
4689 METHOD_TRACE("ips_enable_int_morpheus", 1);
4690
4691 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4692 Oimr &= ~0x08;
4693 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4694 readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4695}
4696
4697
4698
4699
4700
4701
4702
4703
4704
4705
4706static int
4707ips_init_copperhead(ips_ha_t * ha)
4708{
4709 uint8_t Isr;
4710 uint8_t Cbsp;
4711 uint8_t PostByte[IPS_MAX_POST_BYTES];
4712 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES];
4713 int i, j;
4714
4715 METHOD_TRACE("ips_init_copperhead", 1);
4716
4717 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4718 for (j = 0; j < 45; j++) {
4719 Isr = inb(ha->io_addr + IPS_REG_HISR);
4720 if (Isr & IPS_BIT_GHI)
4721 break;
4722
4723
4724 MDELAY(IPS_ONE_SEC);
4725 }
4726
4727 if (j >= 45)
4728
4729 return (0);
4730
4731 PostByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4732 outb(Isr, ha->io_addr + IPS_REG_HISR);
4733 }
4734
4735 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4736 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4737 "reset controller fails (post status %x %x).\n",
4738 PostByte[0], PostByte[1]);
4739
4740 return (0);
4741 }
4742
4743 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4744 for (j = 0; j < 240; j++) {
4745 Isr = inb(ha->io_addr + IPS_REG_HISR);
4746 if (Isr & IPS_BIT_GHI)
4747 break;
4748
4749
4750 MDELAY(IPS_ONE_SEC);
4751 }
4752
4753 if (j >= 240)
4754
4755 return (0);
4756
4757 ConfigByte[i] = inb(ha->io_addr + IPS_REG_ISPR);
4758 outb(Isr, ha->io_addr + IPS_REG_HISR);
4759 }
4760
4761 for (i = 0; i < 240; i++) {
4762 Cbsp = inb(ha->io_addr + IPS_REG_CBSP);
4763
4764 if ((Cbsp & IPS_BIT_OP) == 0)
4765 break;
4766
4767
4768 MDELAY(IPS_ONE_SEC);
4769 }
4770
4771 if (i >= 240)
4772
4773 return (0);
4774
4775
4776 outl(0x1010, ha->io_addr + IPS_REG_CCCR);
4777
4778
4779 outb(IPS_BIT_EBM, ha->io_addr + IPS_REG_SCPR);
4780
4781 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
4782
4783 outl(0, ha->io_addr + IPS_REG_NDAE);
4784
4785
4786 outb(IPS_BIT_EI, ha->io_addr + IPS_REG_HISR);
4787
4788 return (1);
4789}
4790
4791
4792
4793
4794
4795
4796
4797
4798
4799
4800static int
4801ips_init_copperhead_memio(ips_ha_t * ha)
4802{
4803 uint8_t Isr = 0;
4804 uint8_t Cbsp;
4805 uint8_t PostByte[IPS_MAX_POST_BYTES];
4806 uint8_t ConfigByte[IPS_MAX_CONFIG_BYTES];
4807 int i, j;
4808
4809 METHOD_TRACE("ips_init_copperhead_memio", 1);
4810
4811 for (i = 0; i < IPS_MAX_POST_BYTES; i++) {
4812 for (j = 0; j < 45; j++) {
4813 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4814 if (Isr & IPS_BIT_GHI)
4815 break;
4816
4817
4818 MDELAY(IPS_ONE_SEC);
4819 }
4820
4821 if (j >= 45)
4822
4823 return (0);
4824
4825 PostByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
4826 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4827 }
4828
4829 if (PostByte[0] < IPS_GOOD_POST_STATUS) {
4830 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4831 "reset controller fails (post status %x %x).\n",
4832 PostByte[0], PostByte[1]);
4833
4834 return (0);
4835 }
4836
4837 for (i = 0; i < IPS_MAX_CONFIG_BYTES; i++) {
4838 for (j = 0; j < 240; j++) {
4839 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
4840 if (Isr & IPS_BIT_GHI)
4841 break;
4842
4843
4844 MDELAY(IPS_ONE_SEC);
4845 }
4846
4847 if (j >= 240)
4848
4849 return (0);
4850
4851 ConfigByte[i] = readb(ha->mem_ptr + IPS_REG_ISPR);
4852 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
4853 }
4854
4855 for (i = 0; i < 240; i++) {
4856 Cbsp = readb(ha->mem_ptr + IPS_REG_CBSP);
4857
4858 if ((Cbsp & IPS_BIT_OP) == 0)
4859 break;
4860
4861
4862 MDELAY(IPS_ONE_SEC);
4863 }
4864
4865 if (i >= 240)
4866
4867 return (0);
4868
4869
4870 writel(0x1010, ha->mem_ptr + IPS_REG_CCCR);
4871
4872
4873 writeb(IPS_BIT_EBM, ha->mem_ptr + IPS_REG_SCPR);
4874
4875 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
4876
4877 writel(0, ha->mem_ptr + IPS_REG_NDAE);
4878
4879
4880 writeb(IPS_BIT_EI, ha->mem_ptr + IPS_REG_HISR);
4881
4882
4883 return (1);
4884}
4885
4886
4887
4888
4889
4890
4891
4892
4893
4894
4895static int
4896ips_init_morpheus(ips_ha_t * ha)
4897{
4898 uint32_t Post;
4899 uint32_t Config;
4900 uint32_t Isr;
4901 uint32_t Oimr;
4902 int i;
4903
4904 METHOD_TRACE("ips_init_morpheus", 1);
4905
4906
4907 for (i = 0; i < 45; i++) {
4908 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4909
4910 if (Isr & IPS_BIT_I960_MSG0I)
4911 break;
4912
4913
4914 MDELAY(IPS_ONE_SEC);
4915 }
4916
4917 if (i >= 45) {
4918
4919 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4920 "timeout waiting for post.\n");
4921
4922 return (0);
4923 }
4924
4925 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4926
4927 if (Post == 0x4F00) {
4928 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4929 "Flashing Battery PIC, Please wait ...\n");
4930
4931
4932 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
4933 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4934
4935 for (i = 0; i < 120; i++) {
4936 Post = readl(ha->mem_ptr + IPS_REG_I960_MSG0);
4937 if (Post != 0x4F00)
4938 break;
4939
4940 MDELAY(IPS_ONE_SEC);
4941 }
4942
4943 if (i >= 120) {
4944 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4945 "timeout waiting for Battery PIC Flash\n");
4946 return (0);
4947 }
4948
4949 }
4950
4951
4952 Isr = (uint32_t) IPS_BIT_I960_MSG0I;
4953 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4954
4955 if (Post < (IPS_GOOD_POST_STATUS << 8)) {
4956 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4957 "reset controller fails (post status %x).\n", Post);
4958
4959 return (0);
4960 }
4961
4962
4963 for (i = 0; i < 240; i++) {
4964 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
4965
4966 if (Isr & IPS_BIT_I960_MSG1I)
4967 break;
4968
4969
4970 MDELAY(IPS_ONE_SEC);
4971 }
4972
4973 if (i >= 240) {
4974
4975 IPS_PRINTK(KERN_WARNING, ha->pcidev,
4976 "timeout waiting for config.\n");
4977
4978 return (0);
4979 }
4980
4981 Config = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
4982
4983
4984 Isr = (uint32_t) IPS_BIT_I960_MSG1I;
4985 writel(Isr, ha->mem_ptr + IPS_REG_I2O_HIR);
4986
4987
4988 Oimr = readl(ha->mem_ptr + IPS_REG_I960_OIMR);
4989 Oimr &= ~0x8;
4990 writel(Oimr, ha->mem_ptr + IPS_REG_I960_OIMR);
4991
4992
4993
4994
4995 if (Post == 0xEF10) {
4996 if ((Config == 0x000F) || (Config == 0x0009))
4997 ha->requires_esl = 1;
4998 }
4999
5000 return (1);
5001}
5002
5003
5004
5005
5006
5007
5008
5009
5010
5011
5012static int
5013ips_reset_copperhead(ips_ha_t * ha)
5014{
5015 int reset_counter;
5016
5017 METHOD_TRACE("ips_reset_copperhead", 1);
5018
5019 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead: io addr: %x, irq: %d",
5020 ips_name, ha->host_num, ha->io_addr, ha->pcidev->irq);
5021
5022 reset_counter = 0;
5023
5024 while (reset_counter < 2) {
5025 reset_counter++;
5026
5027 outb(IPS_BIT_RST, ha->io_addr + IPS_REG_SCPR);
5028
5029
5030 MDELAY(IPS_ONE_SEC);
5031
5032 outb(0, ha->io_addr + IPS_REG_SCPR);
5033
5034
5035 MDELAY(IPS_ONE_SEC);
5036
5037 if ((*ha->func.init) (ha))
5038 break;
5039 else if (reset_counter >= 2) {
5040
5041 return (0);
5042 }
5043 }
5044
5045 return (1);
5046}
5047
5048
5049
5050
5051
5052
5053
5054
5055
5056
5057static int
5058ips_reset_copperhead_memio(ips_ha_t * ha)
5059{
5060 int reset_counter;
5061
5062 METHOD_TRACE("ips_reset_copperhead_memio", 1);
5063
5064 DEBUG_VAR(1, "(%s%d) ips_reset_copperhead_memio: mem addr: %x, irq: %d",
5065 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq);
5066
5067 reset_counter = 0;
5068
5069 while (reset_counter < 2) {
5070 reset_counter++;
5071
5072 writeb(IPS_BIT_RST, ha->mem_ptr + IPS_REG_SCPR);
5073
5074
5075 MDELAY(IPS_ONE_SEC);
5076
5077 writeb(0, ha->mem_ptr + IPS_REG_SCPR);
5078
5079
5080 MDELAY(IPS_ONE_SEC);
5081
5082 if ((*ha->func.init) (ha))
5083 break;
5084 else if (reset_counter >= 2) {
5085
5086 return (0);
5087 }
5088 }
5089
5090 return (1);
5091}
5092
5093
5094
5095
5096
5097
5098
5099
5100
5101
5102static int
5103ips_reset_morpheus(ips_ha_t * ha)
5104{
5105 int reset_counter;
5106 uint8_t junk;
5107
5108 METHOD_TRACE("ips_reset_morpheus", 1);
5109
5110 DEBUG_VAR(1, "(%s%d) ips_reset_morpheus: mem addr: %x, irq: %d",
5111 ips_name, ha->host_num, ha->mem_addr, ha->pcidev->irq);
5112
5113 reset_counter = 0;
5114
5115 while (reset_counter < 2) {
5116 reset_counter++;
5117
5118 writel(0x80000000, ha->mem_ptr + IPS_REG_I960_IDR);
5119
5120
5121 MDELAY(5 * IPS_ONE_SEC);
5122
5123
5124 pci_read_config_byte(ha->pcidev, 4, &junk);
5125
5126 if ((*ha->func.init) (ha))
5127 break;
5128 else if (reset_counter >= 2) {
5129
5130 return (0);
5131 }
5132 }
5133
5134 return (1);
5135}
5136
5137
5138
5139
5140
5141
5142
5143
5144
5145
5146static void
5147ips_statinit(ips_ha_t * ha)
5148{
5149 uint32_t phys_status_start;
5150
5151 METHOD_TRACE("ips_statinit", 1);
5152
5153 ha->adapt->p_status_start = ha->adapt->status;
5154 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5155 ha->adapt->p_status_tail = ha->adapt->status;
5156
5157 phys_status_start = ha->adapt->hw_status_start;
5158 outl(phys_status_start, ha->io_addr + IPS_REG_SQSR);
5159 outl(phys_status_start + IPS_STATUS_Q_SIZE,
5160 ha->io_addr + IPS_REG_SQER);
5161 outl(phys_status_start + IPS_STATUS_SIZE,
5162 ha->io_addr + IPS_REG_SQHR);
5163 outl(phys_status_start, ha->io_addr + IPS_REG_SQTR);
5164
5165 ha->adapt->hw_status_tail = phys_status_start;
5166}
5167
5168
5169
5170
5171
5172
5173
5174
5175
5176
5177static void
5178ips_statinit_memio(ips_ha_t * ha)
5179{
5180 uint32_t phys_status_start;
5181
5182 METHOD_TRACE("ips_statinit_memio", 1);
5183
5184 ha->adapt->p_status_start = ha->adapt->status;
5185 ha->adapt->p_status_end = ha->adapt->status + IPS_MAX_CMDS;
5186 ha->adapt->p_status_tail = ha->adapt->status;
5187
5188 phys_status_start = ha->adapt->hw_status_start;
5189 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQSR);
5190 writel(phys_status_start + IPS_STATUS_Q_SIZE,
5191 ha->mem_ptr + IPS_REG_SQER);
5192 writel(phys_status_start + IPS_STATUS_SIZE, ha->mem_ptr + IPS_REG_SQHR);
5193 writel(phys_status_start, ha->mem_ptr + IPS_REG_SQTR);
5194
5195 ha->adapt->hw_status_tail = phys_status_start;
5196}
5197
5198
5199
5200
5201
5202
5203
5204
5205
5206
5207static uint32_t
5208ips_statupd_copperhead(ips_ha_t * ha)
5209{
5210 METHOD_TRACE("ips_statupd_copperhead", 1);
5211
5212 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5213 ha->adapt->p_status_tail++;
5214 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5215 } else {
5216 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5217 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5218 }
5219
5220 outl(ha->adapt->hw_status_tail,
5221 ha->io_addr + IPS_REG_SQTR);
5222
5223 return (ha->adapt->p_status_tail->value);
5224}
5225
5226
5227
5228
5229
5230
5231
5232
5233
5234
5235static uint32_t
5236ips_statupd_copperhead_memio(ips_ha_t * ha)
5237{
5238 METHOD_TRACE("ips_statupd_copperhead_memio", 1);
5239
5240 if (ha->adapt->p_status_tail != ha->adapt->p_status_end) {
5241 ha->adapt->p_status_tail++;
5242 ha->adapt->hw_status_tail += sizeof (IPS_STATUS);
5243 } else {
5244 ha->adapt->p_status_tail = ha->adapt->p_status_start;
5245 ha->adapt->hw_status_tail = ha->adapt->hw_status_start;
5246 }
5247
5248 writel(ha->adapt->hw_status_tail, ha->mem_ptr + IPS_REG_SQTR);
5249
5250 return (ha->adapt->p_status_tail->value);
5251}
5252
5253
5254
5255
5256
5257
5258
5259
5260
5261
5262static uint32_t
5263ips_statupd_morpheus(ips_ha_t * ha)
5264{
5265 uint32_t val;
5266
5267 METHOD_TRACE("ips_statupd_morpheus", 1);
5268
5269 val = readl(ha->mem_ptr + IPS_REG_I2O_OUTMSGQ);
5270
5271 return (val);
5272}
5273
5274
5275
5276
5277
5278
5279
5280
5281
5282
5283static int
5284ips_issue_copperhead(ips_ha_t * ha, ips_scb_t * scb)
5285{
5286 uint32_t TimeOut;
5287 uint32_t val;
5288
5289 METHOD_TRACE("ips_issue_copperhead", 1);
5290
5291 if (scb->scsi_cmd) {
5292 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5293 ips_name,
5294 ha->host_num,
5295 scb->cdb[0],
5296 scb->cmd.basic_io.command_id,
5297 scb->bus, scb->target_id, scb->lun);
5298 } else {
5299 DEBUG_VAR(2, KERN_NOTICE "(%s%d) ips_issue: logical cmd id %d",
5300 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5301 }
5302
5303 TimeOut = 0;
5304
5305 while ((val =
5306 le32_to_cpu(inl(ha->io_addr + IPS_REG_CCCR))) & IPS_BIT_SEM) {
5307 udelay(1000);
5308
5309 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5310 if (!(val & IPS_BIT_START_STOP))
5311 break;
5312
5313 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5314 "ips_issue val [0x%x].\n", val);
5315 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5316 "ips_issue semaphore chk timeout.\n");
5317
5318 return (IPS_FAILURE);
5319 }
5320 }
5321
5322 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_CCSAR);
5323 outw(IPS_BIT_START_CMD, ha->io_addr + IPS_REG_CCCR);
5324
5325 return (IPS_SUCCESS);
5326}
5327
5328
5329
5330
5331
5332
5333
5334
5335
5336
5337static int
5338ips_issue_copperhead_memio(ips_ha_t * ha, ips_scb_t * scb)
5339{
5340 uint32_t TimeOut;
5341 uint32_t val;
5342
5343 METHOD_TRACE("ips_issue_copperhead_memio", 1);
5344
5345 if (scb->scsi_cmd) {
5346 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5347 ips_name,
5348 ha->host_num,
5349 scb->cdb[0],
5350 scb->cmd.basic_io.command_id,
5351 scb->bus, scb->target_id, scb->lun);
5352 } else {
5353 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5354 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5355 }
5356
5357 TimeOut = 0;
5358
5359 while ((val = readl(ha->mem_ptr + IPS_REG_CCCR)) & IPS_BIT_SEM) {
5360 udelay(1000);
5361
5362 if (++TimeOut >= IPS_SEM_TIMEOUT) {
5363 if (!(val & IPS_BIT_START_STOP))
5364 break;
5365
5366 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5367 "ips_issue val [0x%x].\n", val);
5368 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5369 "ips_issue semaphore chk timeout.\n");
5370
5371 return (IPS_FAILURE);
5372 }
5373 }
5374
5375 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_CCSAR);
5376 writel(IPS_BIT_START_CMD, ha->mem_ptr + IPS_REG_CCCR);
5377
5378 return (IPS_SUCCESS);
5379}
5380
5381
5382
5383
5384
5385
5386
5387
5388
5389
5390static int
5391ips_issue_i2o(ips_ha_t * ha, ips_scb_t * scb)
5392{
5393
5394 METHOD_TRACE("ips_issue_i2o", 1);
5395
5396 if (scb->scsi_cmd) {
5397 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5398 ips_name,
5399 ha->host_num,
5400 scb->cdb[0],
5401 scb->cmd.basic_io.command_id,
5402 scb->bus, scb->target_id, scb->lun);
5403 } else {
5404 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5405 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5406 }
5407
5408 outl(scb->scb_busaddr, ha->io_addr + IPS_REG_I2O_INMSGQ);
5409
5410 return (IPS_SUCCESS);
5411}
5412
5413
5414
5415
5416
5417
5418
5419
5420
5421
5422static int
5423ips_issue_i2o_memio(ips_ha_t * ha, ips_scb_t * scb)
5424{
5425
5426 METHOD_TRACE("ips_issue_i2o_memio", 1);
5427
5428 if (scb->scsi_cmd) {
5429 DEBUG_VAR(2, "(%s%d) ips_issue: cmd 0x%X id %d (%d %d %d)",
5430 ips_name,
5431 ha->host_num,
5432 scb->cdb[0],
5433 scb->cmd.basic_io.command_id,
5434 scb->bus, scb->target_id, scb->lun);
5435 } else {
5436 DEBUG_VAR(2, "(%s%d) ips_issue: logical cmd id %d",
5437 ips_name, ha->host_num, scb->cmd.basic_io.command_id);
5438 }
5439
5440 writel(scb->scb_busaddr, ha->mem_ptr + IPS_REG_I2O_INMSGQ);
5441
5442 return (IPS_SUCCESS);
5443}
5444
5445
5446
5447
5448
5449
5450
5451
5452
5453
5454static int
5455ips_isintr_copperhead(ips_ha_t * ha)
5456{
5457 uint8_t Isr;
5458
5459 METHOD_TRACE("ips_isintr_copperhead", 2);
5460
5461 Isr = inb(ha->io_addr + IPS_REG_HISR);
5462
5463 if (Isr == 0xFF)
5464
5465 return (0);
5466
5467 if (Isr & IPS_BIT_SCE)
5468 return (1);
5469 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5470
5471
5472 outb(Isr, ha->io_addr + IPS_REG_HISR);
5473 }
5474
5475 return (0);
5476}
5477
5478
5479
5480
5481
5482
5483
5484
5485
5486
5487static int
5488ips_isintr_copperhead_memio(ips_ha_t * ha)
5489{
5490 uint8_t Isr;
5491
5492 METHOD_TRACE("ips_isintr_memio", 2);
5493
5494 Isr = readb(ha->mem_ptr + IPS_REG_HISR);
5495
5496 if (Isr == 0xFF)
5497
5498 return (0);
5499
5500 if (Isr & IPS_BIT_SCE)
5501 return (1);
5502 else if (Isr & (IPS_BIT_SQO | IPS_BIT_GHI)) {
5503
5504
5505 writeb(Isr, ha->mem_ptr + IPS_REG_HISR);
5506 }
5507
5508 return (0);
5509}
5510
5511
5512
5513
5514
5515
5516
5517
5518
5519
5520static int
5521ips_isintr_morpheus(ips_ha_t * ha)
5522{
5523 uint32_t Isr;
5524
5525 METHOD_TRACE("ips_isintr_morpheus", 2);
5526
5527 Isr = readl(ha->mem_ptr + IPS_REG_I2O_HIR);
5528
5529 if (Isr & IPS_BIT_I2O_OPQI)
5530 return (1);
5531 else
5532 return (0);
5533}
5534
5535
5536
5537
5538
5539
5540
5541
5542
5543
5544static int
5545ips_wait(ips_ha_t * ha, int time, int intr)
5546{
5547 int ret;
5548 int done;
5549
5550 METHOD_TRACE("ips_wait", 1);
5551
5552 ret = IPS_FAILURE;
5553 done = FALSE;
5554
5555 time *= IPS_ONE_SEC;
5556
5557 while ((time > 0) && (!done)) {
5558 if (intr == IPS_INTR_ON) {
5559 if (ha->waitflag == FALSE) {
5560 ret = IPS_SUCCESS;
5561 done = TRUE;
5562 break;
5563 }
5564 } else if (intr == IPS_INTR_IORL) {
5565 if (ha->waitflag == FALSE) {
5566
5567
5568
5569
5570
5571 ret = IPS_SUCCESS;
5572 done = TRUE;
5573 break;
5574 }
5575
5576
5577
5578
5579
5580
5581
5582 (*ha->func.intr) (ha);
5583 }
5584
5585
5586 udelay(1000);
5587 time--;
5588 }
5589
5590 return (ret);
5591}
5592
5593
5594
5595
5596
5597
5598
5599
5600
5601
5602static int
5603ips_write_driver_status(ips_ha_t * ha, int intr)
5604{
5605 METHOD_TRACE("ips_write_driver_status", 1);
5606
5607 if (!ips_readwrite_page5(ha, FALSE, intr)) {
5608 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5609 "unable to read NVRAM page 5.\n");
5610
5611 return (0);
5612 }
5613
5614
5615
5616 if (le32_to_cpu(ha->nvram->signature) != IPS_NVRAM_P5_SIG) {
5617 DEBUG_VAR(1,
5618 "(%s%d) NVRAM page 5 has an invalid signature: %X.",
5619 ips_name, ha->host_num, ha->nvram->signature);
5620 ha->nvram->signature = IPS_NVRAM_P5_SIG;
5621 }
5622
5623 DEBUG_VAR(2,
5624 "(%s%d) Ad Type: %d, Ad Slot: %d, BIOS: %c%c%c%c %c%c%c%c.",
5625 ips_name, ha->host_num, le16_to_cpu(ha->nvram->adapter_type),
5626 ha->nvram->adapter_slot, ha->nvram->bios_high[0],
5627 ha->nvram->bios_high[1], ha->nvram->bios_high[2],
5628 ha->nvram->bios_high[3], ha->nvram->bios_low[0],
5629 ha->nvram->bios_low[1], ha->nvram->bios_low[2],
5630 ha->nvram->bios_low[3]);
5631
5632 ips_get_bios_version(ha, intr);
5633
5634
5635 ha->nvram->operating_system = IPS_OS_LINUX;
5636 ha->nvram->adapter_type = ha->ad_type;
5637 strncpy((char *) ha->nvram->driver_high, IPS_VERSION_HIGH, 4);
5638 strncpy((char *) ha->nvram->driver_low, IPS_VERSION_LOW, 4);
5639 strncpy((char *) ha->nvram->bios_high, ha->bios_version, 4);
5640 strncpy((char *) ha->nvram->bios_low, ha->bios_version + 4, 4);
5641
5642 ha->nvram->versioning = 0;
5643
5644
5645 if (!ips_readwrite_page5(ha, TRUE, intr)) {
5646 IPS_PRINTK(KERN_WARNING, ha->pcidev,
5647 "unable to write NVRAM page 5.\n");
5648
5649 return (0);
5650 }
5651
5652
5653 ha->slot_num = ha->nvram->adapter_slot;
5654
5655 return (1);
5656}
5657
5658
5659
5660
5661
5662
5663
5664
5665
5666
5667static int
5668ips_read_adapter_status(ips_ha_t * ha, int intr)
5669{
5670 ips_scb_t *scb;
5671 int ret;
5672
5673 METHOD_TRACE("ips_read_adapter_status", 1);
5674
5675 scb = &ha->scbs[ha->max_cmds - 1];
5676
5677 ips_init_scb(ha, scb);
5678
5679 scb->timeout = ips_cmd_timeout;
5680 scb->cdb[0] = IPS_CMD_ENQUIRY;
5681
5682 scb->cmd.basic_io.op_code = IPS_CMD_ENQUIRY;
5683 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5684 scb->cmd.basic_io.sg_count = 0;
5685 scb->cmd.basic_io.lba = 0;
5686 scb->cmd.basic_io.sector_count = 0;
5687 scb->cmd.basic_io.log_drv = 0;
5688 scb->data_len = sizeof (*ha->enq);
5689 scb->cmd.basic_io.sg_addr = ha->enq_busaddr;
5690
5691
5692 if (((ret =
5693 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5694 || (ret == IPS_SUCCESS_IMM)
5695 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5696 return (0);
5697
5698 return (1);
5699}
5700
5701
5702
5703
5704
5705
5706
5707
5708
5709
5710static int
5711ips_read_subsystem_parameters(ips_ha_t * ha, int intr)
5712{
5713 ips_scb_t *scb;
5714 int ret;
5715
5716 METHOD_TRACE("ips_read_subsystem_parameters", 1);
5717
5718 scb = &ha->scbs[ha->max_cmds - 1];
5719
5720 ips_init_scb(ha, scb);
5721
5722 scb->timeout = ips_cmd_timeout;
5723 scb->cdb[0] = IPS_CMD_GET_SUBSYS;
5724
5725 scb->cmd.basic_io.op_code = IPS_CMD_GET_SUBSYS;
5726 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5727 scb->cmd.basic_io.sg_count = 0;
5728 scb->cmd.basic_io.lba = 0;
5729 scb->cmd.basic_io.sector_count = 0;
5730 scb->cmd.basic_io.log_drv = 0;
5731 scb->data_len = sizeof (*ha->subsys);
5732 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5733
5734
5735 if (((ret =
5736 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5737 || (ret == IPS_SUCCESS_IMM)
5738 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5739 return (0);
5740
5741 memcpy(ha->subsys, ha->ioctl_data, sizeof(*ha->subsys));
5742 return (1);
5743}
5744
5745
5746
5747
5748
5749
5750
5751
5752
5753
5754static int
5755ips_read_config(ips_ha_t * ha, int intr)
5756{
5757 ips_scb_t *scb;
5758 int i;
5759 int ret;
5760
5761 METHOD_TRACE("ips_read_config", 1);
5762
5763
5764 for (i = 0; i < 4; i++)
5765 ha->conf->init_id[i] = 7;
5766
5767 scb = &ha->scbs[ha->max_cmds - 1];
5768
5769 ips_init_scb(ha, scb);
5770
5771 scb->timeout = ips_cmd_timeout;
5772 scb->cdb[0] = IPS_CMD_READ_CONF;
5773
5774 scb->cmd.basic_io.op_code = IPS_CMD_READ_CONF;
5775 scb->cmd.basic_io.command_id = IPS_COMMAND_ID(ha, scb);
5776 scb->data_len = sizeof (*ha->conf);
5777 scb->cmd.basic_io.sg_addr = ha->ioctl_busaddr;
5778
5779
5780 if (((ret =
5781 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5782 || (ret == IPS_SUCCESS_IMM)
5783 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5784
5785 memset(ha->conf, 0, sizeof (IPS_CONF));
5786
5787
5788 for (i = 0; i < 4; i++)
5789 ha->conf->init_id[i] = 7;
5790
5791
5792 if ((scb->basic_status & IPS_GSC_STATUS_MASK) ==
5793 IPS_CMD_CMPLT_WERROR)
5794 return (1);
5795
5796 return (0);
5797 }
5798
5799 memcpy(ha->conf, ha->ioctl_data, sizeof(*ha->conf));
5800 return (1);
5801}
5802
5803
5804
5805
5806
5807
5808
5809
5810
5811
5812static int
5813ips_readwrite_page5(ips_ha_t * ha, int write, int intr)
5814{
5815 ips_scb_t *scb;
5816 int ret;
5817
5818 METHOD_TRACE("ips_readwrite_page5", 1);
5819
5820 scb = &ha->scbs[ha->max_cmds - 1];
5821
5822 ips_init_scb(ha, scb);
5823
5824 scb->timeout = ips_cmd_timeout;
5825 scb->cdb[0] = IPS_CMD_RW_NVRAM_PAGE;
5826
5827 scb->cmd.nvram.op_code = IPS_CMD_RW_NVRAM_PAGE;
5828 scb->cmd.nvram.command_id = IPS_COMMAND_ID(ha, scb);
5829 scb->cmd.nvram.page = 5;
5830 scb->cmd.nvram.write = write;
5831 scb->cmd.nvram.reserved = 0;
5832 scb->cmd.nvram.reserved2 = 0;
5833 scb->data_len = sizeof (*ha->nvram);
5834 scb->cmd.nvram.buffer_addr = ha->ioctl_busaddr;
5835 if (write)
5836 memcpy(ha->ioctl_data, ha->nvram, sizeof(*ha->nvram));
5837
5838
5839 if (((ret =
5840 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5841 || (ret == IPS_SUCCESS_IMM)
5842 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1)) {
5843
5844 memset(ha->nvram, 0, sizeof (IPS_NVRAM_P5));
5845
5846 return (0);
5847 }
5848 if (!write)
5849 memcpy(ha->nvram, ha->ioctl_data, sizeof(*ha->nvram));
5850 return (1);
5851}
5852
5853
5854
5855
5856
5857
5858
5859
5860
5861
5862static int
5863ips_clear_adapter(ips_ha_t * ha, int intr)
5864{
5865 ips_scb_t *scb;
5866 int ret;
5867
5868 METHOD_TRACE("ips_clear_adapter", 1);
5869
5870 scb = &ha->scbs[ha->max_cmds - 1];
5871
5872 ips_init_scb(ha, scb);
5873
5874 scb->timeout = ips_reset_timeout;
5875 scb->cdb[0] = IPS_CMD_CONFIG_SYNC;
5876
5877 scb->cmd.config_sync.op_code = IPS_CMD_CONFIG_SYNC;
5878 scb->cmd.config_sync.command_id = IPS_COMMAND_ID(ha, scb);
5879 scb->cmd.config_sync.channel = 0;
5880 scb->cmd.config_sync.source_target = IPS_POCL;
5881 scb->cmd.config_sync.reserved = 0;
5882 scb->cmd.config_sync.reserved2 = 0;
5883 scb->cmd.config_sync.reserved3 = 0;
5884
5885
5886 if (((ret =
5887 ips_send_wait(ha, scb, ips_reset_timeout, intr)) == IPS_FAILURE)
5888 || (ret == IPS_SUCCESS_IMM)
5889 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5890 return (0);
5891
5892
5893 ips_init_scb(ha, scb);
5894
5895 scb->cdb[0] = IPS_CMD_ERROR_TABLE;
5896 scb->timeout = ips_reset_timeout;
5897
5898 scb->cmd.unlock_stripe.op_code = IPS_CMD_ERROR_TABLE;
5899 scb->cmd.unlock_stripe.command_id = IPS_COMMAND_ID(ha, scb);
5900 scb->cmd.unlock_stripe.log_drv = 0;
5901 scb->cmd.unlock_stripe.control = IPS_CSL;
5902 scb->cmd.unlock_stripe.reserved = 0;
5903 scb->cmd.unlock_stripe.reserved2 = 0;
5904 scb->cmd.unlock_stripe.reserved3 = 0;
5905
5906
5907 if (((ret =
5908 ips_send_wait(ha, scb, ips_cmd_timeout, intr)) == IPS_FAILURE)
5909 || (ret == IPS_SUCCESS_IMM)
5910 || ((scb->basic_status & IPS_GSC_STATUS_MASK) > 1))
5911 return (0);
5912
5913 return (1);
5914}
5915
5916
5917
5918
5919
5920
5921
5922
5923
5924
5925static void
5926ips_ffdc_reset(ips_ha_t * ha, int intr)
5927{
5928 ips_scb_t *scb;
5929
5930 METHOD_TRACE("ips_ffdc_reset", 1);
5931
5932 scb = &ha->scbs[ha->max_cmds - 1];
5933
5934 ips_init_scb(ha, scb);
5935
5936 scb->timeout = ips_cmd_timeout;
5937 scb->cdb[0] = IPS_CMD_FFDC;
5938 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
5939 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
5940 scb->cmd.ffdc.reset_count = ha->reset_count;
5941 scb->cmd.ffdc.reset_type = 0x80;
5942
5943
5944 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
5945
5946
5947 ips_send_wait(ha, scb, ips_cmd_timeout, intr);
5948}
5949
5950
5951
5952
5953
5954
5955
5956
5957
5958
5959static void
5960ips_ffdc_time(ips_ha_t * ha)
5961{
5962 ips_scb_t *scb;
5963
5964 METHOD_TRACE("ips_ffdc_time", 1);
5965
5966 DEBUG_VAR(1, "(%s%d) Sending time update.", ips_name, ha->host_num);
5967
5968 scb = &ha->scbs[ha->max_cmds - 1];
5969
5970 ips_init_scb(ha, scb);
5971
5972 scb->timeout = ips_cmd_timeout;
5973 scb->cdb[0] = IPS_CMD_FFDC;
5974 scb->cmd.ffdc.op_code = IPS_CMD_FFDC;
5975 scb->cmd.ffdc.command_id = IPS_COMMAND_ID(ha, scb);
5976 scb->cmd.ffdc.reset_count = 0;
5977 scb->cmd.ffdc.reset_type = 0;
5978
5979
5980 ips_fix_ffdc_time(ha, scb, ha->last_ffdc);
5981
5982
5983 ips_send_wait(ha, scb, ips_cmd_timeout, IPS_FFDC);
5984}
5985
5986
5987
5988
5989
5990
5991
5992
5993
5994static void
5995ips_fix_ffdc_time(ips_ha_t * ha, ips_scb_t * scb, time_t current_time)
5996{
5997 long days;
5998 long rem;
5999 int i;
6000 int year;
6001 int yleap;
6002 int year_lengths[2] = { IPS_DAYS_NORMAL_YEAR, IPS_DAYS_LEAP_YEAR };
6003 int month_lengths[12][2] = { {31, 31},
6004 {28, 29},
6005 {31, 31},
6006 {30, 30},
6007 {31, 31},
6008 {30, 30},
6009 {31, 31},
6010 {31, 31},
6011 {30, 30},
6012 {31, 31},
6013 {30, 30},
6014 {31, 31}
6015 };
6016
6017 METHOD_TRACE("ips_fix_ffdc_time", 1);
6018
6019 days = current_time / IPS_SECS_DAY;
6020 rem = current_time % IPS_SECS_DAY;
6021
6022 scb->cmd.ffdc.hour = (rem / IPS_SECS_HOUR);
6023 rem = rem % IPS_SECS_HOUR;
6024 scb->cmd.ffdc.minute = (rem / IPS_SECS_MIN);
6025 scb->cmd.ffdc.second = (rem % IPS_SECS_MIN);
6026
6027 year = IPS_EPOCH_YEAR;
6028 while (days < 0 || days >= year_lengths[yleap = IPS_IS_LEAP_YEAR(year)]) {
6029 int newy;
6030
6031 newy = year + (days / IPS_DAYS_NORMAL_YEAR);
6032 if (days < 0)
6033 --newy;
6034 days -= (newy - year) * IPS_DAYS_NORMAL_YEAR +
6035 IPS_NUM_LEAP_YEARS_THROUGH(newy - 1) -
6036 IPS_NUM_LEAP_YEARS_THROUGH(year - 1);
6037 year = newy;
6038 }
6039
6040 scb->cmd.ffdc.yearH = year / 100;
6041 scb->cmd.ffdc.yearL = year % 100;
6042
6043 for (i = 0; days >= month_lengths[i][yleap]; ++i)
6044 days -= month_lengths[i][yleap];
6045
6046 scb->cmd.ffdc.month = i + 1;
6047 scb->cmd.ffdc.day = days + 1;
6048}
6049
6050
6051
6052
6053
6054
6055
6056
6057
6058
6059
6060
6061
6062static int
6063ips_erase_bios(ips_ha_t * ha)
6064{
6065 int timeout;
6066 uint8_t status = 0;
6067
6068 METHOD_TRACE("ips_erase_bios", 1);
6069
6070 status = 0;
6071
6072
6073 outl(0, ha->io_addr + IPS_REG_FLAP);
6074 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6075 udelay(25);
6076
6077 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6078 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6079 udelay(25);
6080
6081
6082 outb(0x20, ha->io_addr + IPS_REG_FLDP);
6083 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6084 udelay(25);
6085
6086
6087 outb(0xD0, ha->io_addr + IPS_REG_FLDP);
6088 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6089 udelay(25);
6090
6091
6092 outb(0x70, ha->io_addr + IPS_REG_FLDP);
6093 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6094 udelay(25);
6095
6096 timeout = 80000;
6097
6098 while (timeout > 0) {
6099 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6100 outl(0, ha->io_addr + IPS_REG_FLAP);
6101 udelay(25);
6102 }
6103
6104 status = inb(ha->io_addr + IPS_REG_FLDP);
6105
6106 if (status & 0x80)
6107 break;
6108
6109 MDELAY(1);
6110 timeout--;
6111 }
6112
6113
6114 if (timeout <= 0) {
6115
6116
6117
6118 outb(0xB0, ha->io_addr + IPS_REG_FLDP);
6119 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6120 udelay(25);
6121
6122
6123 timeout = 10000;
6124 while (timeout > 0) {
6125 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6126 outl(0, ha->io_addr + IPS_REG_FLAP);
6127 udelay(25);
6128 }
6129
6130 status = inb(ha->io_addr + IPS_REG_FLDP);
6131
6132 if (status & 0xC0)
6133 break;
6134
6135 MDELAY(1);
6136 timeout--;
6137 }
6138
6139 return (1);
6140 }
6141
6142
6143 if (status & 0x08)
6144
6145 return (1);
6146
6147
6148 if (status & 0x30)
6149
6150 return (1);
6151
6152
6153
6154 outb(0x50, ha->io_addr + IPS_REG_FLDP);
6155 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6156 udelay(25);
6157
6158
6159 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6160 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6161 udelay(25);
6162
6163 return (0);
6164}
6165
6166
6167
6168
6169
6170
6171
6172
6173
6174static int
6175ips_erase_bios_memio(ips_ha_t * ha)
6176{
6177 int timeout;
6178 uint8_t status;
6179
6180 METHOD_TRACE("ips_erase_bios_memio", 1);
6181
6182 status = 0;
6183
6184
6185 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6186 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6187 udelay(25);
6188
6189 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6190 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6191 udelay(25);
6192
6193
6194 writeb(0x20, ha->mem_ptr + IPS_REG_FLDP);
6195 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6196 udelay(25);
6197
6198
6199 writeb(0xD0, ha->mem_ptr + IPS_REG_FLDP);
6200 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6201 udelay(25);
6202
6203
6204 writeb(0x70, ha->mem_ptr + IPS_REG_FLDP);
6205 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6206 udelay(25);
6207
6208 timeout = 80000;
6209
6210 while (timeout > 0) {
6211 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6212 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6213 udelay(25);
6214 }
6215
6216 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6217
6218 if (status & 0x80)
6219 break;
6220
6221 MDELAY(1);
6222 timeout--;
6223 }
6224
6225
6226 if (timeout <= 0) {
6227
6228
6229
6230 writeb(0xB0, ha->mem_ptr + IPS_REG_FLDP);
6231 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6232 udelay(25);
6233
6234
6235 timeout = 10000;
6236 while (timeout > 0) {
6237 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6238 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6239 udelay(25);
6240 }
6241
6242 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6243
6244 if (status & 0xC0)
6245 break;
6246
6247 MDELAY(1);
6248 timeout--;
6249 }
6250
6251 return (1);
6252 }
6253
6254
6255 if (status & 0x08)
6256
6257 return (1);
6258
6259
6260 if (status & 0x30)
6261
6262 return (1);
6263
6264
6265
6266 writeb(0x50, ha->mem_ptr + IPS_REG_FLDP);
6267 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6268 udelay(25);
6269
6270
6271 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6272 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6273 udelay(25);
6274
6275 return (0);
6276}
6277
6278
6279
6280
6281
6282
6283
6284
6285
6286static int
6287ips_program_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6288 uint32_t offset)
6289{
6290 int i;
6291 int timeout;
6292 uint8_t status = 0;
6293
6294 METHOD_TRACE("ips_program_bios", 1);
6295
6296 status = 0;
6297
6298 for (i = 0; i < buffersize; i++) {
6299
6300 outl(i + offset, ha->io_addr + IPS_REG_FLAP);
6301 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6302 udelay(25);
6303
6304 outb(0x40, ha->io_addr + IPS_REG_FLDP);
6305 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6306 udelay(25);
6307
6308 outb(buffer[i], ha->io_addr + IPS_REG_FLDP);
6309 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6310 udelay(25);
6311
6312
6313 timeout = 1000;
6314 while (timeout > 0) {
6315 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6316 outl(0, ha->io_addr + IPS_REG_FLAP);
6317 udelay(25);
6318 }
6319
6320 status = inb(ha->io_addr + IPS_REG_FLDP);
6321
6322 if (status & 0x80)
6323 break;
6324
6325 MDELAY(1);
6326 timeout--;
6327 }
6328
6329 if (timeout == 0) {
6330
6331 outl(0, ha->io_addr + IPS_REG_FLAP);
6332 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6333 udelay(25);
6334
6335 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6336 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6337 udelay(25);
6338
6339 return (1);
6340 }
6341
6342
6343 if (status & 0x18) {
6344
6345 outl(0, ha->io_addr + IPS_REG_FLAP);
6346 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6347 udelay(25);
6348
6349 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6350 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6351 udelay(25);
6352
6353 return (1);
6354 }
6355 }
6356
6357
6358 outl(0, ha->io_addr + IPS_REG_FLAP);
6359 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6360 udelay(25);
6361
6362 outb(0xFF, ha->io_addr + IPS_REG_FLDP);
6363 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6364 udelay(25);
6365
6366 return (0);
6367}
6368
6369
6370
6371
6372
6373
6374
6375
6376
6377static int
6378ips_program_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6379 uint32_t offset)
6380{
6381 int i;
6382 int timeout;
6383 uint8_t status = 0;
6384
6385 METHOD_TRACE("ips_program_bios_memio", 1);
6386
6387 status = 0;
6388
6389 for (i = 0; i < buffersize; i++) {
6390
6391 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6392 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6393 udelay(25);
6394
6395 writeb(0x40, ha->mem_ptr + IPS_REG_FLDP);
6396 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6397 udelay(25);
6398
6399 writeb(buffer[i], ha->mem_ptr + IPS_REG_FLDP);
6400 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6401 udelay(25);
6402
6403
6404 timeout = 1000;
6405 while (timeout > 0) {
6406 if (ha->pcidev->revision == IPS_REVID_TROMBONE64) {
6407 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6408 udelay(25);
6409 }
6410
6411 status = readb(ha->mem_ptr + IPS_REG_FLDP);
6412
6413 if (status & 0x80)
6414 break;
6415
6416 MDELAY(1);
6417 timeout--;
6418 }
6419
6420 if (timeout == 0) {
6421
6422 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6423 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6424 udelay(25);
6425
6426 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6427 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6428 udelay(25);
6429
6430 return (1);
6431 }
6432
6433
6434 if (status & 0x18) {
6435
6436 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6437 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6438 udelay(25);
6439
6440 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6441 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6442 udelay(25);
6443
6444 return (1);
6445 }
6446 }
6447
6448
6449 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6450 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6451 udelay(25);
6452
6453 writeb(0xFF, ha->mem_ptr + IPS_REG_FLDP);
6454 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6455 udelay(25);
6456
6457 return (0);
6458}
6459
6460
6461
6462
6463
6464
6465
6466
6467
6468static int
6469ips_verify_bios(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6470 uint32_t offset)
6471{
6472 uint8_t checksum;
6473 int i;
6474
6475 METHOD_TRACE("ips_verify_bios", 1);
6476
6477
6478 outl(0, ha->io_addr + IPS_REG_FLAP);
6479 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6480 udelay(25);
6481
6482 if (inb(ha->io_addr + IPS_REG_FLDP) != 0x55)
6483 return (1);
6484
6485 outl(1, ha->io_addr + IPS_REG_FLAP);
6486 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6487 udelay(25);
6488 if (inb(ha->io_addr + IPS_REG_FLDP) != 0xAA)
6489 return (1);
6490
6491 checksum = 0xff;
6492 for (i = 2; i < buffersize; i++) {
6493
6494 outl(i + offset, ha->io_addr + IPS_REG_FLAP);
6495 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6496 udelay(25);
6497
6498 checksum = (uint8_t) checksum + inb(ha->io_addr + IPS_REG_FLDP);
6499 }
6500
6501 if (checksum != 0)
6502
6503 return (1);
6504 else
6505
6506 return (0);
6507}
6508
6509
6510
6511
6512
6513
6514
6515
6516
6517static int
6518ips_verify_bios_memio(ips_ha_t * ha, char *buffer, uint32_t buffersize,
6519 uint32_t offset)
6520{
6521 uint8_t checksum;
6522 int i;
6523
6524 METHOD_TRACE("ips_verify_bios_memio", 1);
6525
6526
6527 writel(0, ha->mem_ptr + IPS_REG_FLAP);
6528 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6529 udelay(25);
6530
6531 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0x55)
6532 return (1);
6533
6534 writel(1, ha->mem_ptr + IPS_REG_FLAP);
6535 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6536 udelay(25);
6537 if (readb(ha->mem_ptr + IPS_REG_FLDP) != 0xAA)
6538 return (1);
6539
6540 checksum = 0xff;
6541 for (i = 2; i < buffersize; i++) {
6542
6543 writel(i + offset, ha->mem_ptr + IPS_REG_FLAP);
6544 if (ha->pcidev->revision == IPS_REVID_TROMBONE64)
6545 udelay(25);
6546
6547 checksum =
6548 (uint8_t) checksum + readb(ha->mem_ptr + IPS_REG_FLDP);
6549 }
6550
6551 if (checksum != 0)
6552
6553 return (1);
6554 else
6555
6556 return (0);
6557}
6558
6559
6560
6561
6562
6563
6564
6565
6566static int
6567ips_abort_init(ips_ha_t * ha, int index)
6568{
6569 ha->active = 0;
6570 ips_free(ha);
6571 ips_ha[index] = NULL;
6572 ips_sh[index] = NULL;
6573 return -1;
6574}
6575
6576
6577
6578
6579
6580
6581
6582
6583static void
6584ips_shift_controllers(int lowindex, int highindex)
6585{
6586 ips_ha_t *ha_sav = ips_ha[highindex];
6587 struct Scsi_Host *sh_sav = ips_sh[highindex];
6588 int i;
6589
6590 for (i = highindex; i > lowindex; i--) {
6591 ips_ha[i] = ips_ha[i - 1];
6592 ips_sh[i] = ips_sh[i - 1];
6593 ips_ha[i]->host_num = i;
6594 }
6595 ha_sav->host_num = lowindex;
6596 ips_ha[lowindex] = ha_sav;
6597 ips_sh[lowindex] = sh_sav;
6598}
6599
6600
6601
6602
6603
6604
6605
6606
6607static void
6608ips_order_controllers(void)
6609{
6610 int i, j, tmp, position = 0;
6611 IPS_NVRAM_P5 *nvram;
6612 if (!ips_ha[0])
6613 return;
6614 nvram = ips_ha[0]->nvram;
6615
6616 if (nvram->adapter_order[0]) {
6617 for (i = 1; i <= nvram->adapter_order[0]; i++) {
6618 for (j = position; j < ips_num_controllers; j++) {
6619 switch (ips_ha[j]->ad_type) {
6620 case IPS_ADTYPE_SERVERAID6M:
6621 case IPS_ADTYPE_SERVERAID7M:
6622 if (nvram->adapter_order[i] == 'M') {
6623 ips_shift_controllers(position,
6624 j);
6625 position++;
6626 }
6627 break;
6628 case IPS_ADTYPE_SERVERAID4L:
6629 case IPS_ADTYPE_SERVERAID4M:
6630 case IPS_ADTYPE_SERVERAID4MX:
6631 case IPS_ADTYPE_SERVERAID4LX:
6632 if (nvram->adapter_order[i] == 'N') {
6633 ips_shift_controllers(position,
6634 j);
6635 position++;
6636 }
6637 break;
6638 case IPS_ADTYPE_SERVERAID6I:
6639 case IPS_ADTYPE_SERVERAID5I2:
6640 case IPS_ADTYPE_SERVERAID5I1:
6641 case IPS_ADTYPE_SERVERAID7k:
6642 if (nvram->adapter_order[i] == 'S') {
6643 ips_shift_controllers(position,
6644 j);
6645 position++;
6646 }
6647 break;
6648 case IPS_ADTYPE_SERVERAID:
6649 case IPS_ADTYPE_SERVERAID2:
6650 case IPS_ADTYPE_NAVAJO:
6651 case IPS_ADTYPE_KIOWA:
6652 case IPS_ADTYPE_SERVERAID3L:
6653 case IPS_ADTYPE_SERVERAID3:
6654 case IPS_ADTYPE_SERVERAID4H:
6655 if (nvram->adapter_order[i] == 'A') {
6656 ips_shift_controllers(position,
6657 j);
6658 position++;
6659 }
6660 break;
6661 default:
6662 break;
6663 }
6664 }
6665 }
6666
6667 return;
6668 }
6669
6670 tmp = 0;
6671 for (i = position; i < ips_num_controllers; i++) {
6672 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I2 ||
6673 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID5I1) {
6674 ips_shift_controllers(position, i);
6675 position++;
6676 tmp = 1;
6677 }
6678 }
6679
6680 if (!tmp)
6681 return;
6682 for (i = position; i < ips_num_controllers; i++) {
6683 if (ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4L ||
6684 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4M ||
6685 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4LX ||
6686 ips_ha[i]->ad_type == IPS_ADTYPE_SERVERAID4MX) {
6687 ips_shift_controllers(position, i);
6688 position++;
6689 }
6690 }
6691
6692 return;
6693}
6694
6695
6696
6697
6698
6699
6700
6701
6702static int
6703ips_register_scsi(int index)
6704{
6705 struct Scsi_Host *sh;
6706 ips_ha_t *ha, *oldha = ips_ha[index];
6707 sh = scsi_host_alloc(&ips_driver_template, sizeof (ips_ha_t));
6708 if (!sh) {
6709 IPS_PRINTK(KERN_WARNING, oldha->pcidev,
6710 "Unable to register controller with SCSI subsystem\n");
6711 return -1;
6712 }
6713 ha = IPS_HA(sh);
6714 memcpy(ha, oldha, sizeof (ips_ha_t));
6715 free_irq(oldha->pcidev->irq, oldha);
6716
6717 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
6718 IPS_PRINTK(KERN_WARNING, ha->pcidev,
6719 "Unable to install interrupt handler\n");
6720 goto err_out_sh;
6721 }
6722
6723 kfree(oldha);
6724
6725
6726 sh->unique_id = (ha->io_addr) ? ha->io_addr : ha->mem_addr;
6727 sh->sg_tablesize = sh->hostt->sg_tablesize;
6728 sh->can_queue = sh->hostt->can_queue;
6729 sh->cmd_per_lun = sh->hostt->cmd_per_lun;
6730 sh->use_clustering = sh->hostt->use_clustering;
6731 sh->max_sectors = 128;
6732
6733 sh->max_id = ha->ntargets;
6734 sh->max_lun = ha->nlun;
6735 sh->max_channel = ha->nbus - 1;
6736 sh->can_queue = ha->max_cmds - 1;
6737
6738 if (scsi_add_host(sh, &ha->pcidev->dev))
6739 goto err_out;
6740
6741 ips_sh[index] = sh;
6742 ips_ha[index] = ha;
6743
6744 scsi_scan_host(sh);
6745
6746 return 0;
6747
6748err_out:
6749 free_irq(ha->pcidev->irq, ha);
6750err_out_sh:
6751 scsi_host_put(sh);
6752 return -1;
6753}
6754
6755
6756
6757
6758
6759
6760
6761static void
6762ips_remove_device(struct pci_dev *pci_dev)
6763{
6764 struct Scsi_Host *sh = pci_get_drvdata(pci_dev);
6765
6766 pci_set_drvdata(pci_dev, NULL);
6767
6768 ips_release(sh);
6769
6770 pci_release_regions(pci_dev);
6771 pci_disable_device(pci_dev);
6772}
6773
6774
6775
6776
6777
6778
6779
6780
6781static int __init
6782ips_module_init(void)
6783{
6784#if !defined(__i386__) && !defined(__ia64__) && !defined(__x86_64__)
6785 printk(KERN_ERR "ips: This driver has only been tested on the x86/ia64/x86_64 platforms\n");
6786 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
6787#endif
6788
6789 if (pci_register_driver(&ips_pci_driver) < 0)
6790 return -ENODEV;
6791 ips_driver_template.module = THIS_MODULE;
6792 ips_order_controllers();
6793 if (!ips_detect(&ips_driver_template)) {
6794 pci_unregister_driver(&ips_pci_driver);
6795 return -ENODEV;
6796 }
6797 register_reboot_notifier(&ips_notifier);
6798 return 0;
6799}
6800
6801
6802
6803
6804
6805
6806
6807
6808static void __exit
6809ips_module_exit(void)
6810{
6811 pci_unregister_driver(&ips_pci_driver);
6812 unregister_reboot_notifier(&ips_notifier);
6813}
6814
6815module_init(ips_module_init);
6816module_exit(ips_module_exit);
6817
6818
6819
6820
6821
6822
6823
6824
6825
6826
6827static int
6828ips_insert_device(struct pci_dev *pci_dev, const struct pci_device_id *ent)
6829{
6830 int index = -1;
6831 int rc;
6832
6833 METHOD_TRACE("ips_insert_device", 1);
6834 rc = pci_enable_device(pci_dev);
6835 if (rc)
6836 return rc;
6837
6838 rc = pci_request_regions(pci_dev, "ips");
6839 if (rc)
6840 goto err_out;
6841
6842 rc = ips_init_phase1(pci_dev, &index);
6843 if (rc == SUCCESS)
6844 rc = ips_init_phase2(index);
6845
6846 if (ips_hotplug)
6847 if (ips_register_scsi(index)) {
6848 ips_free(ips_ha[index]);
6849 rc = -1;
6850 }
6851
6852 if (rc == SUCCESS)
6853 ips_num_controllers++;
6854
6855 ips_next_controller = ips_num_controllers;
6856
6857 if (rc < 0) {
6858 rc = -ENODEV;
6859 goto err_out_regions;
6860 }
6861
6862 pci_set_drvdata(pci_dev, ips_sh[index]);
6863 return 0;
6864
6865err_out_regions:
6866 pci_release_regions(pci_dev);
6867err_out:
6868 pci_disable_device(pci_dev);
6869 return rc;
6870}
6871
6872
6873
6874
6875
6876
6877
6878
6879
6880
6881static int
6882ips_init_phase1(struct pci_dev *pci_dev, int *indexPtr)
6883{
6884 ips_ha_t *ha;
6885 uint32_t io_addr;
6886 uint32_t mem_addr;
6887 uint32_t io_len;
6888 uint32_t mem_len;
6889 uint8_t bus;
6890 uint8_t func;
6891 int j;
6892 int index;
6893 dma_addr_t dma_address;
6894 char __iomem *ioremap_ptr;
6895 char __iomem *mem_ptr;
6896 uint32_t IsDead;
6897
6898 METHOD_TRACE("ips_init_phase1", 1);
6899 index = IPS_MAX_ADAPTERS;
6900 for (j = 0; j < IPS_MAX_ADAPTERS; j++) {
6901 if (ips_ha[j] == NULL) {
6902 index = j;
6903 break;
6904 }
6905 }
6906
6907 if (index >= IPS_MAX_ADAPTERS)
6908 return -1;
6909
6910
6911 bus = pci_dev->bus->number;
6912 func = pci_dev->devfn;
6913
6914
6915 mem_addr = 0;
6916 io_addr = 0;
6917 mem_len = 0;
6918 io_len = 0;
6919
6920 for (j = 0; j < 2; j++) {
6921 if (!pci_resource_start(pci_dev, j))
6922 break;
6923
6924 if (pci_resource_flags(pci_dev, j) & IORESOURCE_IO) {
6925 io_addr = pci_resource_start(pci_dev, j);
6926 io_len = pci_resource_len(pci_dev, j);
6927 } else {
6928 mem_addr = pci_resource_start(pci_dev, j);
6929 mem_len = pci_resource_len(pci_dev, j);
6930 }
6931 }
6932
6933
6934 if (mem_addr) {
6935 uint32_t base;
6936 uint32_t offs;
6937
6938 base = mem_addr & PAGE_MASK;
6939 offs = mem_addr - base;
6940 ioremap_ptr = ioremap(base, PAGE_SIZE);
6941 if (!ioremap_ptr)
6942 return -1;
6943 mem_ptr = ioremap_ptr + offs;
6944 } else {
6945 ioremap_ptr = NULL;
6946 mem_ptr = NULL;
6947 }
6948
6949
6950 ha = kzalloc(sizeof (ips_ha_t), GFP_KERNEL);
6951 if (ha == NULL) {
6952 IPS_PRINTK(KERN_WARNING, pci_dev,
6953 "Unable to allocate temporary ha struct\n");
6954 return -1;
6955 }
6956
6957 ips_sh[index] = NULL;
6958 ips_ha[index] = ha;
6959 ha->active = 1;
6960
6961
6962 ha->io_addr = io_addr;
6963 ha->io_len = io_len;
6964 ha->mem_addr = mem_addr;
6965 ha->mem_len = mem_len;
6966 ha->mem_ptr = mem_ptr;
6967 ha->ioremap_ptr = ioremap_ptr;
6968 ha->host_num = (uint32_t) index;
6969 ha->slot_num = PCI_SLOT(pci_dev->devfn);
6970 ha->pcidev = pci_dev;
6971
6972
6973
6974
6975
6976
6977
6978 if (IPS_ENABLE_DMA64 && IPS_HAS_ENH_SGLIST(ha) &&
6979 !pci_set_dma_mask(ha->pcidev, DMA_BIT_MASK(64))) {
6980 (ha)->flags |= IPS_HA_ENH_SG;
6981 } else {
6982 if (pci_set_dma_mask(ha->pcidev, DMA_BIT_MASK(32)) != 0) {
6983 printk(KERN_WARNING "Unable to set DMA Mask\n");
6984 return ips_abort_init(ha, index);
6985 }
6986 }
6987 if(ips_cd_boot && !ips_FlashData){
6988 ips_FlashData = pci_alloc_consistent(pci_dev, PAGE_SIZE << 7,
6989 &ips_flashbusaddr);
6990 }
6991
6992 ha->enq = pci_alloc_consistent(pci_dev, sizeof (IPS_ENQ),
6993 &ha->enq_busaddr);
6994 if (!ha->enq) {
6995 IPS_PRINTK(KERN_WARNING, pci_dev,
6996 "Unable to allocate host inquiry structure\n");
6997 return ips_abort_init(ha, index);
6998 }
6999
7000 ha->adapt = pci_alloc_consistent(pci_dev, sizeof (IPS_ADAPTER) +
7001 sizeof (IPS_IO_CMD), &dma_address);
7002 if (!ha->adapt) {
7003 IPS_PRINTK(KERN_WARNING, pci_dev,
7004 "Unable to allocate host adapt & dummy structures\n");
7005 return ips_abort_init(ha, index);
7006 }
7007 ha->adapt->hw_status_start = dma_address;
7008 ha->dummy = (void *) (ha->adapt + 1);
7009
7010
7011
7012 ha->logical_drive_info = pci_alloc_consistent(pci_dev, sizeof (IPS_LD_INFO), &dma_address);
7013 if (!ha->logical_drive_info) {
7014 IPS_PRINTK(KERN_WARNING, pci_dev,
7015 "Unable to allocate logical drive info structure\n");
7016 return ips_abort_init(ha, index);
7017 }
7018 ha->logical_drive_info_dma_addr = dma_address;
7019
7020
7021 ha->conf = kmalloc(sizeof (IPS_CONF), GFP_KERNEL);
7022
7023 if (!ha->conf) {
7024 IPS_PRINTK(KERN_WARNING, pci_dev,
7025 "Unable to allocate host conf structure\n");
7026 return ips_abort_init(ha, index);
7027 }
7028
7029 ha->nvram = kmalloc(sizeof (IPS_NVRAM_P5), GFP_KERNEL);
7030
7031 if (!ha->nvram) {
7032 IPS_PRINTK(KERN_WARNING, pci_dev,
7033 "Unable to allocate host NVRAM structure\n");
7034 return ips_abort_init(ha, index);
7035 }
7036
7037 ha->subsys = kmalloc(sizeof (IPS_SUBSYS), GFP_KERNEL);
7038
7039 if (!ha->subsys) {
7040 IPS_PRINTK(KERN_WARNING, pci_dev,
7041 "Unable to allocate host subsystem structure\n");
7042 return ips_abort_init(ha, index);
7043 }
7044
7045
7046
7047 if (ips_ioctlsize < PAGE_SIZE)
7048 ips_ioctlsize = PAGE_SIZE;
7049
7050 ha->ioctl_data = pci_alloc_consistent(pci_dev, ips_ioctlsize,
7051 &ha->ioctl_busaddr);
7052 ha->ioctl_len = ips_ioctlsize;
7053 if (!ha->ioctl_data) {
7054 IPS_PRINTK(KERN_WARNING, pci_dev,
7055 "Unable to allocate IOCTL data\n");
7056 return ips_abort_init(ha, index);
7057 }
7058
7059
7060
7061
7062 ips_setup_funclist(ha);
7063
7064 if ((IPS_IS_MORPHEUS(ha)) || (IPS_IS_MARCO(ha))) {
7065
7066 IsDead = readl(ha->mem_ptr + IPS_REG_I960_MSG1);
7067 if (IsDead == 0xDEADBEEF) {
7068 ips_reset_morpheus(ha);
7069 }
7070 }
7071
7072
7073
7074
7075
7076 if (!(*ha->func.isinit) (ha)) {
7077 if (!(*ha->func.init) (ha)) {
7078
7079
7080
7081 IPS_PRINTK(KERN_WARNING, pci_dev,
7082 "Unable to initialize controller\n");
7083 return ips_abort_init(ha, index);
7084 }
7085 }
7086
7087 *indexPtr = index;
7088 return SUCCESS;
7089}
7090
7091
7092
7093
7094
7095
7096
7097
7098
7099
7100static int
7101ips_init_phase2(int index)
7102{
7103 ips_ha_t *ha;
7104
7105 ha = ips_ha[index];
7106
7107 METHOD_TRACE("ips_init_phase2", 1);
7108 if (!ha->active) {
7109 ips_ha[index] = NULL;
7110 return -1;
7111 }
7112
7113
7114 if (request_irq(ha->pcidev->irq, do_ipsintr, IRQF_SHARED, ips_name, ha)) {
7115 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7116 "Unable to install interrupt handler\n");
7117 return ips_abort_init(ha, index);
7118 }
7119
7120
7121
7122
7123 ha->max_cmds = 1;
7124 if (!ips_allocatescbs(ha)) {
7125 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7126 "Unable to allocate a CCB\n");
7127 free_irq(ha->pcidev->irq, ha);
7128 return ips_abort_init(ha, index);
7129 }
7130
7131 if (!ips_hainit(ha)) {
7132 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7133 "Unable to initialize controller\n");
7134 free_irq(ha->pcidev->irq, ha);
7135 return ips_abort_init(ha, index);
7136 }
7137
7138 ips_deallocatescbs(ha, 1);
7139
7140
7141 if (!ips_allocatescbs(ha)) {
7142 IPS_PRINTK(KERN_WARNING, ha->pcidev,
7143 "Unable to allocate CCBs\n");
7144 free_irq(ha->pcidev->irq, ha);
7145 return ips_abort_init(ha, index);
7146 }
7147
7148 return SUCCESS;
7149}
7150
7151MODULE_LICENSE("GPL");
7152MODULE_DESCRIPTION("IBM ServeRAID Adapter Driver " IPS_VER_STRING);
7153MODULE_VERSION(IPS_VER_STRING);
7154
7155
7156
7157
7158
7159
7160
7161
7162
7163
7164
7165
7166
7167
7168
7169
7170
7171
7172
7173
7174
