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41#include <linux/slab.h>
42#include "pm8001_sas.h"
43#include "pm8001_chips.h"
44
45static struct scsi_transport_template *pm8001_stt;
46
47
48
49
50
51static const struct pm8001_chip_info pm8001_chips[] = {
52 [chip_8001] = {0, 8, &pm8001_8001_dispatch,},
53 [chip_8008] = {0, 8, &pm8001_80xx_dispatch,},
54 [chip_8009] = {1, 8, &pm8001_80xx_dispatch,},
55 [chip_8018] = {0, 16, &pm8001_80xx_dispatch,},
56 [chip_8019] = {1, 16, &pm8001_80xx_dispatch,},
57 [chip_8074] = {0, 8, &pm8001_80xx_dispatch,},
58 [chip_8076] = {0, 16, &pm8001_80xx_dispatch,},
59 [chip_8077] = {0, 16, &pm8001_80xx_dispatch,},
60 [chip_8006] = {0, 16, &pm8001_80xx_dispatch,},
61 [chip_8070] = {0, 8, &pm8001_80xx_dispatch,},
62 [chip_8072] = {0, 16, &pm8001_80xx_dispatch,},
63};
64static int pm8001_id;
65
66LIST_HEAD(hba_list);
67
68struct workqueue_struct *pm8001_wq;
69
70
71
72
73static struct scsi_host_template pm8001_sht = {
74 .module = THIS_MODULE,
75 .name = DRV_NAME,
76 .queuecommand = sas_queuecommand,
77 .target_alloc = sas_target_alloc,
78 .slave_configure = sas_slave_configure,
79 .scan_finished = pm8001_scan_finished,
80 .scan_start = pm8001_scan_start,
81 .change_queue_depth = sas_change_queue_depth,
82 .bios_param = sas_bios_param,
83 .can_queue = 1,
84 .this_id = -1,
85 .sg_tablesize = SG_ALL,
86 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
87 .use_clustering = ENABLE_CLUSTERING,
88 .eh_device_reset_handler = sas_eh_device_reset_handler,
89 .eh_bus_reset_handler = sas_eh_bus_reset_handler,
90 .target_destroy = sas_target_destroy,
91 .ioctl = sas_ioctl,
92 .shost_attrs = pm8001_host_attrs,
93 .track_queue_depth = 1,
94};
95
96
97
98
99static struct sas_domain_function_template pm8001_transport_ops = {
100 .lldd_dev_found = pm8001_dev_found,
101 .lldd_dev_gone = pm8001_dev_gone,
102
103 .lldd_execute_task = pm8001_queue_command,
104 .lldd_control_phy = pm8001_phy_control,
105
106 .lldd_abort_task = pm8001_abort_task,
107 .lldd_abort_task_set = pm8001_abort_task_set,
108 .lldd_clear_aca = pm8001_clear_aca,
109 .lldd_clear_task_set = pm8001_clear_task_set,
110 .lldd_I_T_nexus_reset = pm8001_I_T_nexus_reset,
111 .lldd_lu_reset = pm8001_lu_reset,
112 .lldd_query_task = pm8001_query_task,
113};
114
115
116
117
118
119
120static void pm8001_phy_init(struct pm8001_hba_info *pm8001_ha, int phy_id)
121{
122 struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
123 struct asd_sas_phy *sas_phy = &phy->sas_phy;
124 phy->phy_state = 0;
125 phy->pm8001_ha = pm8001_ha;
126 sas_phy->enabled = (phy_id < pm8001_ha->chip->n_phy) ? 1 : 0;
127 sas_phy->class = SAS;
128 sas_phy->iproto = SAS_PROTOCOL_ALL;
129 sas_phy->tproto = 0;
130 sas_phy->type = PHY_TYPE_PHYSICAL;
131 sas_phy->role = PHY_ROLE_INITIATOR;
132 sas_phy->oob_mode = OOB_NOT_CONNECTED;
133 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
134 sas_phy->id = phy_id;
135 sas_phy->sas_addr = &pm8001_ha->sas_addr[0];
136 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
137 sas_phy->ha = (struct sas_ha_struct *)pm8001_ha->shost->hostdata;
138 sas_phy->lldd_phy = phy;
139}
140
141
142
143
144
145
146static void pm8001_free(struct pm8001_hba_info *pm8001_ha)
147{
148 int i;
149
150 if (!pm8001_ha)
151 return;
152
153 for (i = 0; i < USI_MAX_MEMCNT; i++) {
154 if (pm8001_ha->memoryMap.region[i].virt_ptr != NULL) {
155 pci_free_consistent(pm8001_ha->pdev,
156 (pm8001_ha->memoryMap.region[i].total_len +
157 pm8001_ha->memoryMap.region[i].alignment),
158 pm8001_ha->memoryMap.region[i].virt_ptr,
159 pm8001_ha->memoryMap.region[i].phys_addr);
160 }
161 }
162 PM8001_CHIP_DISP->chip_iounmap(pm8001_ha);
163 if (pm8001_ha->shost)
164 scsi_host_put(pm8001_ha->shost);
165 flush_workqueue(pm8001_wq);
166 kfree(pm8001_ha->tags);
167 kfree(pm8001_ha);
168}
169
170#ifdef PM8001_USE_TASKLET
171
172
173
174
175
176
177static void pm8001_tasklet(unsigned long opaque)
178{
179 struct pm8001_hba_info *pm8001_ha;
180 struct isr_param *irq_vector;
181
182 irq_vector = (struct isr_param *)opaque;
183 pm8001_ha = irq_vector->drv_inst;
184 if (unlikely(!pm8001_ha))
185 BUG_ON(1);
186 PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
187}
188#endif
189
190
191
192
193
194
195
196
197static irqreturn_t pm8001_interrupt_handler_msix(int irq, void *opaque)
198{
199 struct isr_param *irq_vector;
200 struct pm8001_hba_info *pm8001_ha;
201 irqreturn_t ret = IRQ_HANDLED;
202 irq_vector = (struct isr_param *)opaque;
203 pm8001_ha = irq_vector->drv_inst;
204
205 if (unlikely(!pm8001_ha))
206 return IRQ_NONE;
207 if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
208 return IRQ_NONE;
209#ifdef PM8001_USE_TASKLET
210 tasklet_schedule(&pm8001_ha->tasklet[irq_vector->irq_id]);
211#else
212 ret = PM8001_CHIP_DISP->isr(pm8001_ha, irq_vector->irq_id);
213#endif
214 return ret;
215}
216
217
218
219
220
221
222static irqreturn_t pm8001_interrupt_handler_intx(int irq, void *dev_id)
223{
224 struct pm8001_hba_info *pm8001_ha;
225 irqreturn_t ret = IRQ_HANDLED;
226 struct sas_ha_struct *sha = dev_id;
227 pm8001_ha = sha->lldd_ha;
228 if (unlikely(!pm8001_ha))
229 return IRQ_NONE;
230 if (!PM8001_CHIP_DISP->is_our_interupt(pm8001_ha))
231 return IRQ_NONE;
232
233#ifdef PM8001_USE_TASKLET
234 tasklet_schedule(&pm8001_ha->tasklet[0]);
235#else
236 ret = PM8001_CHIP_DISP->isr(pm8001_ha, 0);
237#endif
238 return ret;
239}
240
241
242
243
244
245
246static int pm8001_alloc(struct pm8001_hba_info *pm8001_ha,
247 const struct pci_device_id *ent)
248{
249 int i;
250 spin_lock_init(&pm8001_ha->lock);
251 spin_lock_init(&pm8001_ha->bitmap_lock);
252 PM8001_INIT_DBG(pm8001_ha,
253 pm8001_printk("pm8001_alloc: PHY:%x\n",
254 pm8001_ha->chip->n_phy));
255 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
256 pm8001_phy_init(pm8001_ha, i);
257 pm8001_ha->port[i].wide_port_phymap = 0;
258 pm8001_ha->port[i].port_attached = 0;
259 pm8001_ha->port[i].port_state = 0;
260 INIT_LIST_HEAD(&pm8001_ha->port[i].list);
261 }
262
263 pm8001_ha->tags = kzalloc(PM8001_MAX_CCB, GFP_KERNEL);
264 if (!pm8001_ha->tags)
265 goto err_out;
266
267 pm8001_ha->memoryMap.region[AAP1].num_elements = 1;
268 pm8001_ha->memoryMap.region[AAP1].element_size = PM8001_EVENT_LOG_SIZE;
269 pm8001_ha->memoryMap.region[AAP1].total_len = PM8001_EVENT_LOG_SIZE;
270 pm8001_ha->memoryMap.region[AAP1].alignment = 32;
271
272
273 pm8001_ha->memoryMap.region[IOP].num_elements = 1;
274 pm8001_ha->memoryMap.region[IOP].element_size = PM8001_EVENT_LOG_SIZE;
275 pm8001_ha->memoryMap.region[IOP].total_len = PM8001_EVENT_LOG_SIZE;
276 pm8001_ha->memoryMap.region[IOP].alignment = 32;
277
278 for (i = 0; i < PM8001_MAX_SPCV_INB_NUM; i++) {
279
280 pm8001_ha->memoryMap.region[CI+i].num_elements = 1;
281 pm8001_ha->memoryMap.region[CI+i].element_size = 4;
282 pm8001_ha->memoryMap.region[CI+i].total_len = 4;
283 pm8001_ha->memoryMap.region[CI+i].alignment = 4;
284
285 if ((ent->driver_data) != chip_8001) {
286
287 pm8001_ha->memoryMap.region[IB+i].num_elements =
288 PM8001_MPI_QUEUE;
289 pm8001_ha->memoryMap.region[IB+i].element_size = 128;
290 pm8001_ha->memoryMap.region[IB+i].total_len =
291 PM8001_MPI_QUEUE * 128;
292 pm8001_ha->memoryMap.region[IB+i].alignment = 128;
293 } else {
294 pm8001_ha->memoryMap.region[IB+i].num_elements =
295 PM8001_MPI_QUEUE;
296 pm8001_ha->memoryMap.region[IB+i].element_size = 64;
297 pm8001_ha->memoryMap.region[IB+i].total_len =
298 PM8001_MPI_QUEUE * 64;
299 pm8001_ha->memoryMap.region[IB+i].alignment = 64;
300 }
301 }
302
303 for (i = 0; i < PM8001_MAX_SPCV_OUTB_NUM; i++) {
304
305 pm8001_ha->memoryMap.region[PI+i].num_elements = 1;
306 pm8001_ha->memoryMap.region[PI+i].element_size = 4;
307 pm8001_ha->memoryMap.region[PI+i].total_len = 4;
308 pm8001_ha->memoryMap.region[PI+i].alignment = 4;
309
310 if (ent->driver_data != chip_8001) {
311
312 pm8001_ha->memoryMap.region[OB+i].num_elements =
313 PM8001_MPI_QUEUE;
314 pm8001_ha->memoryMap.region[OB+i].element_size = 128;
315 pm8001_ha->memoryMap.region[OB+i].total_len =
316 PM8001_MPI_QUEUE * 128;
317 pm8001_ha->memoryMap.region[OB+i].alignment = 128;
318 } else {
319
320 pm8001_ha->memoryMap.region[OB+i].num_elements =
321 PM8001_MPI_QUEUE;
322 pm8001_ha->memoryMap.region[OB+i].element_size = 64;
323 pm8001_ha->memoryMap.region[OB+i].total_len =
324 PM8001_MPI_QUEUE * 64;
325 pm8001_ha->memoryMap.region[OB+i].alignment = 64;
326 }
327
328 }
329
330 pm8001_ha->memoryMap.region[NVMD].num_elements = 1;
331 pm8001_ha->memoryMap.region[NVMD].element_size = 4096;
332 pm8001_ha->memoryMap.region[NVMD].total_len = 4096;
333
334 pm8001_ha->memoryMap.region[DEV_MEM].num_elements = 1;
335 pm8001_ha->memoryMap.region[DEV_MEM].element_size = PM8001_MAX_DEVICES *
336 sizeof(struct pm8001_device);
337 pm8001_ha->memoryMap.region[DEV_MEM].total_len = PM8001_MAX_DEVICES *
338 sizeof(struct pm8001_device);
339
340
341 pm8001_ha->memoryMap.region[CCB_MEM].num_elements = 1;
342 pm8001_ha->memoryMap.region[CCB_MEM].element_size = PM8001_MAX_CCB *
343 sizeof(struct pm8001_ccb_info);
344 pm8001_ha->memoryMap.region[CCB_MEM].total_len = PM8001_MAX_CCB *
345 sizeof(struct pm8001_ccb_info);
346
347
348 pm8001_ha->memoryMap.region[FW_FLASH].total_len = 4096;
349
350 pm8001_ha->memoryMap.region[FORENSIC_MEM].num_elements = 1;
351 pm8001_ha->memoryMap.region[FORENSIC_MEM].total_len = 0x10000;
352 pm8001_ha->memoryMap.region[FORENSIC_MEM].element_size = 0x10000;
353 pm8001_ha->memoryMap.region[FORENSIC_MEM].alignment = 0x10000;
354 for (i = 0; i < USI_MAX_MEMCNT; i++) {
355 if (pm8001_mem_alloc(pm8001_ha->pdev,
356 &pm8001_ha->memoryMap.region[i].virt_ptr,
357 &pm8001_ha->memoryMap.region[i].phys_addr,
358 &pm8001_ha->memoryMap.region[i].phys_addr_hi,
359 &pm8001_ha->memoryMap.region[i].phys_addr_lo,
360 pm8001_ha->memoryMap.region[i].total_len,
361 pm8001_ha->memoryMap.region[i].alignment) != 0) {
362 PM8001_FAIL_DBG(pm8001_ha,
363 pm8001_printk("Mem%d alloc failed\n",
364 i));
365 goto err_out;
366 }
367 }
368
369 pm8001_ha->devices = pm8001_ha->memoryMap.region[DEV_MEM].virt_ptr;
370 for (i = 0; i < PM8001_MAX_DEVICES; i++) {
371 pm8001_ha->devices[i].dev_type = SAS_PHY_UNUSED;
372 pm8001_ha->devices[i].id = i;
373 pm8001_ha->devices[i].device_id = PM8001_MAX_DEVICES;
374 pm8001_ha->devices[i].running_req = 0;
375 }
376 pm8001_ha->ccb_info = pm8001_ha->memoryMap.region[CCB_MEM].virt_ptr;
377 for (i = 0; i < PM8001_MAX_CCB; i++) {
378 pm8001_ha->ccb_info[i].ccb_dma_handle =
379 pm8001_ha->memoryMap.region[CCB_MEM].phys_addr +
380 i * sizeof(struct pm8001_ccb_info);
381 pm8001_ha->ccb_info[i].task = NULL;
382 pm8001_ha->ccb_info[i].ccb_tag = 0xffffffff;
383 pm8001_ha->ccb_info[i].device = NULL;
384 ++pm8001_ha->tags_num;
385 }
386 pm8001_ha->flags = PM8001F_INIT_TIME;
387
388 pm8001_tag_init(pm8001_ha);
389 return 0;
390err_out:
391 return 1;
392}
393
394
395
396
397
398
399static int pm8001_ioremap(struct pm8001_hba_info *pm8001_ha)
400{
401 u32 bar;
402 u32 logicalBar = 0;
403 struct pci_dev *pdev;
404
405 pdev = pm8001_ha->pdev;
406
407 for (bar = 0; bar < 6; bar++) {
408
409
410
411
412
413
414
415
416 if ((bar == 1) || (bar == 3))
417 continue;
418 if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
419 pm8001_ha->io_mem[logicalBar].membase =
420 pci_resource_start(pdev, bar);
421 pm8001_ha->io_mem[logicalBar].memsize =
422 pci_resource_len(pdev, bar);
423 pm8001_ha->io_mem[logicalBar].memvirtaddr =
424 ioremap(pm8001_ha->io_mem[logicalBar].membase,
425 pm8001_ha->io_mem[logicalBar].memsize);
426 PM8001_INIT_DBG(pm8001_ha,
427 pm8001_printk("PCI: bar %d, logicalBar %d ",
428 bar, logicalBar));
429 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
430 "base addr %llx virt_addr=%llx len=%d\n",
431 (u64)pm8001_ha->io_mem[logicalBar].membase,
432 (u64)(unsigned long)
433 pm8001_ha->io_mem[logicalBar].memvirtaddr,
434 pm8001_ha->io_mem[logicalBar].memsize));
435 } else {
436 pm8001_ha->io_mem[logicalBar].membase = 0;
437 pm8001_ha->io_mem[logicalBar].memsize = 0;
438 pm8001_ha->io_mem[logicalBar].memvirtaddr = 0;
439 }
440 logicalBar++;
441 }
442 return 0;
443}
444
445
446
447
448
449
450
451static struct pm8001_hba_info *pm8001_pci_alloc(struct pci_dev *pdev,
452 const struct pci_device_id *ent,
453 struct Scsi_Host *shost)
454
455{
456 struct pm8001_hba_info *pm8001_ha;
457 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
458 int j;
459
460 pm8001_ha = sha->lldd_ha;
461 if (!pm8001_ha)
462 return NULL;
463
464 pm8001_ha->pdev = pdev;
465 pm8001_ha->dev = &pdev->dev;
466 pm8001_ha->chip_id = ent->driver_data;
467 pm8001_ha->chip = &pm8001_chips[pm8001_ha->chip_id];
468 pm8001_ha->irq = pdev->irq;
469 pm8001_ha->sas = sha;
470 pm8001_ha->shost = shost;
471 pm8001_ha->id = pm8001_id++;
472 pm8001_ha->logging_level = 0x01;
473 sprintf(pm8001_ha->name, "%s%d", DRV_NAME, pm8001_ha->id);
474
475 if (pm8001_ha->chip_id != chip_8001)
476 pm8001_ha->iomb_size = IOMB_SIZE_SPCV;
477 else
478 pm8001_ha->iomb_size = IOMB_SIZE_SPC;
479
480#ifdef PM8001_USE_TASKLET
481
482 if ((!pdev->msix_cap || !pci_msi_enabled())
483 || (pm8001_ha->chip_id == chip_8001))
484 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
485 (unsigned long)&(pm8001_ha->irq_vector[0]));
486 else
487 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
488 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
489 (unsigned long)&(pm8001_ha->irq_vector[j]));
490#endif
491 pm8001_ioremap(pm8001_ha);
492 if (!pm8001_alloc(pm8001_ha, ent))
493 return pm8001_ha;
494 pm8001_free(pm8001_ha);
495 return NULL;
496}
497
498
499
500
501
502static int pci_go_44(struct pci_dev *pdev)
503{
504 int rc;
505
506 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(44))) {
507 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(44));
508 if (rc) {
509 rc = pci_set_consistent_dma_mask(pdev,
510 DMA_BIT_MASK(32));
511 if (rc) {
512 dev_printk(KERN_ERR, &pdev->dev,
513 "44-bit DMA enable failed\n");
514 return rc;
515 }
516 }
517 } else {
518 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
519 if (rc) {
520 dev_printk(KERN_ERR, &pdev->dev,
521 "32-bit DMA enable failed\n");
522 return rc;
523 }
524 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
525 if (rc) {
526 dev_printk(KERN_ERR, &pdev->dev,
527 "32-bit consistent DMA enable failed\n");
528 return rc;
529 }
530 }
531 return rc;
532}
533
534
535
536
537
538
539static int pm8001_prep_sas_ha_init(struct Scsi_Host *shost,
540 const struct pm8001_chip_info *chip_info)
541{
542 int phy_nr, port_nr;
543 struct asd_sas_phy **arr_phy;
544 struct asd_sas_port **arr_port;
545 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
546
547 phy_nr = chip_info->n_phy;
548 port_nr = phy_nr;
549 memset(sha, 0x00, sizeof(*sha));
550 arr_phy = kcalloc(phy_nr, sizeof(void *), GFP_KERNEL);
551 if (!arr_phy)
552 goto exit;
553 arr_port = kcalloc(port_nr, sizeof(void *), GFP_KERNEL);
554 if (!arr_port)
555 goto exit_free2;
556
557 sha->sas_phy = arr_phy;
558 sha->sas_port = arr_port;
559 sha->lldd_ha = kzalloc(sizeof(struct pm8001_hba_info), GFP_KERNEL);
560 if (!sha->lldd_ha)
561 goto exit_free1;
562
563 shost->transportt = pm8001_stt;
564 shost->max_id = PM8001_MAX_DEVICES;
565 shost->max_lun = 8;
566 shost->max_channel = 0;
567 shost->unique_id = pm8001_id;
568 shost->max_cmd_len = 16;
569 shost->can_queue = PM8001_CAN_QUEUE;
570 shost->cmd_per_lun = 32;
571 return 0;
572exit_free1:
573 kfree(arr_port);
574exit_free2:
575 kfree(arr_phy);
576exit:
577 return -1;
578}
579
580
581
582
583
584
585static void pm8001_post_sas_ha_init(struct Scsi_Host *shost,
586 const struct pm8001_chip_info *chip_info)
587{
588 int i = 0;
589 struct pm8001_hba_info *pm8001_ha;
590 struct sas_ha_struct *sha = SHOST_TO_SAS_HA(shost);
591
592 pm8001_ha = sha->lldd_ha;
593 for (i = 0; i < chip_info->n_phy; i++) {
594 sha->sas_phy[i] = &pm8001_ha->phy[i].sas_phy;
595 sha->sas_port[i] = &pm8001_ha->port[i].sas_port;
596 }
597 sha->sas_ha_name = DRV_NAME;
598 sha->dev = pm8001_ha->dev;
599
600 sha->lldd_module = THIS_MODULE;
601 sha->sas_addr = &pm8001_ha->sas_addr[0];
602 sha->num_phys = chip_info->n_phy;
603 sha->core.shost = shost;
604}
605
606
607
608
609
610
611
612
613static void pm8001_init_sas_add(struct pm8001_hba_info *pm8001_ha)
614{
615 u8 i, j;
616#ifdef PM8001_READ_VPD
617
618
619
620
621 DECLARE_COMPLETION_ONSTACK(completion);
622 struct pm8001_ioctl_payload payload;
623 u16 deviceid;
624 int rc;
625
626 pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
627 pm8001_ha->nvmd_completion = &completion;
628
629 if (pm8001_ha->chip_id == chip_8001) {
630 if (deviceid == 0x8081 || deviceid == 0x0042) {
631 payload.minor_function = 4;
632 payload.length = 4096;
633 } else {
634 payload.minor_function = 0;
635 payload.length = 128;
636 }
637 } else if ((pm8001_ha->chip_id == chip_8070 ||
638 pm8001_ha->chip_id == chip_8072) &&
639 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
640 payload.minor_function = 4;
641 payload.length = 4096;
642 } else {
643 payload.minor_function = 1;
644 payload.length = 4096;
645 }
646 payload.offset = 0;
647 payload.func_specific = kzalloc(payload.length, GFP_KERNEL);
648 if (!payload.func_specific) {
649 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("mem alloc fail\n"));
650 return;
651 }
652 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
653 if (rc) {
654 kfree(payload.func_specific);
655 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
656 return;
657 }
658 wait_for_completion(&completion);
659
660 for (i = 0, j = 0; i <= 7; i++, j++) {
661 if (pm8001_ha->chip_id == chip_8001) {
662 if (deviceid == 0x8081)
663 pm8001_ha->sas_addr[j] =
664 payload.func_specific[0x704 + i];
665 else if (deviceid == 0x0042)
666 pm8001_ha->sas_addr[j] =
667 payload.func_specific[0x010 + i];
668 } else if ((pm8001_ha->chip_id == chip_8070 ||
669 pm8001_ha->chip_id == chip_8072) &&
670 pm8001_ha->pdev->subsystem_vendor == PCI_VENDOR_ID_ATTO) {
671 pm8001_ha->sas_addr[j] =
672 payload.func_specific[0x010 + i];
673 } else
674 pm8001_ha->sas_addr[j] =
675 payload.func_specific[0x804 + i];
676 }
677
678 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
679 memcpy(&pm8001_ha->phy[i].dev_sas_addr,
680 pm8001_ha->sas_addr, SAS_ADDR_SIZE);
681 PM8001_INIT_DBG(pm8001_ha,
682 pm8001_printk("phy %d sas_addr = %016llx\n", i,
683 pm8001_ha->phy[i].dev_sas_addr));
684 }
685 kfree(payload.func_specific);
686#else
687 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
688 pm8001_ha->phy[i].dev_sas_addr = 0x50010c600047f9d0ULL;
689 pm8001_ha->phy[i].dev_sas_addr =
690 cpu_to_be64((u64)
691 (*(u64 *)&pm8001_ha->phy[i].dev_sas_addr));
692 }
693 memcpy(pm8001_ha->sas_addr, &pm8001_ha->phy[0].dev_sas_addr,
694 SAS_ADDR_SIZE);
695#endif
696}
697
698
699
700
701
702static int pm8001_get_phy_settings_info(struct pm8001_hba_info *pm8001_ha)
703{
704
705#ifdef PM8001_READ_VPD
706
707 DECLARE_COMPLETION_ONSTACK(completion);
708 struct pm8001_ioctl_payload payload;
709 int rc;
710
711 pm8001_ha->nvmd_completion = &completion;
712
713 payload.minor_function = 6;
714 payload.offset = 0;
715 payload.length = 4096;
716 payload.func_specific = kzalloc(4096, GFP_KERNEL);
717 if (!payload.func_specific)
718 return -ENOMEM;
719
720 rc = PM8001_CHIP_DISP->get_nvmd_req(pm8001_ha, &payload);
721 if (rc) {
722 kfree(payload.func_specific);
723 PM8001_INIT_DBG(pm8001_ha, pm8001_printk("nvmd failed\n"));
724 return -ENOMEM;
725 }
726 wait_for_completion(&completion);
727 pm8001_set_phy_profile(pm8001_ha, sizeof(u8), payload.func_specific);
728 kfree(payload.func_specific);
729#endif
730 return 0;
731}
732
733struct pm8001_mpi3_phy_pg_trx_config {
734 u32 LaneLosCfg;
735 u32 LanePgaCfg1;
736 u32 LanePisoCfg1;
737 u32 LanePisoCfg2;
738 u32 LanePisoCfg3;
739 u32 LanePisoCfg4;
740 u32 LanePisoCfg5;
741 u32 LanePisoCfg6;
742 u32 LaneBctCtrl;
743};
744
745
746
747
748
749
750static
751void pm8001_get_internal_phy_settings(struct pm8001_hba_info *pm8001_ha,
752 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
753{
754 phycfg->LaneLosCfg = 0x00000132;
755 phycfg->LanePgaCfg1 = 0x00203949;
756 phycfg->LanePisoCfg1 = 0x000000FF;
757 phycfg->LanePisoCfg2 = 0xFF000001;
758 phycfg->LanePisoCfg3 = 0xE7011300;
759 phycfg->LanePisoCfg4 = 0x631C40C0;
760 phycfg->LanePisoCfg5 = 0xF8102036;
761 phycfg->LanePisoCfg6 = 0xF74A1000;
762 phycfg->LaneBctCtrl = 0x00FB33F8;
763}
764
765
766
767
768
769
770static
771void pm8001_get_external_phy_settings(struct pm8001_hba_info *pm8001_ha,
772 struct pm8001_mpi3_phy_pg_trx_config *phycfg)
773{
774 phycfg->LaneLosCfg = 0x00000132;
775 phycfg->LanePgaCfg1 = 0x00203949;
776 phycfg->LanePisoCfg1 = 0x000000FF;
777 phycfg->LanePisoCfg2 = 0xFF000001;
778 phycfg->LanePisoCfg3 = 0xE7011300;
779 phycfg->LanePisoCfg4 = 0x63349140;
780 phycfg->LanePisoCfg5 = 0xF8102036;
781 phycfg->LanePisoCfg6 = 0xF80D9300;
782 phycfg->LaneBctCtrl = 0x00FB33F8;
783}
784
785
786
787
788
789
790static
791void pm8001_get_phy_mask(struct pm8001_hba_info *pm8001_ha, int *phymask)
792{
793 switch (pm8001_ha->pdev->subsystem_device) {
794 case 0x0070:
795 case 0x0072:
796 *phymask = 0x0000;
797 break;
798
799 case 0x0071:
800 case 0x0073:
801 *phymask = 0xFFFF;
802 break;
803
804 case 0x0080:
805 *phymask = 0x00F0;
806 break;
807
808 case 0x0081:
809 *phymask = 0x0FF0;
810 break;
811
812 case 0x0082:
813 *phymask = 0xFF00;
814 break;
815
816 default:
817 PM8001_INIT_DBG(pm8001_ha,
818 pm8001_printk("Unknown subsystem device=0x%.04x",
819 pm8001_ha->pdev->subsystem_device));
820 }
821}
822
823
824
825
826
827static
828int pm8001_set_phy_settings_ven_117c_12G(struct pm8001_hba_info *pm8001_ha)
829{
830 struct pm8001_mpi3_phy_pg_trx_config phycfg_int;
831 struct pm8001_mpi3_phy_pg_trx_config phycfg_ext;
832 int phymask = 0;
833 int i = 0;
834
835 memset(&phycfg_int, 0, sizeof(phycfg_int));
836 memset(&phycfg_ext, 0, sizeof(phycfg_ext));
837
838 pm8001_get_internal_phy_settings(pm8001_ha, &phycfg_int);
839 pm8001_get_external_phy_settings(pm8001_ha, &phycfg_ext);
840 pm8001_get_phy_mask(pm8001_ha, &phymask);
841
842 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
843 if (phymask & (1 << i)) {
844 pm8001_set_phy_profile_single(pm8001_ha, i,
845 sizeof(phycfg_int) / sizeof(u32),
846 (u32 *)&phycfg_int);
847
848 } else {
849 pm8001_set_phy_profile_single(pm8001_ha, i,
850 sizeof(phycfg_ext) / sizeof(u32),
851 (u32 *)&phycfg_ext);
852 }
853 }
854
855 return 0;
856}
857
858
859
860
861
862static int pm8001_configure_phy_settings(struct pm8001_hba_info *pm8001_ha)
863{
864 switch (pm8001_ha->pdev->subsystem_vendor) {
865 case PCI_VENDOR_ID_ATTO:
866 if (pm8001_ha->pdev->device == 0x0042)
867 return 0;
868 else
869 return pm8001_set_phy_settings_ven_117c_12G(pm8001_ha);
870
871 case PCI_VENDOR_ID_ADAPTEC2:
872 case 0:
873 return 0;
874
875 default:
876 return pm8001_get_phy_settings_info(pm8001_ha);
877 }
878}
879
880#ifdef PM8001_USE_MSIX
881
882
883
884
885
886static u32 pm8001_setup_msix(struct pm8001_hba_info *pm8001_ha)
887{
888 u32 i = 0, j = 0;
889 u32 number_of_intr;
890 int flag = 0;
891 int rc;
892 static char intr_drvname[PM8001_MAX_MSIX_VEC][sizeof(DRV_NAME)+3];
893
894
895 if (pm8001_ha->chip_id == chip_8001) {
896 number_of_intr = 1;
897 } else {
898 number_of_intr = PM8001_MAX_MSIX_VEC;
899 flag &= ~IRQF_SHARED;
900 }
901
902 rc = pci_alloc_irq_vectors(pm8001_ha->pdev, number_of_intr,
903 number_of_intr, PCI_IRQ_MSIX);
904 if (rc < 0)
905 return rc;
906 pm8001_ha->number_of_intr = number_of_intr;
907
908 PM8001_INIT_DBG(pm8001_ha, pm8001_printk(
909 "pci_alloc_irq_vectors request ret:%d no of intr %d\n",
910 rc, pm8001_ha->number_of_intr));
911
912 for (i = 0; i < number_of_intr; i++) {
913 snprintf(intr_drvname[i], sizeof(intr_drvname[0]),
914 DRV_NAME"%d", i);
915 pm8001_ha->irq_vector[i].irq_id = i;
916 pm8001_ha->irq_vector[i].drv_inst = pm8001_ha;
917
918 rc = request_irq(pci_irq_vector(pm8001_ha->pdev, i),
919 pm8001_interrupt_handler_msix, flag,
920 intr_drvname[i], &(pm8001_ha->irq_vector[i]));
921 if (rc) {
922 for (j = 0; j < i; j++) {
923 free_irq(pci_irq_vector(pm8001_ha->pdev, i),
924 &(pm8001_ha->irq_vector[i]));
925 }
926 pci_free_irq_vectors(pm8001_ha->pdev);
927 break;
928 }
929 }
930
931 return rc;
932}
933#endif
934
935
936
937
938
939static u32 pm8001_request_irq(struct pm8001_hba_info *pm8001_ha)
940{
941 struct pci_dev *pdev;
942 int rc;
943
944 pdev = pm8001_ha->pdev;
945
946#ifdef PM8001_USE_MSIX
947 if (pdev->msix_cap && pci_msi_enabled())
948 return pm8001_setup_msix(pm8001_ha);
949 else {
950 PM8001_INIT_DBG(pm8001_ha,
951 pm8001_printk("MSIX not supported!!!\n"));
952 goto intx;
953 }
954#endif
955
956intx:
957
958 pm8001_ha->irq_vector[0].irq_id = 0;
959 pm8001_ha->irq_vector[0].drv_inst = pm8001_ha;
960 rc = request_irq(pdev->irq, pm8001_interrupt_handler_intx, IRQF_SHARED,
961 DRV_NAME, SHOST_TO_SAS_HA(pm8001_ha->shost));
962 return rc;
963}
964
965
966
967
968
969
970
971
972
973
974static int pm8001_pci_probe(struct pci_dev *pdev,
975 const struct pci_device_id *ent)
976{
977 unsigned int rc;
978 u32 pci_reg;
979 u8 i = 0;
980 struct pm8001_hba_info *pm8001_ha;
981 struct Scsi_Host *shost = NULL;
982 const struct pm8001_chip_info *chip;
983
984 dev_printk(KERN_INFO, &pdev->dev,
985 "pm80xx: driver version %s\n", DRV_VERSION);
986 rc = pci_enable_device(pdev);
987 if (rc)
988 goto err_out_enable;
989 pci_set_master(pdev);
990
991
992
993
994
995 pci_read_config_dword(pdev, PCI_COMMAND, &pci_reg);
996 pci_reg |= 0x157;
997 pci_write_config_dword(pdev, PCI_COMMAND, pci_reg);
998 rc = pci_request_regions(pdev, DRV_NAME);
999 if (rc)
1000 goto err_out_disable;
1001 rc = pci_go_44(pdev);
1002 if (rc)
1003 goto err_out_regions;
1004
1005 shost = scsi_host_alloc(&pm8001_sht, sizeof(void *));
1006 if (!shost) {
1007 rc = -ENOMEM;
1008 goto err_out_regions;
1009 }
1010 chip = &pm8001_chips[ent->driver_data];
1011 SHOST_TO_SAS_HA(shost) =
1012 kzalloc(sizeof(struct sas_ha_struct), GFP_KERNEL);
1013 if (!SHOST_TO_SAS_HA(shost)) {
1014 rc = -ENOMEM;
1015 goto err_out_free_host;
1016 }
1017
1018 rc = pm8001_prep_sas_ha_init(shost, chip);
1019 if (rc) {
1020 rc = -ENOMEM;
1021 goto err_out_free;
1022 }
1023 pci_set_drvdata(pdev, SHOST_TO_SAS_HA(shost));
1024
1025 pm8001_ha = pm8001_pci_alloc(pdev, ent, shost);
1026 if (!pm8001_ha) {
1027 rc = -ENOMEM;
1028 goto err_out_free;
1029 }
1030 list_add_tail(&pm8001_ha->list, &hba_list);
1031 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1032 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1033 if (rc) {
1034 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1035 "chip_init failed [ret: %d]\n", rc));
1036 goto err_out_ha_free;
1037 }
1038
1039 rc = scsi_add_host(shost, &pdev->dev);
1040 if (rc)
1041 goto err_out_ha_free;
1042 rc = pm8001_request_irq(pm8001_ha);
1043 if (rc) {
1044 PM8001_FAIL_DBG(pm8001_ha, pm8001_printk(
1045 "pm8001_request_irq failed [ret: %d]\n", rc));
1046 goto err_out_shost;
1047 }
1048
1049 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1050 if (pm8001_ha->chip_id != chip_8001) {
1051 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1052 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1053
1054 pm80xx_set_thermal_config(pm8001_ha);
1055 }
1056
1057 pm8001_init_sas_add(pm8001_ha);
1058
1059 if (pm8001_configure_phy_settings(pm8001_ha))
1060 goto err_out_shost;
1061
1062 pm8001_post_sas_ha_init(shost, chip);
1063 rc = sas_register_ha(SHOST_TO_SAS_HA(shost));
1064 if (rc)
1065 goto err_out_shost;
1066 scsi_scan_host(pm8001_ha->shost);
1067 return 0;
1068
1069err_out_shost:
1070 scsi_remove_host(pm8001_ha->shost);
1071err_out_ha_free:
1072 pm8001_free(pm8001_ha);
1073err_out_free:
1074 kfree(SHOST_TO_SAS_HA(shost));
1075err_out_free_host:
1076 kfree(shost);
1077err_out_regions:
1078 pci_release_regions(pdev);
1079err_out_disable:
1080 pci_disable_device(pdev);
1081err_out_enable:
1082 return rc;
1083}
1084
1085static void pm8001_pci_remove(struct pci_dev *pdev)
1086{
1087 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1088 struct pm8001_hba_info *pm8001_ha;
1089 int i, j;
1090 pm8001_ha = sha->lldd_ha;
1091 sas_unregister_ha(sha);
1092 sas_remove_host(pm8001_ha->shost);
1093 list_del(&pm8001_ha->list);
1094 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1095 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1096
1097#ifdef PM8001_USE_MSIX
1098 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1099 synchronize_irq(pci_irq_vector(pdev, i));
1100 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1101 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1102 pci_free_irq_vectors(pdev);
1103#else
1104 free_irq(pm8001_ha->irq, sha);
1105#endif
1106#ifdef PM8001_USE_TASKLET
1107
1108 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1109 (pm8001_ha->chip_id == chip_8001))
1110 tasklet_kill(&pm8001_ha->tasklet[0]);
1111 else
1112 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1113 tasklet_kill(&pm8001_ha->tasklet[j]);
1114#endif
1115 pm8001_free(pm8001_ha);
1116 kfree(sha->sas_phy);
1117 kfree(sha->sas_port);
1118 kfree(sha);
1119 pci_release_regions(pdev);
1120 pci_disable_device(pdev);
1121}
1122
1123
1124
1125
1126
1127
1128
1129
1130static int pm8001_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1131{
1132 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1133 struct pm8001_hba_info *pm8001_ha;
1134 int i, j;
1135 u32 device_state;
1136 pm8001_ha = sha->lldd_ha;
1137 sas_suspend_ha(sha);
1138 flush_workqueue(pm8001_wq);
1139 scsi_block_requests(pm8001_ha->shost);
1140 if (!pdev->pm_cap) {
1141 dev_err(&pdev->dev, " PCI PM not supported\n");
1142 return -ENODEV;
1143 }
1144 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1145 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1146#ifdef PM8001_USE_MSIX
1147 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1148 synchronize_irq(pci_irq_vector(pdev, i));
1149 for (i = 0; i < pm8001_ha->number_of_intr; i++)
1150 free_irq(pci_irq_vector(pdev, i), &pm8001_ha->irq_vector[i]);
1151 pci_free_irq_vectors(pdev);
1152#else
1153 free_irq(pm8001_ha->irq, sha);
1154#endif
1155#ifdef PM8001_USE_TASKLET
1156
1157 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1158 (pm8001_ha->chip_id == chip_8001))
1159 tasklet_kill(&pm8001_ha->tasklet[0]);
1160 else
1161 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1162 tasklet_kill(&pm8001_ha->tasklet[j]);
1163#endif
1164 device_state = pci_choose_state(pdev, state);
1165 pm8001_printk("pdev=0x%p, slot=%s, entering "
1166 "operating state [D%d]\n", pdev,
1167 pm8001_ha->name, device_state);
1168 pci_save_state(pdev);
1169 pci_disable_device(pdev);
1170 pci_set_power_state(pdev, device_state);
1171 return 0;
1172}
1173
1174
1175
1176
1177
1178
1179
1180static int pm8001_pci_resume(struct pci_dev *pdev)
1181{
1182 struct sas_ha_struct *sha = pci_get_drvdata(pdev);
1183 struct pm8001_hba_info *pm8001_ha;
1184 int rc;
1185 u8 i = 0, j;
1186 u32 device_state;
1187 DECLARE_COMPLETION_ONSTACK(completion);
1188 pm8001_ha = sha->lldd_ha;
1189 device_state = pdev->current_state;
1190
1191 pm8001_printk("pdev=0x%p, slot=%s, resuming from previous "
1192 "operating state [D%d]\n", pdev, pm8001_ha->name, device_state);
1193
1194 pci_set_power_state(pdev, PCI_D0);
1195 pci_enable_wake(pdev, PCI_D0, 0);
1196 pci_restore_state(pdev);
1197 rc = pci_enable_device(pdev);
1198 if (rc) {
1199 pm8001_printk("slot=%s Enable device failed during resume\n",
1200 pm8001_ha->name);
1201 goto err_out_enable;
1202 }
1203
1204 pci_set_master(pdev);
1205 rc = pci_go_44(pdev);
1206 if (rc)
1207 goto err_out_disable;
1208 sas_prep_resume_ha(sha);
1209
1210 if (pm8001_ha->chip_id == chip_8001) {
1211 PM8001_CHIP_DISP->chip_soft_rst(pm8001_ha);
1212 PM8001_INIT_DBG(pm8001_ha,
1213 pm8001_printk("chip soft reset successful\n"));
1214 }
1215 rc = PM8001_CHIP_DISP->chip_init(pm8001_ha);
1216 if (rc)
1217 goto err_out_disable;
1218
1219
1220 PM8001_CHIP_DISP->interrupt_disable(pm8001_ha, 0xFF);
1221
1222 rc = pm8001_request_irq(pm8001_ha);
1223 if (rc)
1224 goto err_out_disable;
1225#ifdef PM8001_USE_TASKLET
1226
1227 if ((!pdev->msix_cap || !pci_msi_enabled()) ||
1228 (pm8001_ha->chip_id == chip_8001))
1229 tasklet_init(&pm8001_ha->tasklet[0], pm8001_tasklet,
1230 (unsigned long)&(pm8001_ha->irq_vector[0]));
1231 else
1232 for (j = 0; j < PM8001_MAX_MSIX_VEC; j++)
1233 tasklet_init(&pm8001_ha->tasklet[j], pm8001_tasklet,
1234 (unsigned long)&(pm8001_ha->irq_vector[j]));
1235#endif
1236 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, 0);
1237 if (pm8001_ha->chip_id != chip_8001) {
1238 for (i = 1; i < pm8001_ha->number_of_intr; i++)
1239 PM8001_CHIP_DISP->interrupt_enable(pm8001_ha, i);
1240 }
1241
1242
1243
1244
1245
1246
1247 if (pm8001_ha->chip_id == chip_8070 ||
1248 pm8001_ha->chip_id == chip_8072) {
1249 mdelay(500);
1250 }
1251
1252
1253
1254 pm8001_ha->flags = PM8001F_RUN_TIME;
1255 for (i = 0; i < pm8001_ha->chip->n_phy; i++) {
1256 pm8001_ha->phy[i].enable_completion = &completion;
1257 PM8001_CHIP_DISP->phy_start_req(pm8001_ha, i);
1258 wait_for_completion(&completion);
1259 }
1260 sas_resume_ha(sha);
1261 return 0;
1262
1263err_out_disable:
1264 scsi_remove_host(pm8001_ha->shost);
1265 pci_disable_device(pdev);
1266err_out_enable:
1267 return rc;
1268}
1269
1270
1271
1272
1273static struct pci_device_id pm8001_pci_table[] = {
1274 { PCI_VDEVICE(PMC_Sierra, 0x8001), chip_8001 },
1275 { PCI_VDEVICE(PMC_Sierra, 0x8006), chip_8006 },
1276 { PCI_VDEVICE(ADAPTEC2, 0x8006), chip_8006 },
1277 { PCI_VDEVICE(ATTO, 0x0042), chip_8001 },
1278
1279 { PCI_VDEVICE(ADAPTEC2, 0x8001), chip_8001 },
1280 { PCI_VDEVICE(PMC_Sierra, 0x8008), chip_8008 },
1281 { PCI_VDEVICE(ADAPTEC2, 0x8008), chip_8008 },
1282 { PCI_VDEVICE(PMC_Sierra, 0x8018), chip_8018 },
1283 { PCI_VDEVICE(ADAPTEC2, 0x8018), chip_8018 },
1284 { PCI_VDEVICE(PMC_Sierra, 0x8009), chip_8009 },
1285 { PCI_VDEVICE(ADAPTEC2, 0x8009), chip_8009 },
1286 { PCI_VDEVICE(PMC_Sierra, 0x8019), chip_8019 },
1287 { PCI_VDEVICE(ADAPTEC2, 0x8019), chip_8019 },
1288 { PCI_VDEVICE(PMC_Sierra, 0x8074), chip_8074 },
1289 { PCI_VDEVICE(ADAPTEC2, 0x8074), chip_8074 },
1290 { PCI_VDEVICE(PMC_Sierra, 0x8076), chip_8076 },
1291 { PCI_VDEVICE(ADAPTEC2, 0x8076), chip_8076 },
1292 { PCI_VDEVICE(PMC_Sierra, 0x8077), chip_8077 },
1293 { PCI_VDEVICE(ADAPTEC2, 0x8077), chip_8077 },
1294 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1295 PCI_VENDOR_ID_ADAPTEC2, 0x0400, 0, 0, chip_8001 },
1296 { PCI_VENDOR_ID_ADAPTEC2, 0x8081,
1297 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8001 },
1298 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1299 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8008 },
1300 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1301 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8008 },
1302 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1303 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8009 },
1304 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1305 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8009 },
1306 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1307 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8018 },
1308 { PCI_VENDOR_ID_ADAPTEC2, 0x8088,
1309 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8018 },
1310 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1311 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8019 },
1312 { PCI_VENDOR_ID_ADAPTEC2, 0x8089,
1313 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8019 },
1314 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1315 PCI_VENDOR_ID_ADAPTEC2, 0x0800, 0, 0, chip_8074 },
1316 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1317 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8076 },
1318 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1319 PCI_VENDOR_ID_ADAPTEC2, 0x1600, 0, 0, chip_8077 },
1320 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1321 PCI_VENDOR_ID_ADAPTEC2, 0x0008, 0, 0, chip_8074 },
1322 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1323 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8076 },
1324 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1325 PCI_VENDOR_ID_ADAPTEC2, 0x0016, 0, 0, chip_8077 },
1326 { PCI_VENDOR_ID_ADAPTEC2, 0x8076,
1327 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8076 },
1328 { PCI_VENDOR_ID_ADAPTEC2, 0x8077,
1329 PCI_VENDOR_ID_ADAPTEC2, 0x0808, 0, 0, chip_8077 },
1330 { PCI_VENDOR_ID_ADAPTEC2, 0x8074,
1331 PCI_VENDOR_ID_ADAPTEC2, 0x0404, 0, 0, chip_8074 },
1332 { PCI_VENDOR_ID_ATTO, 0x8070,
1333 PCI_VENDOR_ID_ATTO, 0x0070, 0, 0, chip_8070 },
1334 { PCI_VENDOR_ID_ATTO, 0x8070,
1335 PCI_VENDOR_ID_ATTO, 0x0071, 0, 0, chip_8070 },
1336 { PCI_VENDOR_ID_ATTO, 0x8072,
1337 PCI_VENDOR_ID_ATTO, 0x0072, 0, 0, chip_8072 },
1338 { PCI_VENDOR_ID_ATTO, 0x8072,
1339 PCI_VENDOR_ID_ATTO, 0x0073, 0, 0, chip_8072 },
1340 { PCI_VENDOR_ID_ATTO, 0x8070,
1341 PCI_VENDOR_ID_ATTO, 0x0080, 0, 0, chip_8070 },
1342 { PCI_VENDOR_ID_ATTO, 0x8072,
1343 PCI_VENDOR_ID_ATTO, 0x0081, 0, 0, chip_8072 },
1344 { PCI_VENDOR_ID_ATTO, 0x8072,
1345 PCI_VENDOR_ID_ATTO, 0x0082, 0, 0, chip_8072 },
1346 {}
1347};
1348
1349static struct pci_driver pm8001_pci_driver = {
1350 .name = DRV_NAME,
1351 .id_table = pm8001_pci_table,
1352 .probe = pm8001_pci_probe,
1353 .remove = pm8001_pci_remove,
1354 .suspend = pm8001_pci_suspend,
1355 .resume = pm8001_pci_resume,
1356};
1357
1358
1359
1360
1361static int __init pm8001_init(void)
1362{
1363 int rc = -ENOMEM;
1364
1365 pm8001_wq = alloc_workqueue("pm80xx", 0, 0);
1366 if (!pm8001_wq)
1367 goto err;
1368
1369 pm8001_id = 0;
1370 pm8001_stt = sas_domain_attach_transport(&pm8001_transport_ops);
1371 if (!pm8001_stt)
1372 goto err_wq;
1373 rc = pci_register_driver(&pm8001_pci_driver);
1374 if (rc)
1375 goto err_tp;
1376 return 0;
1377
1378err_tp:
1379 sas_release_transport(pm8001_stt);
1380err_wq:
1381 destroy_workqueue(pm8001_wq);
1382err:
1383 return rc;
1384}
1385
1386static void __exit pm8001_exit(void)
1387{
1388 pci_unregister_driver(&pm8001_pci_driver);
1389 sas_release_transport(pm8001_stt);
1390 destroy_workqueue(pm8001_wq);
1391}
1392
1393module_init(pm8001_init);
1394module_exit(pm8001_exit);
1395
1396MODULE_AUTHOR("Jack Wang <jack_wang@usish.com>");
1397MODULE_AUTHOR("Anand Kumar Santhanam <AnandKumar.Santhanam@pmcs.com>");
1398MODULE_AUTHOR("Sangeetha Gnanasekaran <Sangeetha.Gnanasekaran@pmcs.com>");
1399MODULE_AUTHOR("Nikith Ganigarakoppal <Nikith.Ganigarakoppal@pmcs.com>");
1400MODULE_DESCRIPTION(
1401 "PMC-Sierra PM8001/8006/8081/8088/8089/8074/8076/8077/8070/8072 "
1402 "SAS/SATA controller driver");
1403MODULE_VERSION(DRV_VERSION);
1404MODULE_LICENSE("GPL");
1405MODULE_DEVICE_TABLE(pci, pm8001_pci_table);
1406
1407
