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9#include <linux/interrupt.h>
10#include <linux/device.h>
11#include <linux/kernel.h>
12#include <linux/sysfs.h>
13#include <linux/i2c.h>
14#include <linux/regulator/consumer.h>
15#include <linux/types.h>
16#include <linux/err.h>
17#include <linux/delay.h>
18#include <linux/module.h>
19
20#include <linux/iio/iio.h>
21#include <linux/iio/sysfs.h>
22#include <linux/iio/buffer.h>
23#include <linux/iio/kfifo_buf.h>
24
25
26#define AD5933_REG_CONTROL_HB 0x80
27#define AD5933_REG_CONTROL_LB 0x81
28#define AD5933_REG_FREQ_START 0x82
29#define AD5933_REG_FREQ_INC 0x85
30#define AD5933_REG_INC_NUM 0x88
31#define AD5933_REG_SETTLING_CYCLES 0x8A
32#define AD5933_REG_STATUS 0x8F
33#define AD5933_REG_TEMP_DATA 0x92
34#define AD5933_REG_REAL_DATA 0x94
35#define AD5933_REG_IMAG_DATA 0x96
36
37
38#define AD5933_CTRL_INIT_START_FREQ (0x1 << 4)
39#define AD5933_CTRL_START_SWEEP (0x2 << 4)
40#define AD5933_CTRL_INC_FREQ (0x3 << 4)
41#define AD5933_CTRL_REPEAT_FREQ (0x4 << 4)
42#define AD5933_CTRL_MEASURE_TEMP (0x9 << 4)
43#define AD5933_CTRL_POWER_DOWN (0xA << 4)
44#define AD5933_CTRL_STANDBY (0xB << 4)
45
46#define AD5933_CTRL_RANGE_2000mVpp (0x0 << 1)
47#define AD5933_CTRL_RANGE_200mVpp (0x1 << 1)
48#define AD5933_CTRL_RANGE_400mVpp (0x2 << 1)
49#define AD5933_CTRL_RANGE_1000mVpp (0x3 << 1)
50#define AD5933_CTRL_RANGE(x) ((x) << 1)
51
52#define AD5933_CTRL_PGA_GAIN_1 (0x1 << 0)
53#define AD5933_CTRL_PGA_GAIN_5 (0x0 << 0)
54
55
56#define AD5933_CTRL_RESET (0x1 << 4)
57#define AD5933_CTRL_INT_SYSCLK (0x0 << 3)
58#define AD5933_CTRL_EXT_SYSCLK (0x1 << 3)
59
60
61#define AD5933_STAT_TEMP_VALID (0x1 << 0)
62#define AD5933_STAT_DATA_VALID (0x1 << 1)
63#define AD5933_STAT_SWEEP_DONE (0x1 << 2)
64
65
66#define AD5933_I2C_BLOCK_WRITE 0xA0
67#define AD5933_I2C_BLOCK_READ 0xA1
68#define AD5933_I2C_ADDR_POINTER 0xB0
69
70
71#define AD5933_INT_OSC_FREQ_Hz 16776000
72#define AD5933_MAX_OUTPUT_FREQ_Hz 100000
73#define AD5933_MAX_RETRIES 100
74
75#define AD5933_OUT_RANGE 1
76#define AD5933_OUT_RANGE_AVAIL 2
77#define AD5933_OUT_SETTLING_CYCLES 3
78#define AD5933_IN_PGA_GAIN 4
79#define AD5933_IN_PGA_GAIN_AVAIL 5
80#define AD5933_FREQ_POINTS 6
81
82#define AD5933_POLL_TIME_ms 10
83#define AD5933_INIT_EXCITATION_TIME_ms 100
84
85
86
87
88
89
90
91
92struct ad5933_platform_data {
93 unsigned long ext_clk_Hz;
94 unsigned short vref_mv;
95};
96
97struct ad5933_state {
98 struct i2c_client *client;
99 struct regulator *reg;
100 struct delayed_work work;
101 struct mutex lock;
102 unsigned long mclk_hz;
103 unsigned char ctrl_hb;
104 unsigned char ctrl_lb;
105 unsigned int range_avail[4];
106 unsigned short vref_mv;
107 unsigned short settling_cycles;
108 unsigned short freq_points;
109 unsigned int freq_start;
110 unsigned int freq_inc;
111 unsigned int state;
112 unsigned int poll_time_jiffies;
113};
114
115static struct ad5933_platform_data ad5933_default_pdata = {
116 .vref_mv = 3300,
117};
118
119static const struct iio_chan_spec ad5933_channels[] = {
120 {
121 .type = IIO_TEMP,
122 .indexed = 1,
123 .channel = 0,
124 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
125 BIT(IIO_CHAN_INFO_SCALE),
126 .address = AD5933_REG_TEMP_DATA,
127 .scan_index = -1,
128 .scan_type = {
129 .sign = 's',
130 .realbits = 14,
131 .storagebits = 16,
132 },
133 }, {
134 .type = IIO_VOLTAGE,
135 .indexed = 1,
136 .channel = 0,
137 .extend_name = "real",
138 .address = AD5933_REG_REAL_DATA,
139 .scan_index = 0,
140 .scan_type = {
141 .sign = 's',
142 .realbits = 16,
143 .storagebits = 16,
144 },
145 }, {
146 .type = IIO_VOLTAGE,
147 .indexed = 1,
148 .channel = 0,
149 .extend_name = "imag",
150 .address = AD5933_REG_IMAG_DATA,
151 .scan_index = 1,
152 .scan_type = {
153 .sign = 's',
154 .realbits = 16,
155 .storagebits = 16,
156 },
157 },
158};
159
160static int ad5933_i2c_write(struct i2c_client *client, u8 reg, u8 len, u8 *data)
161{
162 int ret;
163
164 while (len--) {
165 ret = i2c_smbus_write_byte_data(client, reg++, *data++);
166 if (ret < 0) {
167 dev_err(&client->dev, "I2C write error\n");
168 return ret;
169 }
170 }
171 return 0;
172}
173
174static int ad5933_i2c_read(struct i2c_client *client, u8 reg, u8 len, u8 *data)
175{
176 int ret;
177
178 while (len--) {
179 ret = i2c_smbus_read_byte_data(client, reg++);
180 if (ret < 0) {
181 dev_err(&client->dev, "I2C read error\n");
182 return ret;
183 }
184 *data++ = ret;
185 }
186 return 0;
187}
188
189static int ad5933_cmd(struct ad5933_state *st, unsigned char cmd)
190{
191 unsigned char dat = st->ctrl_hb | cmd;
192
193 return ad5933_i2c_write(st->client,
194 AD5933_REG_CONTROL_HB, 1, &dat);
195}
196
197static int ad5933_reset(struct ad5933_state *st)
198{
199 unsigned char dat = st->ctrl_lb | AD5933_CTRL_RESET;
200
201 return ad5933_i2c_write(st->client,
202 AD5933_REG_CONTROL_LB, 1, &dat);
203}
204
205static int ad5933_wait_busy(struct ad5933_state *st, unsigned char event)
206{
207 unsigned char val, timeout = AD5933_MAX_RETRIES;
208 int ret;
209
210 while (timeout--) {
211 ret = ad5933_i2c_read(st->client, AD5933_REG_STATUS, 1, &val);
212 if (ret < 0)
213 return ret;
214 if (val & event)
215 return val;
216 cpu_relax();
217 mdelay(1);
218 }
219
220 return -EAGAIN;
221}
222
223static int ad5933_set_freq(struct ad5933_state *st,
224 unsigned int reg, unsigned long freq)
225{
226 unsigned long long freqreg;
227 union {
228 __be32 d32;
229 u8 d8[4];
230 } dat;
231
232 freqreg = (u64) freq * (u64) (1 << 27);
233 do_div(freqreg, st->mclk_hz / 4);
234
235 switch (reg) {
236 case AD5933_REG_FREQ_START:
237 st->freq_start = freq;
238 break;
239 case AD5933_REG_FREQ_INC:
240 st->freq_inc = freq;
241 break;
242 default:
243 return -EINVAL;
244 }
245
246 dat.d32 = cpu_to_be32(freqreg);
247 return ad5933_i2c_write(st->client, reg, 3, &dat.d8[1]);
248}
249
250static int ad5933_setup(struct ad5933_state *st)
251{
252 __be16 dat;
253 int ret;
254
255 ret = ad5933_reset(st);
256 if (ret < 0)
257 return ret;
258
259 ret = ad5933_set_freq(st, AD5933_REG_FREQ_START, 10000);
260 if (ret < 0)
261 return ret;
262
263 ret = ad5933_set_freq(st, AD5933_REG_FREQ_INC, 200);
264 if (ret < 0)
265 return ret;
266
267 st->settling_cycles = 10;
268 dat = cpu_to_be16(st->settling_cycles);
269
270 ret = ad5933_i2c_write(st->client,
271 AD5933_REG_SETTLING_CYCLES,
272 2, (u8 *)&dat);
273 if (ret < 0)
274 return ret;
275
276 st->freq_points = 100;
277 dat = cpu_to_be16(st->freq_points);
278
279 return ad5933_i2c_write(st->client, AD5933_REG_INC_NUM, 2, (u8 *)&dat);
280}
281
282static void ad5933_calc_out_ranges(struct ad5933_state *st)
283{
284 int i;
285 unsigned int normalized_3v3[4] = {1980, 198, 383, 970};
286
287 for (i = 0; i < 4; i++)
288 st->range_avail[i] = normalized_3v3[i] * st->vref_mv / 3300;
289
290}
291
292
293
294
295
296static ssize_t ad5933_show_frequency(struct device *dev,
297 struct device_attribute *attr,
298 char *buf)
299{
300 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
301 struct ad5933_state *st = iio_priv(indio_dev);
302 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
303 int ret;
304 unsigned long long freqreg;
305 union {
306 __be32 d32;
307 u8 d8[4];
308 } dat;
309
310 ret = iio_device_claim_direct_mode(indio_dev);
311 if (ret)
312 return ret;
313 ret = ad5933_i2c_read(st->client, this_attr->address, 3, &dat.d8[1]);
314 iio_device_release_direct_mode(indio_dev);
315 if (ret < 0)
316 return ret;
317
318 freqreg = be32_to_cpu(dat.d32) & 0xFFFFFF;
319
320 freqreg = (u64)freqreg * (u64)(st->mclk_hz / 4);
321 do_div(freqreg, 1 << 27);
322
323 return sprintf(buf, "%d\n", (int)freqreg);
324}
325
326static ssize_t ad5933_store_frequency(struct device *dev,
327 struct device_attribute *attr,
328 const char *buf,
329 size_t len)
330{
331 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
332 struct ad5933_state *st = iio_priv(indio_dev);
333 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
334 unsigned long val;
335 int ret;
336
337 ret = kstrtoul(buf, 10, &val);
338 if (ret)
339 return ret;
340
341 if (val > AD5933_MAX_OUTPUT_FREQ_Hz)
342 return -EINVAL;
343
344 ret = iio_device_claim_direct_mode(indio_dev);
345 if (ret)
346 return ret;
347 ret = ad5933_set_freq(st, this_attr->address, val);
348 iio_device_release_direct_mode(indio_dev);
349
350 return ret ? ret : len;
351}
352
353static IIO_DEVICE_ATTR(out_voltage0_freq_start, 0644,
354 ad5933_show_frequency,
355 ad5933_store_frequency,
356 AD5933_REG_FREQ_START);
357
358static IIO_DEVICE_ATTR(out_voltage0_freq_increment, 0644,
359 ad5933_show_frequency,
360 ad5933_store_frequency,
361 AD5933_REG_FREQ_INC);
362
363static ssize_t ad5933_show(struct device *dev,
364 struct device_attribute *attr,
365 char *buf)
366{
367 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
368 struct ad5933_state *st = iio_priv(indio_dev);
369 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
370 int ret = 0, len = 0;
371
372 mutex_lock(&st->lock);
373 switch ((u32)this_attr->address) {
374 case AD5933_OUT_RANGE:
375 len = sprintf(buf, "%u\n",
376 st->range_avail[(st->ctrl_hb >> 1) & 0x3]);
377 break;
378 case AD5933_OUT_RANGE_AVAIL:
379 len = sprintf(buf, "%u %u %u %u\n", st->range_avail[0],
380 st->range_avail[3], st->range_avail[2],
381 st->range_avail[1]);
382 break;
383 case AD5933_OUT_SETTLING_CYCLES:
384 len = sprintf(buf, "%d\n", st->settling_cycles);
385 break;
386 case AD5933_IN_PGA_GAIN:
387 len = sprintf(buf, "%s\n",
388 (st->ctrl_hb & AD5933_CTRL_PGA_GAIN_1) ?
389 "1" : "0.2");
390 break;
391 case AD5933_IN_PGA_GAIN_AVAIL:
392 len = sprintf(buf, "1 0.2\n");
393 break;
394 case AD5933_FREQ_POINTS:
395 len = sprintf(buf, "%d\n", st->freq_points);
396 break;
397 default:
398 ret = -EINVAL;
399 }
400
401 mutex_unlock(&st->lock);
402 return ret ? ret : len;
403}
404
405static ssize_t ad5933_store(struct device *dev,
406 struct device_attribute *attr,
407 const char *buf,
408 size_t len)
409{
410 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
411 struct ad5933_state *st = iio_priv(indio_dev);
412 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
413 u16 val;
414 int i, ret = 0;
415 __be16 dat;
416
417 if (this_attr->address != AD5933_IN_PGA_GAIN) {
418 ret = kstrtou16(buf, 10, &val);
419 if (ret)
420 return ret;
421 }
422
423 ret = iio_device_claim_direct_mode(indio_dev);
424 if (ret)
425 return ret;
426 mutex_lock(&st->lock);
427 switch ((u32)this_attr->address) {
428 case AD5933_OUT_RANGE:
429 ret = -EINVAL;
430 for (i = 0; i < 4; i++)
431 if (val == st->range_avail[i]) {
432 st->ctrl_hb &= ~AD5933_CTRL_RANGE(0x3);
433 st->ctrl_hb |= AD5933_CTRL_RANGE(i);
434 ret = ad5933_cmd(st, 0);
435 break;
436 }
437 break;
438 case AD5933_IN_PGA_GAIN:
439 if (sysfs_streq(buf, "1")) {
440 st->ctrl_hb |= AD5933_CTRL_PGA_GAIN_1;
441 } else if (sysfs_streq(buf, "0.2")) {
442 st->ctrl_hb &= ~AD5933_CTRL_PGA_GAIN_1;
443 } else {
444 ret = -EINVAL;
445 break;
446 }
447 ret = ad5933_cmd(st, 0);
448 break;
449 case AD5933_OUT_SETTLING_CYCLES:
450 val = clamp(val, (u16)0, (u16)0x7FF);
451 st->settling_cycles = val;
452
453
454 if (val > 1022)
455 val = (val >> 2) | (3 << 9);
456 else if (val > 511)
457 val = (val >> 1) | (1 << 9);
458
459 dat = cpu_to_be16(val);
460 ret = ad5933_i2c_write(st->client,
461 AD5933_REG_SETTLING_CYCLES,
462 2, (u8 *)&dat);
463 break;
464 case AD5933_FREQ_POINTS:
465 val = clamp(val, (u16)0, (u16)511);
466 st->freq_points = val;
467
468 dat = cpu_to_be16(val);
469 ret = ad5933_i2c_write(st->client, AD5933_REG_INC_NUM, 2,
470 (u8 *)&dat);
471 break;
472 default:
473 ret = -EINVAL;
474 }
475
476 mutex_unlock(&st->lock);
477 iio_device_release_direct_mode(indio_dev);
478 return ret ? ret : len;
479}
480
481static IIO_DEVICE_ATTR(out_voltage0_scale, 0644,
482 ad5933_show,
483 ad5933_store,
484 AD5933_OUT_RANGE);
485
486static IIO_DEVICE_ATTR(out_voltage0_scale_available, 0444,
487 ad5933_show,
488 NULL,
489 AD5933_OUT_RANGE_AVAIL);
490
491static IIO_DEVICE_ATTR(in_voltage0_scale, 0644,
492 ad5933_show,
493 ad5933_store,
494 AD5933_IN_PGA_GAIN);
495
496static IIO_DEVICE_ATTR(in_voltage0_scale_available, 0444,
497 ad5933_show,
498 NULL,
499 AD5933_IN_PGA_GAIN_AVAIL);
500
501static IIO_DEVICE_ATTR(out_voltage0_freq_points, 0644,
502 ad5933_show,
503 ad5933_store,
504 AD5933_FREQ_POINTS);
505
506static IIO_DEVICE_ATTR(out_voltage0_settling_cycles, 0644,
507 ad5933_show,
508 ad5933_store,
509 AD5933_OUT_SETTLING_CYCLES);
510
511
512
513
514
515
516static struct attribute *ad5933_attributes[] = {
517 &iio_dev_attr_out_voltage0_scale.dev_attr.attr,
518 &iio_dev_attr_out_voltage0_scale_available.dev_attr.attr,
519 &iio_dev_attr_out_voltage0_freq_start.dev_attr.attr,
520 &iio_dev_attr_out_voltage0_freq_increment.dev_attr.attr,
521 &iio_dev_attr_out_voltage0_freq_points.dev_attr.attr,
522 &iio_dev_attr_out_voltage0_settling_cycles.dev_attr.attr,
523 &iio_dev_attr_in_voltage0_scale.dev_attr.attr,
524 &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
525 NULL
526};
527
528static const struct attribute_group ad5933_attribute_group = {
529 .attrs = ad5933_attributes,
530};
531
532static int ad5933_read_raw(struct iio_dev *indio_dev,
533 struct iio_chan_spec const *chan,
534 int *val,
535 int *val2,
536 long m)
537{
538 struct ad5933_state *st = iio_priv(indio_dev);
539 __be16 dat;
540 int ret;
541
542 switch (m) {
543 case IIO_CHAN_INFO_RAW:
544 ret = iio_device_claim_direct_mode(indio_dev);
545 if (ret)
546 return ret;
547 ret = ad5933_cmd(st, AD5933_CTRL_MEASURE_TEMP);
548 if (ret < 0)
549 goto out;
550 ret = ad5933_wait_busy(st, AD5933_STAT_TEMP_VALID);
551 if (ret < 0)
552 goto out;
553
554 ret = ad5933_i2c_read(st->client,
555 AD5933_REG_TEMP_DATA,
556 2, (u8 *)&dat);
557 if (ret < 0)
558 goto out;
559 iio_device_release_direct_mode(indio_dev);
560 *val = sign_extend32(be16_to_cpu(dat), 13);
561
562 return IIO_VAL_INT;
563 case IIO_CHAN_INFO_SCALE:
564 *val = 1000;
565 *val2 = 5;
566 return IIO_VAL_FRACTIONAL_LOG2;
567 }
568
569 return -EINVAL;
570out:
571 iio_device_release_direct_mode(indio_dev);
572 return ret;
573}
574
575static const struct iio_info ad5933_info = {
576 .read_raw = ad5933_read_raw,
577 .attrs = &ad5933_attribute_group,
578 .driver_module = THIS_MODULE,
579};
580
581static int ad5933_ring_preenable(struct iio_dev *indio_dev)
582{
583 struct ad5933_state *st = iio_priv(indio_dev);
584 int ret;
585
586 if (bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
587 return -EINVAL;
588
589 ret = ad5933_reset(st);
590 if (ret < 0)
591 return ret;
592
593 ret = ad5933_cmd(st, AD5933_CTRL_STANDBY);
594 if (ret < 0)
595 return ret;
596
597 ret = ad5933_cmd(st, AD5933_CTRL_INIT_START_FREQ);
598 if (ret < 0)
599 return ret;
600
601 st->state = AD5933_CTRL_INIT_START_FREQ;
602
603 return 0;
604}
605
606static int ad5933_ring_postenable(struct iio_dev *indio_dev)
607{
608 struct ad5933_state *st = iio_priv(indio_dev);
609
610
611
612
613
614
615
616
617
618
619
620 schedule_delayed_work(&st->work,
621 msecs_to_jiffies(AD5933_INIT_EXCITATION_TIME_ms));
622 return 0;
623}
624
625static int ad5933_ring_postdisable(struct iio_dev *indio_dev)
626{
627 struct ad5933_state *st = iio_priv(indio_dev);
628
629 cancel_delayed_work_sync(&st->work);
630 return ad5933_cmd(st, AD5933_CTRL_POWER_DOWN);
631}
632
633static const struct iio_buffer_setup_ops ad5933_ring_setup_ops = {
634 .preenable = ad5933_ring_preenable,
635 .postenable = ad5933_ring_postenable,
636 .postdisable = ad5933_ring_postdisable,
637};
638
639static int ad5933_register_ring_funcs_and_init(struct iio_dev *indio_dev)
640{
641 struct iio_buffer *buffer;
642
643 buffer = iio_kfifo_allocate();
644 if (!buffer)
645 return -ENOMEM;
646
647 iio_device_attach_buffer(indio_dev, buffer);
648
649
650 indio_dev->setup_ops = &ad5933_ring_setup_ops;
651
652 indio_dev->modes |= INDIO_BUFFER_HARDWARE;
653
654 return 0;
655}
656
657static void ad5933_work(struct work_struct *work)
658{
659 struct ad5933_state *st = container_of(work,
660 struct ad5933_state, work.work);
661 struct iio_dev *indio_dev = i2c_get_clientdata(st->client);
662 __be16 buf[2];
663 int val[2];
664 unsigned char status;
665 int ret;
666
667 if (st->state == AD5933_CTRL_INIT_START_FREQ) {
668
669 ad5933_cmd(st, AD5933_CTRL_START_SWEEP);
670 st->state = AD5933_CTRL_START_SWEEP;
671 schedule_delayed_work(&st->work, st->poll_time_jiffies);
672 return;
673 }
674
675 ret = ad5933_i2c_read(st->client, AD5933_REG_STATUS, 1, &status);
676 if (ret)
677 return;
678
679 if (status & AD5933_STAT_DATA_VALID) {
680 int scan_count = bitmap_weight(indio_dev->active_scan_mask,
681 indio_dev->masklength);
682 ret = ad5933_i2c_read(st->client,
683 test_bit(1, indio_dev->active_scan_mask) ?
684 AD5933_REG_REAL_DATA : AD5933_REG_IMAG_DATA,
685 scan_count * 2, (u8 *)buf);
686 if (ret)
687 return;
688
689 if (scan_count == 2) {
690 val[0] = be16_to_cpu(buf[0]);
691 val[1] = be16_to_cpu(buf[1]);
692 } else {
693 val[0] = be16_to_cpu(buf[0]);
694 }
695 iio_push_to_buffers(indio_dev, val);
696 } else {
697
698 schedule_delayed_work(&st->work, st->poll_time_jiffies);
699 return;
700 }
701
702 if (status & AD5933_STAT_SWEEP_DONE) {
703
704
705
706 ad5933_cmd(st, AD5933_CTRL_POWER_DOWN);
707 } else {
708
709 ad5933_cmd(st, AD5933_CTRL_INC_FREQ);
710 schedule_delayed_work(&st->work, st->poll_time_jiffies);
711 }
712}
713
714static int ad5933_probe(struct i2c_client *client,
715 const struct i2c_device_id *id)
716{
717 int ret, voltage_uv = 0;
718 struct ad5933_platform_data *pdata = dev_get_platdata(&client->dev);
719 struct ad5933_state *st;
720 struct iio_dev *indio_dev;
721
722 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*st));
723 if (!indio_dev)
724 return -ENOMEM;
725
726 st = iio_priv(indio_dev);
727 i2c_set_clientdata(client, indio_dev);
728 st->client = client;
729
730 mutex_init(&st->lock);
731
732 if (!pdata)
733 pdata = &ad5933_default_pdata;
734
735 st->reg = devm_regulator_get(&client->dev, "vdd");
736 if (IS_ERR(st->reg))
737 return PTR_ERR(st->reg);
738
739 ret = regulator_enable(st->reg);
740 if (ret) {
741 dev_err(&client->dev, "Failed to enable specified VDD supply\n");
742 return ret;
743 }
744 voltage_uv = regulator_get_voltage(st->reg);
745
746 if (voltage_uv)
747 st->vref_mv = voltage_uv / 1000;
748 else
749 st->vref_mv = pdata->vref_mv;
750
751 if (pdata->ext_clk_Hz) {
752 st->mclk_hz = pdata->ext_clk_Hz;
753 st->ctrl_lb = AD5933_CTRL_EXT_SYSCLK;
754 } else {
755 st->mclk_hz = AD5933_INT_OSC_FREQ_Hz;
756 st->ctrl_lb = AD5933_CTRL_INT_SYSCLK;
757 }
758
759 ad5933_calc_out_ranges(st);
760 INIT_DELAYED_WORK(&st->work, ad5933_work);
761 st->poll_time_jiffies = msecs_to_jiffies(AD5933_POLL_TIME_ms);
762
763 indio_dev->dev.parent = &client->dev;
764 indio_dev->info = &ad5933_info;
765 indio_dev->name = id->name;
766 indio_dev->modes = INDIO_DIRECT_MODE;
767 indio_dev->channels = ad5933_channels;
768 indio_dev->num_channels = ARRAY_SIZE(ad5933_channels);
769
770 ret = ad5933_register_ring_funcs_and_init(indio_dev);
771 if (ret)
772 goto error_disable_reg;
773
774 ret = ad5933_setup(st);
775 if (ret)
776 goto error_unreg_ring;
777
778 ret = iio_device_register(indio_dev);
779 if (ret)
780 goto error_unreg_ring;
781
782 return 0;
783
784error_unreg_ring:
785 iio_kfifo_free(indio_dev->buffer);
786error_disable_reg:
787 regulator_disable(st->reg);
788
789 return ret;
790}
791
792static int ad5933_remove(struct i2c_client *client)
793{
794 struct iio_dev *indio_dev = i2c_get_clientdata(client);
795 struct ad5933_state *st = iio_priv(indio_dev);
796
797 iio_device_unregister(indio_dev);
798 iio_kfifo_free(indio_dev->buffer);
799 regulator_disable(st->reg);
800
801 return 0;
802}
803
804static const struct i2c_device_id ad5933_id[] = {
805 { "ad5933", 0 },
806 { "ad5934", 0 },
807 {}
808};
809
810MODULE_DEVICE_TABLE(i2c, ad5933_id);
811
812static struct i2c_driver ad5933_driver = {
813 .driver = {
814 .name = "ad5933",
815 },
816 .probe = ad5933_probe,
817 .remove = ad5933_remove,
818 .id_table = ad5933_id,
819};
820module_i2c_driver(ad5933_driver);
821
822MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
823MODULE_DESCRIPTION("Analog Devices AD5933 Impedance Conv. Network Analyzer");
824MODULE_LICENSE("GPL v2");
825
