LXR linux/drivers/staging/media/atomisp/i2c/gc0310.h

   1/*
   2 * Support for GalaxyCore GC0310 VGA camera sensor.
   3 *
   4 * Copyright (c) 2013 Intel Corporation. All Rights Reserved.
   5 *
   6 * This program is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU General Public License version
   8 * 2 as published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  18 * 02110-1301, USA.
  19 *
  20 */
  21
  22#ifndef __GC0310_H__
  23#define __GC0310_H__
  24#include <linux/kernel.h>
  25#include <linux/types.h>
  26#include <linux/i2c.h>
  27#include <linux/acpi.h>
  28#include <linux/delay.h>
  29#include <linux/videodev2.h>
  30#include <linux/spinlock.h>
  31#include <media/v4l2-subdev.h>
  32#include <media/v4l2-device.h>
  33#include <media/v4l2-ctrls.h>
  34#include <linux/v4l2-mediabus.h>
  35#include <media/media-entity.h>
  36
  37#include "../include/linux/atomisp_platform.h"
  38
  39#define GC0310_NAME             "gc0310"
  40
  41/* Defines for register writes and register array processing */
  42#define I2C_MSG_LENGTH          1
  43#define I2C_RETRY_COUNT         5
  44
  45#define GC0310_FOCAL_LENGTH_NUM 278     /*2.78mm*/
  46#define GC0310_FOCAL_LENGTH_DEM 100
  47#define GC0310_F_NUMBER_DEFAULT_NUM     26
  48#define GC0310_F_NUMBER_DEM     10
  49
  50#define MAX_FMTS                1
  51
  52/*
  53 * focal length bits definition:
  54 * bits 31-16: numerator, bits 15-0: denominator
  55 */
  56#define GC0310_FOCAL_LENGTH_DEFAULT 0x1160064
  57
  58/*
  59 * current f-number bits definition:
  60 * bits 31-16: numerator, bits 15-0: denominator
  61 */
  62#define GC0310_F_NUMBER_DEFAULT 0x1a000a
  63
  64/*
  65 * f-number range bits definition:
  66 * bits 31-24: max f-number numerator
  67 * bits 23-16: max f-number denominator
  68 * bits 15-8: min f-number numerator
  69 * bits 7-0: min f-number denominator
  70 */
  71#define GC0310_F_NUMBER_RANGE 0x1a0a1a0a
  72#define GC0310_ID       0xa310
  73
  74#define GC0310_RESET_RELATED            0xFE
  75#define GC0310_REGISTER_PAGE_0          0x0
  76#define GC0310_REGISTER_PAGE_3          0x3
  77
  78#define GC0310_FINE_INTG_TIME_MIN 0
  79#define GC0310_FINE_INTG_TIME_MAX_MARGIN 0
  80#define GC0310_COARSE_INTG_TIME_MIN 1
  81#define GC0310_COARSE_INTG_TIME_MAX_MARGIN 6
  82
  83/*
  84 * GC0310 System control registers
  85 */
  86#define GC0310_SW_STREAM                        0x10
  87
  88#define GC0310_SC_CMMN_CHIP_ID_H                0xf0
  89#define GC0310_SC_CMMN_CHIP_ID_L                0xf1
  90
  91#define GC0310_AEC_PK_EXPO_H                    0x03
  92#define GC0310_AEC_PK_EXPO_L                    0x04
  93#define GC0310_AGC_ADJ                  0x48
  94#define GC0310_DGC_ADJ                  0x71
  95#if 0
  96#define GC0310_GROUP_ACCESS                     0x3208
  97#endif
  98
  99#define GC0310_H_CROP_START_H                   0x09
 100#define GC0310_H_CROP_START_L                   0x0A
 101#define GC0310_V_CROP_START_H                   0x0B
 102#define GC0310_V_CROP_START_L                   0x0C
 103#define GC0310_H_OUTSIZE_H                      0x0F
 104#define GC0310_H_OUTSIZE_L                      0x10
 105#define GC0310_V_OUTSIZE_H                      0x0D
 106#define GC0310_V_OUTSIZE_L                      0x0E
 107#define GC0310_H_BLANKING_H                     0x05
 108#define GC0310_H_BLANKING_L                     0x06
 109#define GC0310_V_BLANKING_H                     0x07
 110#define GC0310_V_BLANKING_L                     0x08
 111#define GC0310_SH_DELAY                 0x11
 112
 113#define GC0310_START_STREAMING                  0x94 /* 8-bit enable */
 114#define GC0310_STOP_STREAMING                   0x0 /* 8-bit disable */
 115
 116#define GC0310_BIN_FACTOR_MAX                   3
 117
 118struct regval_list {
 119        u16 reg_num;
 120        u8 value;
 121};
 122
 123struct gc0310_resolution {
 124        u8 *desc;
 125        const struct gc0310_reg *regs;
 126        int res;
 127        int width;
 128        int height;
 129        int fps;
 130        int pix_clk_freq;
 131        u32 skip_frames;
 132        u16 pixels_per_line;
 133        u16 lines_per_frame;
 134        u8 bin_factor_x;
 135        u8 bin_factor_y;
 136        u8 bin_mode;
 137        bool used;
 138};
 139
 140struct gc0310_format {
 141        u8 *desc;
 142        u32 pixelformat;
 143        struct gc0310_reg *regs;
 144};
 145
 146/*
 147 * gc0310 device structure.
 148 */
 149struct gc0310_device {
 150        struct v4l2_subdev sd;
 151        struct media_pad pad;
 152        struct v4l2_mbus_framefmt format;
 153        struct mutex input_lock;
 154        struct v4l2_ctrl_handler ctrl_handler;
 155
 156        struct camera_sensor_platform_data *platform_data;
 157        int vt_pix_clk_freq_mhz;
 158        int fmt_idx;
 159        int run_mode;
 160        u8 res;
 161        u8 type;
 162};
 163
 164enum gc0310_tok_type {
 165        GC0310_8BIT  = 0x0001,
 166        GC0310_TOK_TERM   = 0xf000,     /* terminating token for reg list */
 167        GC0310_TOK_DELAY  = 0xfe00,     /* delay token for reg list */
 168        GC0310_TOK_MASK = 0xfff0
 169};
 170
 171/**
 172 * struct gc0310_reg - MI sensor  register format
 173 * @type: type of the register
 174 * @reg: 16-bit offset to register
 175 * @val: 8/16/32-bit register value
 176 *
 177 * Define a structure for sensor register initialization values
 178 */
 179struct gc0310_reg {
 180        enum gc0310_tok_type type;
 181        u8 reg;
 182        u8 val; /* @set value for read/mod/write, @mask */
 183};
 184
 185#define to_gc0310_sensor(x) container_of(x, struct gc0310_device, sd)
 186
 187#define GC0310_MAX_WRITE_BUF_SIZE       30
 188
 189struct gc0310_write_buffer {
 190        u8 addr;
 191        u8 data[GC0310_MAX_WRITE_BUF_SIZE];
 192};
 193
 194struct gc0310_write_ctrl {
 195        int index;
 196        struct gc0310_write_buffer buffer;
 197};
 198
 199static const struct i2c_device_id gc0310_id[] = {
 200        {GC0310_NAME, 0},
 201        {}
 202};
 203
 204/*
 205 * Register settings for various resolution
 206 */
 207static const struct gc0310_reg gc0310_reset_register[] = {
 208/////////////////////////////////////////////////
 209/////////////////       system reg      /////////////////
 210/////////////////////////////////////////////////
 211        {GC0310_8BIT, 0xfe, 0xf0},
 212        {GC0310_8BIT, 0xfe, 0xf0},
 213        {GC0310_8BIT, 0xfe, 0x00},
 214
 215        {GC0310_8BIT, 0xfc, 0x0e}, //4e
 216        {GC0310_8BIT, 0xfc, 0x0e}, //16//4e // [0]apwd [6]regf_clk_gate
 217        {GC0310_8BIT, 0xf2, 0x80}, //sync output
 218        {GC0310_8BIT, 0xf3, 0x00}, //1f//01 data output
 219        {GC0310_8BIT, 0xf7, 0x33}, //f9
 220        {GC0310_8BIT, 0xf8, 0x05}, //00
 221        {GC0310_8BIT, 0xf9, 0x0e}, // 0x8e //0f
 222        {GC0310_8BIT, 0xfa, 0x11},
 223
 224/////////////////////////////////////////////////
 225///////////////////   MIPI       ////////////////////
 226/////////////////////////////////////////////////
 227        {GC0310_8BIT, 0xfe, 0x03},
 228        {GC0310_8BIT, 0x01, 0x03}, ///mipi 1lane
 229        {GC0310_8BIT, 0x02, 0x22}, // 0x33
 230        {GC0310_8BIT, 0x03, 0x94},
 231        {GC0310_8BIT, 0x04, 0x01}, // fifo_prog
 232        {GC0310_8BIT, 0x05, 0x00}, //fifo_prog
 233        {GC0310_8BIT, 0x06, 0x80}, //b0  //YUV ISP data
 234        {GC0310_8BIT, 0x11, 0x2a},//1e //LDI set YUV422
 235        {GC0310_8BIT, 0x12, 0x90},//00 //04 //00 //04//00 //LWC[7:0]  //
 236        {GC0310_8BIT, 0x13, 0x02},//05 //05 //LWC[15:8]
 237        {GC0310_8BIT, 0x15, 0x12}, // 0x10 //DPHYY_MODE read_ready
 238        {GC0310_8BIT, 0x17, 0x01},
 239        {GC0310_8BIT, 0x40, 0x08},
 240        {GC0310_8BIT, 0x41, 0x00},
 241        {GC0310_8BIT, 0x42, 0x00},
 242        {GC0310_8BIT, 0x43, 0x00},
 243        {GC0310_8BIT, 0x21, 0x02}, // 0x01
 244        {GC0310_8BIT, 0x22, 0x02}, // 0x01
 245        {GC0310_8BIT, 0x23, 0x01}, // 0x05 //Nor:0x05 DOU:0x06
 246        {GC0310_8BIT, 0x29, 0x00},
 247        {GC0310_8BIT, 0x2A, 0x25}, // 0x05 //data zero 0x7a de
 248        {GC0310_8BIT, 0x2B, 0x02},
 249
 250        {GC0310_8BIT, 0xfe, 0x00},
 251
 252/////////////////////////////////////////////////
 253/////////////////       CISCTL reg      /////////////////
 254/////////////////////////////////////////////////
 255        {GC0310_8BIT, 0x00, 0x2f}, //2f//0f//02//01
 256        {GC0310_8BIT, 0x01, 0x0f}, //06
 257        {GC0310_8BIT, 0x02, 0x04},
 258        {GC0310_8BIT, 0x4f, 0x00}, //AEC 0FF
 259        {GC0310_8BIT, 0x03, 0x01}, // 0x03 //04
 260        {GC0310_8BIT, 0x04, 0xc0}, // 0xe8 //58
 261        {GC0310_8BIT, 0x05, 0x00},
 262        {GC0310_8BIT, 0x06, 0xb2}, // 0x0a //HB
 263        {GC0310_8BIT, 0x07, 0x00},
 264        {GC0310_8BIT, 0x08, 0x0c}, // 0x89 //VB
 265        {GC0310_8BIT, 0x09, 0x00}, //row start
 266        {GC0310_8BIT, 0x0a, 0x00}, //
 267        {GC0310_8BIT, 0x0b, 0x00}, //col start
 268        {GC0310_8BIT, 0x0c, 0x00},
 269        {GC0310_8BIT, 0x0d, 0x01}, //height
 270        {GC0310_8BIT, 0x0e, 0xf2}, // 0xf7 //height
 271        {GC0310_8BIT, 0x0f, 0x02}, //width
 272        {GC0310_8BIT, 0x10, 0x94}, // 0xa0 //height
 273        {GC0310_8BIT, 0x17, 0x14},
 274        {GC0310_8BIT, 0x18, 0x1a}, //0a//[4]double reset
 275        {GC0310_8BIT, 0x19, 0x14}, //AD pipeline
 276        {GC0310_8BIT, 0x1b, 0x48},
 277        {GC0310_8BIT, 0x1e, 0x6b}, //3b//col bias
 278        {GC0310_8BIT, 0x1f, 0x28}, //20//00//08//txlow
 279        {GC0310_8BIT, 0x20, 0x89}, //88//0c//[3:2]DA15
 280        {GC0310_8BIT, 0x21, 0x49}, //48//[3] txhigh
 281        {GC0310_8BIT, 0x22, 0xb0},
 282        {GC0310_8BIT, 0x23, 0x04}, //[1:0]vcm_r
 283        {GC0310_8BIT, 0x24, 0x16}, //15
 284        {GC0310_8BIT, 0x34, 0x20}, //[6:4] rsg high//range
 285
 286/////////////////////////////////////////////////
 287////////////////////   BLK       ////////////////////
 288/////////////////////////////////////////////////
 289        {GC0310_8BIT, 0x26, 0x23}, //[1]dark_current_en [0]offset_en
 290        {GC0310_8BIT, 0x28, 0xff}, //BLK_limie_value
 291        {GC0310_8BIT, 0x29, 0x00}, //global offset
 292        {GC0310_8BIT, 0x33, 0x18}, //offset_ratio
 293        {GC0310_8BIT, 0x37, 0x20}, //dark_current_ratio
 294        {GC0310_8BIT, 0x2a, 0x00},
 295        {GC0310_8BIT, 0x2b, 0x00},
 296        {GC0310_8BIT, 0x2c, 0x00},
 297        {GC0310_8BIT, 0x2d, 0x00},
 298        {GC0310_8BIT, 0x2e, 0x00},
 299        {GC0310_8BIT, 0x2f, 0x00},
 300        {GC0310_8BIT, 0x30, 0x00},
 301        {GC0310_8BIT, 0x31, 0x00},
 302        {GC0310_8BIT, 0x47, 0x80}, //a7
 303        {GC0310_8BIT, 0x4e, 0x66}, //select_row
 304        {GC0310_8BIT, 0xa8, 0x02}, //win_width_dark, same with crop_win_width
 305        {GC0310_8BIT, 0xa9, 0x80},
 306
 307/////////////////////////////////////////////////
 308//////////////////       ISP reg  ///////////////////
 309/////////////////////////////////////////////////
 310        {GC0310_8BIT, 0x40, 0x06}, // 0xff //ff //48
 311        {GC0310_8BIT, 0x41, 0x00}, // 0x21 //00//[0]curve_en
 312        {GC0310_8BIT, 0x42, 0x04}, // 0xcf //0a//[1]awn_en
 313        {GC0310_8BIT, 0x44, 0x18}, // 0x18 //02
 314        {GC0310_8BIT, 0x46, 0x02}, // 0x03 //sync
 315        {GC0310_8BIT, 0x49, 0x03},
 316        {GC0310_8BIT, 0x4c, 0x20}, //00[5]pretect exp
 317        {GC0310_8BIT, 0x50, 0x01}, //crop enable
 318        {GC0310_8BIT, 0x51, 0x00},
 319        {GC0310_8BIT, 0x52, 0x00},
 320        {GC0310_8BIT, 0x53, 0x00},
 321        {GC0310_8BIT, 0x54, 0x01},
 322        {GC0310_8BIT, 0x55, 0x01}, //crop window height
 323        {GC0310_8BIT, 0x56, 0xf0},
 324        {GC0310_8BIT, 0x57, 0x02}, //crop window width
 325        {GC0310_8BIT, 0x58, 0x90},
 326
 327/////////////////////////////////////////////////
 328///////////////////   GAIN       ////////////////////
 329/////////////////////////////////////////////////
 330        {GC0310_8BIT, 0x70, 0x70}, //70 //80//global gain
 331        {GC0310_8BIT, 0x71, 0x20}, // pregain gain
 332        {GC0310_8BIT, 0x72, 0x40}, // post gain
 333        {GC0310_8BIT, 0x5a, 0x84}, //84//analog gain 0
 334        {GC0310_8BIT, 0x5b, 0xc9}, //c9
 335        {GC0310_8BIT, 0x5c, 0xed}, //ed//not use pga gain highest level
 336        {GC0310_8BIT, 0x77, 0x40}, // R gain 0x74 //awb gain
 337        {GC0310_8BIT, 0x78, 0x40}, // G gain
 338        {GC0310_8BIT, 0x79, 0x40}, // B gain 0x5f
 339
 340        {GC0310_8BIT, 0x48, 0x00},
 341        {GC0310_8BIT, 0xfe, 0x01},
 342        {GC0310_8BIT, 0x0a, 0x45}, //[7]col gain mode
 343
 344        {GC0310_8BIT, 0x3e, 0x40},
 345        {GC0310_8BIT, 0x3f, 0x5c},
 346        {GC0310_8BIT, 0x40, 0x7b},
 347        {GC0310_8BIT, 0x41, 0xbd},
 348        {GC0310_8BIT, 0x42, 0xf6},
 349        {GC0310_8BIT, 0x43, 0x63},
 350        {GC0310_8BIT, 0x03, 0x60},
 351        {GC0310_8BIT, 0x44, 0x03},
 352
 353/////////////////////////////////////////////////
 354/////////////////       dark sun   //////////////////
 355/////////////////////////////////////////////////
 356        {GC0310_8BIT, 0xfe, 0x01},
 357        {GC0310_8BIT, 0x45, 0xa4}, // 0xf7
 358        {GC0310_8BIT, 0x46, 0xf0}, // 0xff //f0//sun vaule th
 359        {GC0310_8BIT, 0x48, 0x03}, //sun mode
 360        {GC0310_8BIT, 0x4f, 0x60}, //sun_clamp
 361        {GC0310_8BIT, 0xfe, 0x00},
 362
 363        {GC0310_TOK_TERM, 0, 0},
 364};
 365
 366static struct gc0310_reg const gc0310_VGA_30fps[] = {
 367        {GC0310_8BIT, 0xfe, 0x00},
 368        {GC0310_8BIT, 0x0d, 0x01}, //height
 369        {GC0310_8BIT, 0x0e, 0xf2}, // 0xf7 //height
 370        {GC0310_8BIT, 0x0f, 0x02}, //width
 371        {GC0310_8BIT, 0x10, 0x94}, // 0xa0 //height
 372
 373        {GC0310_8BIT, 0x50, 0x01}, //crop enable
 374        {GC0310_8BIT, 0x51, 0x00},
 375        {GC0310_8BIT, 0x52, 0x00},
 376        {GC0310_8BIT, 0x53, 0x00},
 377        {GC0310_8BIT, 0x54, 0x01},
 378        {GC0310_8BIT, 0x55, 0x01}, //crop window height
 379        {GC0310_8BIT, 0x56, 0xf0},
 380        {GC0310_8BIT, 0x57, 0x02}, //crop window width
 381        {GC0310_8BIT, 0x58, 0x90},
 382
 383        {GC0310_8BIT, 0xfe, 0x03},
 384        {GC0310_8BIT, 0x12, 0x90},//00 //04 //00 //04//00 //LWC[7:0]  //
 385        {GC0310_8BIT, 0x13, 0x02},//05 //05 //LWC[15:8]
 386
 387        {GC0310_8BIT, 0xfe, 0x00},
 388
 389        {GC0310_TOK_TERM, 0, 0},
 390};
 391
 392
 393struct gc0310_resolution gc0310_res_preview[] = {
 394        {
 395                .desc = "gc0310_VGA_30fps",
 396                .width = 656, // 648,
 397                .height = 496, // 488,
 398                .fps = 30,
 399                //.pix_clk_freq = 73,
 400                .used = 0,
 401#if 0
 402                .pixels_per_line = 0x0314,
 403                .lines_per_frame = 0x0213,
 404#endif
 405                .bin_factor_x = 1,
 406                .bin_factor_y = 1,
 407                .bin_mode = 0,
 408                .skip_frames = 2,
 409                .regs = gc0310_VGA_30fps,
 410        },
 411};
 412#define N_RES_PREVIEW (ARRAY_SIZE(gc0310_res_preview))
 413
 414struct gc0310_resolution gc0310_res_still[] = {
 415        {
 416                .desc = "gc0310_VGA_30fps",
 417                .width = 656, // 648,
 418                .height = 496, // 488,
 419                .fps = 30,
 420                //.pix_clk_freq = 73,
 421                .used = 0,
 422#if 0
 423                .pixels_per_line = 0x0314,
 424                .lines_per_frame = 0x0213,
 425#endif
 426                .bin_factor_x = 1,
 427                .bin_factor_y = 1,
 428                .bin_mode = 0,
 429                .skip_frames = 2,
 430                .regs = gc0310_VGA_30fps,
 431        },
 432};
 433#define N_RES_STILL (ARRAY_SIZE(gc0310_res_still))
 434
 435struct gc0310_resolution gc0310_res_video[] = {
 436        {
 437                .desc = "gc0310_VGA_30fps",
 438                .width = 656, // 648,
 439                .height = 496, // 488,
 440                .fps = 30,
 441                //.pix_clk_freq = 73,
 442                .used = 0,
 443#if 0
 444                .pixels_per_line = 0x0314,
 445                .lines_per_frame = 0x0213,
 446#endif
 447                .bin_factor_x = 1,
 448                .bin_factor_y = 1,
 449                .bin_mode = 0,
 450                .skip_frames = 2,
 451                .regs = gc0310_VGA_30fps,
 452        },
 453};
 454#define N_RES_VIDEO (ARRAY_SIZE(gc0310_res_video))
 455
 456static struct gc0310_resolution *gc0310_res = gc0310_res_preview;
 457static unsigned long N_RES = N_RES_PREVIEW;
 458#endif
 459
 460