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17#include <linux/kernel.h>
18#include <linux/module.h>
19#include <linux/atomic.h>
20#include <linux/clk.h>
21#include <linux/completion.h>
22#include <linux/delay.h>
23#include <linux/err.h>
24#include <linux/gpio.h>
25#include <linux/interrupt.h>
26#include <linux/io.h>
27#include <linux/irq.h>
28#include <linux/of.h>
29#include <linux/of_gpio.h>
30#include <linux/list.h>
31#include <linux/mfd/core.h>
32#include <linux/mutex.h>
33#include <linux/notifier.h>
34#include <linux/slab.h>
35#include <linux/spinlock.h>
36#include <linux/workqueue.h>
37
38#include "nvec.h"
39
40#define I2C_CNFG 0x00
41#define I2C_CNFG_PACKET_MODE_EN BIT(10)
42#define I2C_CNFG_NEW_MASTER_SFM BIT(11)
43#define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
44
45#define I2C_SL_CNFG 0x20
46#define I2C_SL_NEWSL BIT(2)
47#define I2C_SL_NACK BIT(1)
48#define I2C_SL_RESP BIT(0)
49#define I2C_SL_IRQ BIT(3)
50#define END_TRANS BIT(4)
51#define RCVD BIT(2)
52#define RNW BIT(1)
53
54#define I2C_SL_RCVD 0x24
55#define I2C_SL_STATUS 0x28
56#define I2C_SL_ADDR1 0x2c
57#define I2C_SL_ADDR2 0x30
58#define I2C_SL_DELAY_COUNT 0x3c
59
60
61
62
63
64
65enum nvec_msg_category {
66 NVEC_MSG_RX,
67 NVEC_MSG_TX,
68};
69
70enum nvec_sleep_subcmds {
71 GLOBAL_EVENTS,
72 AP_PWR_DOWN,
73 AP_SUSPEND,
74};
75
76#define CNF_EVENT_REPORTING 0x01
77#define GET_FIRMWARE_VERSION 0x15
78#define LID_SWITCH BIT(1)
79#define PWR_BUTTON BIT(15)
80
81static struct nvec_chip *nvec_power_handle;
82
83static const struct mfd_cell nvec_devices[] = {
84 {
85 .name = "nvec-kbd",
86 },
87 {
88 .name = "nvec-mouse",
89 },
90 {
91 .name = "nvec-power",
92 .id = 0,
93 },
94 {
95 .name = "nvec-power",
96 .id = 1,
97 },
98 {
99 .name = "nvec-paz00",
100 },
101};
102
103
104
105
106
107
108
109
110
111
112int nvec_register_notifier(struct nvec_chip *nvec, struct notifier_block *nb,
113 unsigned int events)
114{
115 return atomic_notifier_chain_register(&nvec->notifier_list, nb);
116}
117EXPORT_SYMBOL_GPL(nvec_register_notifier);
118
119
120
121
122
123
124
125
126
127int nvec_unregister_notifier(struct nvec_chip *nvec, struct notifier_block *nb)
128{
129 return atomic_notifier_chain_unregister(&nvec->notifier_list, nb);
130}
131EXPORT_SYMBOL_GPL(nvec_unregister_notifier);
132
133
134
135
136
137
138
139static int nvec_status_notifier(struct notifier_block *nb,
140 unsigned long event_type, void *data)
141{
142 struct nvec_chip *nvec = container_of(nb, struct nvec_chip,
143 nvec_status_notifier);
144 unsigned char *msg = data;
145
146 if (event_type != NVEC_CNTL)
147 return NOTIFY_DONE;
148
149 dev_warn(nvec->dev, "unhandled msg type %ld\n", event_type);
150 print_hex_dump(KERN_WARNING, "payload: ", DUMP_PREFIX_NONE, 16, 1,
151 msg, msg[1] + 2, true);
152
153 return NOTIFY_OK;
154}
155
156
157
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159
160
161
162
163
164
165
166
167
168
169
170static struct nvec_msg *nvec_msg_alloc(struct nvec_chip *nvec,
171 enum nvec_msg_category category)
172{
173 int i = (category == NVEC_MSG_TX) ? (NVEC_POOL_SIZE / 4) : 0;
174
175 for (; i < NVEC_POOL_SIZE; i++) {
176 if (atomic_xchg(&nvec->msg_pool[i].used, 1) == 0) {
177 dev_vdbg(nvec->dev, "INFO: Allocate %i\n", i);
178 return &nvec->msg_pool[i];
179 }
180 }
181
182 dev_err(nvec->dev, "could not allocate %s buffer\n",
183 (category == NVEC_MSG_TX) ? "TX" : "RX");
184
185 return NULL;
186}
187
188
189
190
191
192
193
194
195void nvec_msg_free(struct nvec_chip *nvec, struct nvec_msg *msg)
196{
197 if (msg != &nvec->tx_scratch)
198 dev_vdbg(nvec->dev, "INFO: Free %ti\n", msg - nvec->msg_pool);
199 atomic_set(&msg->used, 0);
200}
201EXPORT_SYMBOL_GPL(nvec_msg_free);
202
203
204
205
206
207static bool nvec_msg_is_event(struct nvec_msg *msg)
208{
209 return msg->data[0] >> 7;
210}
211
212
213
214
215
216
217
218static size_t nvec_msg_size(struct nvec_msg *msg)
219{
220 bool is_event = nvec_msg_is_event(msg);
221 int event_length = (msg->data[0] & 0x60) >> 5;
222
223
224 if (!is_event || event_length == NVEC_VAR_SIZE)
225 return (msg->pos || msg->size) ? (msg->data[1] + 2) : 0;
226 else if (event_length == NVEC_2BYTES)
227 return 2;
228 else if (event_length == NVEC_3BYTES)
229 return 3;
230 return 0;
231}
232
233
234
235
236
237
238
239
240static void nvec_gpio_set_value(struct nvec_chip *nvec, int value)
241{
242 dev_dbg(nvec->dev, "GPIO changed from %u to %u\n",
243 gpio_get_value(nvec->gpio), value);
244 gpio_set_value(nvec->gpio, value);
245}
246
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249
250
251
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253
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255
256
257
258
259int nvec_write_async(struct nvec_chip *nvec, const unsigned char *data,
260 short size)
261{
262 struct nvec_msg *msg;
263 unsigned long flags;
264
265 msg = nvec_msg_alloc(nvec, NVEC_MSG_TX);
266
267 if (!msg)
268 return -ENOMEM;
269
270 msg->data[0] = size;
271 memcpy(msg->data + 1, data, size);
272 msg->size = size + 1;
273
274 spin_lock_irqsave(&nvec->tx_lock, flags);
275 list_add_tail(&msg->node, &nvec->tx_data);
276 spin_unlock_irqrestore(&nvec->tx_lock, flags);
277
278 schedule_work(&nvec->tx_work);
279
280 return 0;
281}
282EXPORT_SYMBOL(nvec_write_async);
283
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299
300
301int nvec_write_sync(struct nvec_chip *nvec,
302 const unsigned char *data, short size,
303 struct nvec_msg **msg)
304{
305 mutex_lock(&nvec->sync_write_mutex);
306
307 *msg = NULL;
308 nvec->sync_write_pending = (data[1] << 8) + data[0];
309
310 if (nvec_write_async(nvec, data, size) < 0) {
311 mutex_unlock(&nvec->sync_write_mutex);
312 return -ENOMEM;
313 }
314
315 dev_dbg(nvec->dev, "nvec_sync_write: 0x%04x\n",
316 nvec->sync_write_pending);
317 if (!(wait_for_completion_timeout(&nvec->sync_write,
318 msecs_to_jiffies(2000)))) {
319 dev_warn(nvec->dev,
320 "timeout waiting for sync write to complete\n");
321 mutex_unlock(&nvec->sync_write_mutex);
322 return -ETIMEDOUT;
323 }
324
325 dev_dbg(nvec->dev, "nvec_sync_write: pong!\n");
326
327 *msg = nvec->last_sync_msg;
328
329 mutex_unlock(&nvec->sync_write_mutex);
330
331 return 0;
332}
333EXPORT_SYMBOL(nvec_write_sync);
334
335
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338
339
340
341
342static void nvec_toggle_global_events(struct nvec_chip *nvec, bool state)
343{
344 unsigned char global_events[] = { NVEC_SLEEP, GLOBAL_EVENTS, state };
345
346 nvec_write_async(nvec, global_events, 3);
347}
348
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361
362static void nvec_event_mask(char *ev, u32 mask)
363{
364 ev[3] = mask >> 16 & 0xff;
365 ev[4] = mask >> 24 & 0xff;
366 ev[5] = mask >> 0 & 0xff;
367 ev[6] = mask >> 8 & 0xff;
368}
369
370
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373
374
375
376
377
378static void nvec_request_master(struct work_struct *work)
379{
380 struct nvec_chip *nvec = container_of(work, struct nvec_chip, tx_work);
381 unsigned long flags;
382 long err;
383 struct nvec_msg *msg;
384
385 spin_lock_irqsave(&nvec->tx_lock, flags);
386 while (!list_empty(&nvec->tx_data)) {
387 msg = list_first_entry(&nvec->tx_data, struct nvec_msg, node);
388 spin_unlock_irqrestore(&nvec->tx_lock, flags);
389 nvec_gpio_set_value(nvec, 0);
390 err = wait_for_completion_interruptible_timeout(
391 &nvec->ec_transfer, msecs_to_jiffies(5000));
392
393 if (err == 0) {
394 dev_warn(nvec->dev, "timeout waiting for ec transfer\n");
395 nvec_gpio_set_value(nvec, 1);
396 msg->pos = 0;
397 }
398
399 spin_lock_irqsave(&nvec->tx_lock, flags);
400
401 if (err > 0) {
402 list_del_init(&msg->node);
403 nvec_msg_free(nvec, msg);
404 }
405 }
406 spin_unlock_irqrestore(&nvec->tx_lock, flags);
407}
408
409
410
411
412
413
414
415
416
417static int parse_msg(struct nvec_chip *nvec, struct nvec_msg *msg)
418{
419 if ((msg->data[0] & 1 << 7) == 0 && msg->data[3]) {
420 dev_err(nvec->dev, "ec responded %*ph\n", 4, msg->data);
421 return -EINVAL;
422 }
423
424 if ((msg->data[0] >> 7) == 1 && (msg->data[0] & 0x0f) == 5)
425 print_hex_dump(KERN_WARNING, "ec system event ",
426 DUMP_PREFIX_NONE, 16, 1, msg->data,
427 msg->data[1] + 2, true);
428
429 atomic_notifier_call_chain(&nvec->notifier_list, msg->data[0] & 0x8f,
430 msg->data);
431
432 return 0;
433}
434
435
436
437
438
439
440
441
442static void nvec_dispatch(struct work_struct *work)
443{
444 struct nvec_chip *nvec = container_of(work, struct nvec_chip, rx_work);
445 unsigned long flags;
446 struct nvec_msg *msg;
447
448 spin_lock_irqsave(&nvec->rx_lock, flags);
449 while (!list_empty(&nvec->rx_data)) {
450 msg = list_first_entry(&nvec->rx_data, struct nvec_msg, node);
451 list_del_init(&msg->node);
452 spin_unlock_irqrestore(&nvec->rx_lock, flags);
453
454 if (nvec->sync_write_pending ==
455 (msg->data[2] << 8) + msg->data[0]) {
456 dev_dbg(nvec->dev, "sync write completed!\n");
457 nvec->sync_write_pending = 0;
458 nvec->last_sync_msg = msg;
459 complete(&nvec->sync_write);
460 } else {
461 parse_msg(nvec, msg);
462 nvec_msg_free(nvec, msg);
463 }
464 spin_lock_irqsave(&nvec->rx_lock, flags);
465 }
466 spin_unlock_irqrestore(&nvec->rx_lock, flags);
467}
468
469
470
471
472
473
474
475static void nvec_tx_completed(struct nvec_chip *nvec)
476{
477
478 if (nvec->tx->pos != nvec->tx->size) {
479 dev_err(nvec->dev, "premature END_TRANS, resending\n");
480 nvec->tx->pos = 0;
481 nvec_gpio_set_value(nvec, 0);
482 } else {
483 nvec->state = 0;
484 }
485}
486
487
488
489
490
491
492
493static void nvec_rx_completed(struct nvec_chip *nvec)
494{
495 if (nvec->rx->pos != nvec_msg_size(nvec->rx)) {
496 dev_err(nvec->dev, "RX incomplete: Expected %u bytes, got %u\n",
497 (uint)nvec_msg_size(nvec->rx),
498 (uint)nvec->rx->pos);
499
500 nvec_msg_free(nvec, nvec->rx);
501 nvec->state = 0;
502
503
504 if (nvec->rx->data[0] == NVEC_BAT)
505 complete(&nvec->ec_transfer);
506
507 return;
508 }
509
510 spin_lock(&nvec->rx_lock);
511
512
513
514
515
516 list_add_tail(&nvec->rx->node, &nvec->rx_data);
517
518 spin_unlock(&nvec->rx_lock);
519
520 nvec->state = 0;
521
522 if (!nvec_msg_is_event(nvec->rx))
523 complete(&nvec->ec_transfer);
524
525 schedule_work(&nvec->rx_work);
526}
527
528
529
530
531
532
533
534static void nvec_invalid_flags(struct nvec_chip *nvec, unsigned int status,
535 bool reset)
536{
537 dev_err(nvec->dev, "unexpected status flags 0x%02x during state %i\n",
538 status, nvec->state);
539 if (reset)
540 nvec->state = 0;
541}
542
543
544
545
546
547
548
549
550
551static void nvec_tx_set(struct nvec_chip *nvec)
552{
553 spin_lock(&nvec->tx_lock);
554 if (list_empty(&nvec->tx_data)) {
555 dev_err(nvec->dev, "empty tx - sending no-op\n");
556 memcpy(nvec->tx_scratch.data, "\x02\x07\x02", 3);
557 nvec->tx_scratch.size = 3;
558 nvec->tx_scratch.pos = 0;
559 nvec->tx = &nvec->tx_scratch;
560 list_add_tail(&nvec->tx->node, &nvec->tx_data);
561 } else {
562 nvec->tx = list_first_entry(&nvec->tx_data, struct nvec_msg,
563 node);
564 nvec->tx->pos = 0;
565 }
566 spin_unlock(&nvec->tx_lock);
567
568 dev_dbg(nvec->dev, "Sending message of length %u, command 0x%x\n",
569 (uint)nvec->tx->size, nvec->tx->data[1]);
570}
571
572
573
574
575
576
577
578
579
580
581static irqreturn_t nvec_interrupt(int irq, void *dev)
582{
583 unsigned long status;
584 unsigned int received = 0;
585 unsigned char to_send = 0xff;
586 const unsigned long irq_mask = I2C_SL_IRQ | END_TRANS | RCVD | RNW;
587 struct nvec_chip *nvec = dev;
588 unsigned int state = nvec->state;
589
590 status = readl(nvec->base + I2C_SL_STATUS);
591
592
593 if ((status & irq_mask) == 0 && (status & ~irq_mask) != 0) {
594 dev_err(nvec->dev, "unexpected irq mask %lx\n", status);
595 return IRQ_HANDLED;
596 }
597 if ((status & I2C_SL_IRQ) == 0) {
598 dev_err(nvec->dev, "Spurious IRQ\n");
599 return IRQ_HANDLED;
600 }
601
602
603 if ((status & RNW) == 0) {
604 received = readl(nvec->base + I2C_SL_RCVD);
605 if (status & RCVD)
606 writel(0, nvec->base + I2C_SL_RCVD);
607 }
608
609 if (status == (I2C_SL_IRQ | RCVD))
610 nvec->state = 0;
611
612 switch (nvec->state) {
613 case 0:
614 if (status != (I2C_SL_IRQ | RCVD))
615 nvec_invalid_flags(nvec, status, false);
616 break;
617 case 1:
618 if (status != I2C_SL_IRQ) {
619 nvec_invalid_flags(nvec, status, true);
620 } else {
621 nvec->rx = nvec_msg_alloc(nvec, NVEC_MSG_RX);
622
623 if (unlikely(!nvec->rx)) {
624 nvec->state = 0;
625 break;
626 }
627 nvec->rx->data[0] = received;
628 nvec->rx->pos = 1;
629 nvec->state = 2;
630 }
631 break;
632 case 2:
633 if (status == (I2C_SL_IRQ | RNW | RCVD)) {
634 udelay(33);
635 if (nvec->rx->data[0] != 0x01) {
636 dev_err(nvec->dev,
637 "Read without prior read command\n");
638 nvec->state = 0;
639 break;
640 }
641 nvec_msg_free(nvec, nvec->rx);
642 nvec->state = 3;
643 nvec_tx_set(nvec);
644 to_send = nvec->tx->data[0];
645 nvec->tx->pos = 1;
646 } else if (status == (I2C_SL_IRQ)) {
647 nvec->rx->data[1] = received;
648 nvec->rx->pos = 2;
649 nvec->state = 4;
650 } else {
651 nvec_invalid_flags(nvec, status, true);
652 }
653 break;
654 case 3:
655 if (status & END_TRANS) {
656 nvec_tx_completed(nvec);
657 } else if ((status & RNW) == 0 || (status & RCVD)) {
658 nvec_invalid_flags(nvec, status, true);
659 } else if (nvec->tx && nvec->tx->pos < nvec->tx->size) {
660 to_send = nvec->tx->data[nvec->tx->pos++];
661 } else {
662 dev_err(nvec->dev,
663 "tx buffer underflow on %p (%u > %u)\n",
664 nvec->tx,
665 (uint)(nvec->tx ? nvec->tx->pos : 0),
666 (uint)(nvec->tx ? nvec->tx->size : 0));
667 nvec->state = 0;
668 }
669 break;
670 case 4:
671 if ((status & (END_TRANS | RNW)) == END_TRANS)
672 nvec_rx_completed(nvec);
673 else if (status & (RNW | RCVD))
674 nvec_invalid_flags(nvec, status, true);
675 else if (nvec->rx && nvec->rx->pos < NVEC_MSG_SIZE)
676 nvec->rx->data[nvec->rx->pos++] = received;
677 else
678 dev_err(nvec->dev,
679 "RX buffer overflow on %p: Trying to write byte %u of %u\n",
680 nvec->rx, nvec->rx ? nvec->rx->pos : 0,
681 NVEC_MSG_SIZE);
682 break;
683 default:
684 nvec->state = 0;
685 }
686
687
688 if ((status & (RCVD | RNW)) == RCVD) {
689 if (received != nvec->i2c_addr)
690 dev_err(nvec->dev,
691 "received address 0x%02x, expected 0x%02x\n",
692 received, nvec->i2c_addr);
693 nvec->state = 1;
694 }
695
696
697 if ((status & (RNW | END_TRANS)) == RNW)
698 writel(to_send, nvec->base + I2C_SL_RCVD);
699
700
701 if (status == (I2C_SL_IRQ | RNW | RCVD))
702 nvec_gpio_set_value(nvec, 1);
703
704 dev_dbg(nvec->dev,
705 "Handled: %s 0x%02x, %s 0x%02x in state %u [%s%s%s]\n",
706 (status & RNW) == 0 ? "received" : "R=",
707 received,
708 (status & (RNW | END_TRANS)) ? "sent" : "S=",
709 to_send,
710 state,
711 status & END_TRANS ? " END_TRANS" : "",
712 status & RCVD ? " RCVD" : "",
713 status & RNW ? " RNW" : "");
714
715
716
717
718
719
720
721 udelay(100);
722
723 return IRQ_HANDLED;
724}
725
726static void tegra_init_i2c_slave(struct nvec_chip *nvec)
727{
728 u32 val;
729
730 clk_prepare_enable(nvec->i2c_clk);
731
732 reset_control_assert(nvec->rst);
733 udelay(2);
734 reset_control_deassert(nvec->rst);
735
736 val = I2C_CNFG_NEW_MASTER_SFM | I2C_CNFG_PACKET_MODE_EN |
737 (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
738 writel(val, nvec->base + I2C_CNFG);
739
740 clk_set_rate(nvec->i2c_clk, 8 * 80000);
741
742 writel(I2C_SL_NEWSL, nvec->base + I2C_SL_CNFG);
743 writel(0x1E, nvec->base + I2C_SL_DELAY_COUNT);
744
745 writel(nvec->i2c_addr >> 1, nvec->base + I2C_SL_ADDR1);
746 writel(0, nvec->base + I2C_SL_ADDR2);
747
748 enable_irq(nvec->irq);
749}
750
751#ifdef CONFIG_PM_SLEEP
752static void nvec_disable_i2c_slave(struct nvec_chip *nvec)
753{
754 disable_irq(nvec->irq);
755 writel(I2C_SL_NEWSL | I2C_SL_NACK, nvec->base + I2C_SL_CNFG);
756 clk_disable_unprepare(nvec->i2c_clk);
757}
758#endif
759
760static void nvec_power_off(void)
761{
762 char ap_pwr_down[] = { NVEC_SLEEP, AP_PWR_DOWN };
763
764 nvec_toggle_global_events(nvec_power_handle, false);
765 nvec_write_async(nvec_power_handle, ap_pwr_down, 2);
766}
767
768
769
770
771static int nvec_i2c_parse_dt_pdata(struct nvec_chip *nvec)
772{
773 nvec->gpio = of_get_named_gpio(nvec->dev->of_node, "request-gpios", 0);
774
775 if (nvec->gpio < 0) {
776 dev_err(nvec->dev, "no gpio specified");
777 return -ENODEV;
778 }
779
780 if (of_property_read_u32(nvec->dev->of_node, "slave-addr",
781 &nvec->i2c_addr)) {
782 dev_err(nvec->dev, "no i2c address specified");
783 return -ENODEV;
784 }
785
786 return 0;
787}
788
789static int tegra_nvec_probe(struct platform_device *pdev)
790{
791 int err, ret;
792 struct clk *i2c_clk;
793 struct nvec_chip *nvec;
794 struct nvec_msg *msg;
795 struct resource *res;
796 void __iomem *base;
797 char get_firmware_version[] = { NVEC_CNTL, GET_FIRMWARE_VERSION },
798 unmute_speakers[] = { NVEC_OEM0, 0x10, 0x59, 0x95 },
799 enable_event[7] = { NVEC_SYS, CNF_EVENT_REPORTING, true };
800
801 if (!pdev->dev.of_node) {
802 dev_err(&pdev->dev, "must be instantiated using device tree\n");
803 return -ENODEV;
804 }
805
806 nvec = devm_kzalloc(&pdev->dev, sizeof(struct nvec_chip), GFP_KERNEL);
807 if (!nvec)
808 return -ENOMEM;
809
810 platform_set_drvdata(pdev, nvec);
811 nvec->dev = &pdev->dev;
812
813 err = nvec_i2c_parse_dt_pdata(nvec);
814 if (err < 0)
815 return err;
816
817 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
818 base = devm_ioremap_resource(&pdev->dev, res);
819 if (IS_ERR(base))
820 return PTR_ERR(base);
821
822 nvec->irq = platform_get_irq(pdev, 0);
823 if (nvec->irq < 0) {
824 dev_err(&pdev->dev, "no irq resource?\n");
825 return -ENODEV;
826 }
827
828 i2c_clk = devm_clk_get(&pdev->dev, "div-clk");
829 if (IS_ERR(i2c_clk)) {
830 dev_err(nvec->dev, "failed to get controller clock\n");
831 return -ENODEV;
832 }
833
834 nvec->rst = devm_reset_control_get(&pdev->dev, "i2c");
835 if (IS_ERR(nvec->rst)) {
836 dev_err(nvec->dev, "failed to get controller reset\n");
837 return PTR_ERR(nvec->rst);
838 }
839
840 nvec->base = base;
841 nvec->i2c_clk = i2c_clk;
842 nvec->rx = &nvec->msg_pool[0];
843
844 ATOMIC_INIT_NOTIFIER_HEAD(&nvec->notifier_list);
845
846 init_completion(&nvec->sync_write);
847 init_completion(&nvec->ec_transfer);
848 mutex_init(&nvec->sync_write_mutex);
849 spin_lock_init(&nvec->tx_lock);
850 spin_lock_init(&nvec->rx_lock);
851 INIT_LIST_HEAD(&nvec->rx_data);
852 INIT_LIST_HEAD(&nvec->tx_data);
853 INIT_WORK(&nvec->rx_work, nvec_dispatch);
854 INIT_WORK(&nvec->tx_work, nvec_request_master);
855
856 err = devm_gpio_request_one(&pdev->dev, nvec->gpio, GPIOF_OUT_INIT_HIGH,
857 "nvec gpio");
858 if (err < 0) {
859 dev_err(nvec->dev, "couldn't request gpio\n");
860 return -ENODEV;
861 }
862
863 err = devm_request_irq(&pdev->dev, nvec->irq, nvec_interrupt, 0,
864 "nvec", nvec);
865 if (err) {
866 dev_err(nvec->dev, "couldn't request irq\n");
867 return -ENODEV;
868 }
869 disable_irq(nvec->irq);
870
871 tegra_init_i2c_slave(nvec);
872
873
874 nvec_toggle_global_events(nvec, true);
875
876 nvec->nvec_status_notifier.notifier_call = nvec_status_notifier;
877 nvec_register_notifier(nvec, &nvec->nvec_status_notifier, 0);
878
879 nvec_power_handle = nvec;
880 pm_power_off = nvec_power_off;
881
882
883 err = nvec_write_sync(nvec, get_firmware_version, 2, &msg);
884
885 if (!err) {
886 dev_warn(nvec->dev,
887 "ec firmware version %02x.%02x.%02x / %02x\n",
888 msg->data[4], msg->data[5],
889 msg->data[6], msg->data[7]);
890
891 nvec_msg_free(nvec, msg);
892 }
893
894 ret = mfd_add_devices(nvec->dev, 0, nvec_devices,
895 ARRAY_SIZE(nvec_devices), NULL, 0, NULL);
896 if (ret)
897 dev_err(nvec->dev, "error adding subdevices\n");
898
899
900 nvec_write_async(nvec, unmute_speakers, 4);
901
902
903 nvec_event_mask(enable_event, LID_SWITCH);
904 nvec_write_async(nvec, enable_event, 7);
905
906
907 nvec_event_mask(enable_event, PWR_BUTTON);
908 nvec_write_async(nvec, enable_event, 7);
909
910 return 0;
911}
912
913static int tegra_nvec_remove(struct platform_device *pdev)
914{
915 struct nvec_chip *nvec = platform_get_drvdata(pdev);
916
917 nvec_toggle_global_events(nvec, false);
918 mfd_remove_devices(nvec->dev);
919 nvec_unregister_notifier(nvec, &nvec->nvec_status_notifier);
920 cancel_work_sync(&nvec->rx_work);
921 cancel_work_sync(&nvec->tx_work);
922
923 pm_power_off = NULL;
924
925 return 0;
926}
927
928#ifdef CONFIG_PM_SLEEP
929static int nvec_suspend(struct device *dev)
930{
931 int err;
932 struct platform_device *pdev = to_platform_device(dev);
933 struct nvec_chip *nvec = platform_get_drvdata(pdev);
934 struct nvec_msg *msg;
935 char ap_suspend[] = { NVEC_SLEEP, AP_SUSPEND };
936
937 dev_dbg(nvec->dev, "suspending\n");
938
939
940 nvec_toggle_global_events(nvec, false);
941
942 err = nvec_write_sync(nvec, ap_suspend, sizeof(ap_suspend), &msg);
943 if (!err)
944 nvec_msg_free(nvec, msg);
945
946 nvec_disable_i2c_slave(nvec);
947
948 return 0;
949}
950
951static int nvec_resume(struct device *dev)
952{
953 struct platform_device *pdev = to_platform_device(dev);
954 struct nvec_chip *nvec = platform_get_drvdata(pdev);
955
956 dev_dbg(nvec->dev, "resuming\n");
957 tegra_init_i2c_slave(nvec);
958 nvec_toggle_global_events(nvec, true);
959
960 return 0;
961}
962#endif
963
964static SIMPLE_DEV_PM_OPS(nvec_pm_ops, nvec_suspend, nvec_resume);
965
966
967static const struct of_device_id nvidia_nvec_of_match[] = {
968 { .compatible = "nvidia,nvec", },
969 {},
970};
971MODULE_DEVICE_TABLE(of, nvidia_nvec_of_match);
972
973static struct platform_driver nvec_device_driver = {
974 .probe = tegra_nvec_probe,
975 .remove = tegra_nvec_remove,
976 .driver = {
977 .name = "nvec",
978 .pm = &nvec_pm_ops,
979 .of_match_table = nvidia_nvec_of_match,
980 }
981};
982
983module_platform_driver(nvec_device_driver);
984
985MODULE_ALIAS("platform:nvec");
986MODULE_DESCRIPTION("NVIDIA compliant embedded controller interface");
987MODULE_AUTHOR("Marc Dietrich <marvin24@gmx.de>");
988MODULE_LICENSE("GPL");
989