1/****************************************************************************** 2 * 3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 ******************************************************************************/ 15#ifndef __INC_HAL8188EPHYCFG_H__ 16#define __INC_HAL8188EPHYCFG_H__ 17 18 19/*--------------------------Define Parameters-------------------------------*/ 20#define LOOP_LIMIT 5 21#define MAX_STALL_TIME 50 /* us */ 22#define AntennaDiversityValue 0x80 23#define MAX_TXPWR_IDX_NMODE_92S 63 24#define Reset_Cnt_Limit 3 25 26#define IQK_MAC_REG_NUM 4 27#define IQK_ADDA_REG_NUM 16 28#define IQK_BB_REG_NUM 9 29#define HP_THERMAL_NUM 8 30 31#define MAX_AGGR_NUM 0x07 32 33 34/*--------------------------Define Parameters-------------------------------*/ 35 36 37/*------------------------------Define structure----------------------------*/ 38enum sw_chnl_cmd_id { 39 CmdID_End, 40 CmdID_SetTxPowerLevel, 41 CmdID_BBRegWrite10, 42 CmdID_WritePortUlong, 43 CmdID_WritePortUshort, 44 CmdID_WritePortUchar, 45 CmdID_RF_WriteReg, 46}; 47 48/* 1. Switch channel related */ 49struct sw_chnl_cmd { 50 enum sw_chnl_cmd_id CmdID; 51 u32 Para1; 52 u32 Para2; 53 u32 msDelay; 54}; 55 56enum hw90_block { 57 HW90_BLOCK_MAC = 0, 58 HW90_BLOCK_PHY0 = 1, 59 HW90_BLOCK_PHY1 = 2, 60 HW90_BLOCK_RF = 3, 61 HW90_BLOCK_MAXIMUM = 4, /* Never use this */ 62}; 63 64enum rf_radio_path { 65 RF_PATH_A = 0, /* Radio Path A */ 66 RF_PATH_B = 1, /* Radio Path B */ 67}; 68 69#define MAX_PG_GROUP 13 70 71#define RF_PATH_MAX 2 72#define MAX_RF_PATH RF_PATH_MAX 73#define MAX_TX_COUNT 4 /* path numbers */ 74 75#define CHANNEL_MAX_NUMBER 14 /* 14 is the max chnl number */ 76#define MAX_CHNL_GROUP_24G 6 /* ch1~2, ch3~5, ch6~8, 77 *ch9~11, ch12~13, CH 14 78 * total three groups */ 79#define CHANNEL_GROUP_MAX_88E 6 80 81enum wireless_mode { 82 WIRELESS_MODE_UNKNOWN = 0x00, 83 WIRELESS_MODE_A = BIT(2), 84 WIRELESS_MODE_B = BIT(0), 85 WIRELESS_MODE_G = BIT(1), 86 WIRELESS_MODE_AUTO = BIT(5), 87 WIRELESS_MODE_N_24G = BIT(3), 88 WIRELESS_MODE_N_5G = BIT(4), 89 WIRELESS_MODE_AC = BIT(6) 90}; 91 92enum phy_rate_tx_offset_area { 93 RA_OFFSET_LEGACY_OFDM1, 94 RA_OFFSET_LEGACY_OFDM2, 95 RA_OFFSET_HT_OFDM1, 96 RA_OFFSET_HT_OFDM2, 97 RA_OFFSET_HT_OFDM3, 98 RA_OFFSET_HT_OFDM4, 99 RA_OFFSET_HT_CCK, 100}; 101 102struct bb_reg_def { 103 u32 rfintfs; /* set software control: */ 104 /* 0x870~0x877[8 bytes] */ 105 u32 rfintfi; /* readback data: */ 106 /* 0x8e0~0x8e7[8 bytes] */ 107 u32 rfintfo; /* output data: */ 108 /* 0x860~0x86f [16 bytes] */ 109 u32 rfintfe; /* output enable: */ 110 /* 0x860~0x86f [16 bytes] */ 111 u32 rf3wireOffset; /* LSSI data: */ 112 /* 0x840~0x84f [16 bytes] */ 113 u32 rfLSSI_Select; /* BB Band Select: */ 114 /* 0x878~0x87f [8 bytes] */ 115 u32 rfTxGainStage; /* Tx gain stage: */ 116 /* 0x80c~0x80f [4 bytes] */ 117 u32 rfHSSIPara1; /* wire parameter control1 : */ 118 /* 0x820~0x823,0x828~0x82b, 119 * 0x830~0x833, 0x838~0x83b [16 bytes] */ 120 u32 rfHSSIPara2; /* wire parameter control2 : */ 121 /* 0x824~0x827,0x82c~0x82f, 0x834~0x837, 122 * 0x83c~0x83f [16 bytes] */ 123 u32 rfSwitchControl; /* Tx Rx antenna control : */ 124 /* 0x858~0x85f [16 bytes] */ 125 u32 rfAGCControl1; /* AGC parameter control1 : */ 126 /* 0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 127 * 0xc68~0xc6b [16 bytes] */ 128 u32 rfAGCControl2; /* AGC parameter control2 : */ 129 /* 0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 130 * 0xc6c~0xc6f [16 bytes] */ 131 u32 rfRxIQImbalance; /* OFDM Rx IQ imbalance matrix : */ 132 /* 0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 133 * 0xc2c~0xc2f [16 bytes] */ 134 u32 rfRxAFE; /* Rx IQ DC ofset and Rx digital filter, 135 * Rx DC notch filter : */ 136 /* 0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 137 * 0xc28~0xc2b [16 bytes] */ 138 u32 rfTxIQImbalance; /* OFDM Tx IQ imbalance matrix */ 139 /* 0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 140 * 0xc98~0xc9b [16 bytes] */ 141 u32 rfTxAFE; /* Tx IQ DC Offset and Tx DFIR type */ 142 /* 0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 143 * 0xc9c~0xc9f [16 bytes] */ 144 u32 rfLSSIReadBack; /* LSSI RF readback data SI mode */ 145 /* 0x8a0~0x8af [16 bytes] */ 146 u32 rfLSSIReadBackPi; /* LSSI RF readback data PI mode 0x8b8-8bc for 147 * Path A and B */ 148}; 149 150/*------------------------------Define structure----------------------------*/ 151 152 153/*------------------------Export global variable----------------------------*/ 154/*------------------------Export global variable----------------------------*/ 155 156 157/*------------------------Export Marco Definition---------------------------*/ 158/*------------------------Export Marco Definition---------------------------*/ 159 160 161/*--------------------------Exported Function prototype---------------------*/ 162/* */ 163/* BB and RF register read/write */ 164/* */ 165 166/* Read initi reg value for tx power setting. */ 167void rtl8192c_PHY_GetHWRegOriginalValue(struct adapter *adapter); 168 169/* BB TX Power R/W */ 170void PHY_GetTxPowerLevel8188E(struct adapter *adapter, u32 *powerlevel); 171 172void PHY_ScanOperationBackup8188E(struct adapter *Adapter, u8 Operation); 173 174/* Call after initialization */ 175void ChkFwCmdIoDone(struct adapter *adapter); 176 177/* BB/MAC/RF other monitor API */ 178void PHY_SetRFPathSwitch_8188E(struct adapter *adapter, bool main); 179 180void PHY_SwitchEphyParameter(struct adapter *adapter); 181 182void PHY_EnableHostClkReq(struct adapter *adapter); 183 184bool SetAntennaConfig92C(struct adapter *adapter, u8 defaultant); 185 186/*--------------------------Exported Function prototype---------------------*/ 187 188#define PHY_SetMacReg PHY_SetBBReg 189 190#define SIC_HW_SUPPORT 0 191 192#define SIC_MAX_POLL_CNT 5 193 194#define SIC_CMD_READY 0 195#define SIC_CMD_WRITE 1 196#define SIC_CMD_READ 2 197 198#define SIC_CMD_REG 0x1EB /* 1byte */ 199#define SIC_ADDR_REG 0x1E8 /* 1b9~1ba, 2 bytes */ 200#define SIC_DATA_REG 0x1EC /* 1bc~1bf */ 201 202#endif /* __INC_HAL8192CPHYCFG_H */ 203