LXR linux/drivers/staging/rtl8188eu/include/rtw

   1/******************************************************************************
   2 *
   3 * Copyright(c) 2007 - 2012 Realtek Corporation. All rights reserved.
   4 *
   5 * This program is free software; you can redistribute it and/or modify it
   6 * under the terms of version 2 of the GNU General Public License as
   7 * published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful, but WITHOUT
  10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12 * more details.
  13 *
  14 ******************************************************************************/
  15#ifndef __RTW_PWRCTRL_H_
  16#define __RTW_PWRCTRL_H_
  17
  18#include <osdep_service.h>
  19#include <drv_types.h>
  20
  21#define FW_PWR0         0
  22#define FW_PWR1         1
  23#define FW_PWR2         2
  24#define FW_PWR3         3
  25#define HW_PWR0         7
  26#define HW_PWR1         6
  27#define HW_PWR2         2
  28#define HW_PWR3         0
  29#define HW_PWR4         8
  30
  31#define FW_PWRMSK       0x7
  32
  33#define XMIT_ALIVE      BIT(0)
  34#define RECV_ALIVE      BIT(1)
  35#define CMD_ALIVE       BIT(2)
  36#define EVT_ALIVE       BIT(3)
  37
  38enum power_mgnt {
  39        PS_MODE_ACTIVE = 0,
  40        PS_MODE_MIN,
  41        PS_MODE_MAX,
  42        PS_MODE_DTIM,
  43        PS_MODE_VOIP,
  44        PS_MODE_UAPSD_WMM,
  45        PS_MODE_UAPSD,
  46        PS_MODE_IBSS,
  47        PS_MODE_WWLAN,
  48        PM_Radio_Off,
  49        PM_Card_Disable,
  50        PS_MODE_NUM
  51};
  52
  53/*
  54        BIT[2:0] = HW state
  55        BIT[3] = Protocol PS state,   0: register active state,
  56                                      1: register sleep state
  57        BIT[4] = sub-state
  58*/
  59
  60#define PS_DPS                  BIT(0)
  61#define PS_LCLK                 (PS_DPS)
  62#define PS_RF_OFF               BIT(1)
  63#define PS_ALL_ON               BIT(2)
  64#define PS_ST_ACTIVE            BIT(3)
  65
  66#define PS_ISR_ENABLE           BIT(4)
  67#define PS_IMR_ENABLE           BIT(5)
  68#define PS_ACK                  BIT(6)
  69#define PS_TOGGLE               BIT(7)
  70
  71#define PS_STATE_MASK           (0x0F)
  72#define PS_STATE_HW_MASK        (0x07)
  73#define PS_SEQ_MASK             (0xc0)
  74
  75#define PS_STATE(x)             (PS_STATE_MASK & (x))
  76#define PS_STATE_HW(x)          (PS_STATE_HW_MASK & (x))
  77#define PS_SEQ(x)               (PS_SEQ_MASK & (x))
  78
  79#define PS_STATE_S0             (PS_DPS)
  80#define PS_STATE_S1             (PS_LCLK)
  81#define PS_STATE_S2             (PS_RF_OFF)
  82#define PS_STATE_S3             (PS_ALL_ON)
  83#define PS_STATE_S4             ((PS_ST_ACTIVE) | (PS_ALL_ON))
  84
  85#define PS_IS_RF_ON(x)  ((x) & (PS_ALL_ON))
  86#define PS_IS_ACTIVE(x) ((x) & (PS_ST_ACTIVE))
  87#define CLR_PS_STATE(x) ((x) = ((x) & (0xF0)))
  88
  89struct reportpwrstate_parm {
  90        unsigned char mode;
  91        unsigned char state; /* the CPWM value */
  92        unsigned short rsvd;
  93};
  94
  95#define LPS_DELAY_TIME  1*HZ /*  1 sec */
  96
  97#define EXE_PWR_NONE    0x01
  98#define EXE_PWR_IPS             0x02
  99#define EXE_PWR_LPS             0x04
 100
 101/*  RF state. */
 102enum rt_rf_power_state {
 103        rf_on,          /*  RF is on after RFSleep or RFOff */
 104        rf_sleep,       /*  802.11 Power Save mode */
 105        rf_off,         /*  HW/SW Radio OFF or Inactive Power Save */
 106        /* Add the new RF state above this line===== */
 107        rf_max
 108};
 109
 110/*  RF Off Level for IPS or HW/SW radio off */
 111#define RT_RF_OFF_LEVL_ASPM             BIT(0)  /* PCI ASPM */
 112#define RT_RF_OFF_LEVL_CLK_REQ          BIT(1)  /* PCI clock request */
 113#define RT_RF_OFF_LEVL_PCI_D3           BIT(2)  /* PCI D3 mode */
 114#define RT_RF_OFF_LEVL_HALT_NIC         BIT(3)  /* NIC halt, re-init hw param*/
 115#define RT_RF_OFF_LEVL_FREE_FW          BIT(4)  /* FW free, re-download the FW*/
 116#define RT_RF_OFF_LEVL_FW_32K           BIT(5)  /* FW in 32k */
 117#define RT_RF_PS_LEVEL_ALWAYS_ASPM      BIT(6)  /* Always enable ASPM and Clock
 118                                                 * Req in initialization. */
 119#define RT_RF_LPS_DISALBE_2R            BIT(30) /* When LPS is on, disable 2R
 120                                                 * if no packet is RX or TX. */
 121#define RT_RF_LPS_LEVEL_ASPM            BIT(31) /* LPS with ASPM */
 122
 123#define RT_IN_PS_LEVEL(ppsc, _PS_FLAG)                          \
 124        ((ppsc->cur_ps_level & _PS_FLAG) ? true : false)
 125#define RT_CLEAR_PS_LEVEL(ppsc, _PS_FLAG)                       \
 126        (ppsc->cur_ps_level &= (~(_PS_FLAG)))
 127#define RT_SET_PS_LEVEL(ppsc, _PS_FLAG)                         \
 128        (ppsc->cur_ps_level |= _PS_FLAG)
 129
 130enum _PS_BBRegBackup_ {
 131        PSBBREG_RF0 = 0,
 132        PSBBREG_RF1,
 133        PSBBREG_RF2,
 134        PSBBREG_AFE0,
 135        PSBBREG_TOTALCNT
 136};
 137
 138enum { /*  for ips_mode */
 139        IPS_NONE = 0,
 140        IPS_NORMAL,
 141        IPS_LEVEL_2,
 142};
 143
 144struct pwrctrl_priv {
 145        struct mutex mutex_lock;
 146        volatile u8 rpwm; /*  requested power state for fw */
 147        volatile u8 cpwm; /*  fw current power state. updated when
 148                           * 1. read from HCPWM 2. driver lowers power level */
 149        volatile u8 tog; /*  toggling */
 150        volatile u8 cpwm_tog; /*  toggling */
 151
 152        u8      pwr_mode;
 153        u8      smart_ps;
 154        u8      bcn_ant_mode;
 155
 156        u32     alives;
 157        struct work_struct cpwm_event;
 158        u8      bpower_saving;
 159
 160        u8      b_hw_radio_off;
 161        u8      reg_rfoff;
 162        u8      reg_pdnmode; /* powerdown mode */
 163        u32     rfoff_reason;
 164
 165        /* RF OFF Level */
 166        u32     cur_ps_level;
 167        u32     reg_rfps_level;
 168        uint    ips_enter_cnts;
 169        uint    ips_leave_cnts;
 170
 171        u8      ips_mode;
 172        u8      ips_mode_req;   /*  used to accept the mode setting request,
 173                                 *  will update to ipsmode later */
 174        uint bips_processing;
 175        unsigned long ips_deny_time; /* will deny IPS when system time less than this */
 176        u8 ps_processing; /* temp used to mark whether in rtw_ps_processor */
 177
 178        u8      bLeisurePs;
 179        u8      LpsIdleCount;
 180        u8      power_mgnt;
 181        u8      bFwCurrentInPSMode;
 182        u32     DelayLPSLastTimeStamp;
 183        u8      btcoex_rfon;
 184        s32             pnp_current_pwr_state;
 185        u8              pnp_bstop_trx;
 186
 187        u8              bInternalAutoSuspend;
 188        u8              bInSuspend;
 189        u8              bSupportRemoteWakeup;
 190        struct timer_list pwr_state_check_timer;
 191        int             pwr_state_check_interval;
 192        u8              pwr_state_check_cnts;
 193
 194        int             ps_flag;
 195
 196        enum rt_rf_power_state  rf_pwrstate;/* cur power state */
 197        enum rt_rf_power_state  change_rfpwrstate;
 198
 199        u8              wepkeymask;
 200        u8              bHWPowerdown;/* if support hw power down */
 201        u8              bHWPwrPindetect;
 202        u8              bkeepfwalive;
 203        u8              brfoffbyhw;
 204        unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT];
 205};
 206
 207#define rtw_get_ips_mode_req(pwrctrlpriv) \
 208        (pwrctrlpriv)->ips_mode_req
 209
 210#define rtw_ips_mode_req(pwrctrlpriv, ips_mode) \
 211        ((pwrctrlpriv)->ips_mode_req = (ips_mode))
 212
 213#define RTW_PWR_STATE_CHK_INTERVAL 2000
 214
 215#define _rtw_set_pwr_state_check_timer(pwrctrlpriv, ms) \
 216        mod_timer(&pwrctrlpriv->pwr_state_check_timer,  \
 217                  jiffies + msecs_to_jiffies(ms))
 218
 219#define rtw_set_pwr_state_check_timer(pwrctrl)                  \
 220        _rtw_set_pwr_state_check_timer((pwrctrl),               \
 221                                       (pwrctrl)->pwr_state_check_interval)
 222
 223void rtw_init_pwrctrl_priv(struct adapter *adapter);
 224
 225void rtw_set_ps_mode(struct adapter *adapter, u8 ps_mode, u8 smart_ps,
 226                     u8 bcn_ant_mode);
 227void rtw_set_rpwm(struct adapter *adapter, u8 val8);
 228void LeaveAllPowerSaveMode(struct adapter *adapter);
 229void ips_enter(struct adapter *padapter);
 230int ips_leave(struct adapter *padapter);
 231
 232void rtw_ps_processor(struct adapter *padapter);
 233
 234enum rt_rf_power_state RfOnOffDetect(struct adapter *iadapter);
 235
 236s32 LPS_RF_ON_check(struct adapter *adapter, u32 delay_ms);
 237void LPS_Enter(struct adapter *adapter);
 238void LPS_Leave(struct adapter *adapter);
 239
 240int _rtw_pwr_wakeup(struct adapter *adapter, u32 ips_defer_ms,
 241                    const char *caller);
 242#define rtw_pwr_wakeup(adapter)                                         \
 243         _rtw_pwr_wakeup(adapter, RTW_PWR_STATE_CHK_INTERVAL, __func__)
 244#define rtw_pwr_wakeup_ex(adapter, ips_deffer_ms)                       \
 245         _rtw_pwr_wakeup(adapter, ips_deffer_ms, __func__)
 246int rtw_pm_set_ips(struct adapter *adapter, u8 mode);
 247int rtw_pm_set_lps(struct adapter *adapter, u8 mode);
 248
 249#endif  /* __RTL871X_PWRCTRL_H_ */
 250