LXR linux/drivers/staging/rtl8192u/r8192U.h

   1/*
   2 * This is part of rtl8187 OpenSource driver.
   3 * Copyright (C) Andrea Merello 2004-2005  <andrea.merello@gmail.com>
   4 * Released under the terms of GPL (General Public Licence)
   5 *
   6 * Parts of this driver are based on the GPL part of the
   7 * official realtek driver
   8 *
   9 * Parts of this driver are based on the rtl8192 driver skeleton
  10 * from Patric Schenke & Andres Salomon
  11 *
  12 * Parts of this driver are based on the Intel Pro Wireless 2100 GPL driver
  13 *
  14 * We want to thank the Authors of those projects and the Ndiswrapper
  15 * project Authors.
  16 */
  17
  18#ifndef R819xU_H
  19#define R819xU_H
  20
  21#include <linux/module.h>
  22#include <linux/kernel.h>
  23#include <linux/ioport.h>
  24#include <linux/sched.h>
  25#include <linux/types.h>
  26#include <linux/slab.h>
  27#include <linux/netdevice.h>
  28#include <linux/usb.h>
  29#include <linux/etherdevice.h>
  30#include <linux/delay.h>
  31#include <linux/rtnetlink.h>
  32#include <linux/wireless.h>
  33#include <linux/timer.h>
  34#include <linux/proc_fs.h>
  35#include <linux/if_arp.h>
  36#include <linux/random.h>
  37#include <linux/io.h>
  38#include "ieee80211/ieee80211.h"
  39
  40#define RTL8192U
  41#define RTL819xU_MODULE_NAME "rtl819xU"
  42/* HW security */
  43#define MAX_KEY_LEN     61
  44#define KEY_BUF_SIZE    5
  45
  46#define Rx_Smooth_Factor                20
  47#define DMESG(x, a...)
  48#define DMESGW(x, a...)
  49#define DMESGE(x, a...)
  50extern u32 rt_global_debug_component;
  51#define RT_TRACE(component, x, args...) \
  52        do {                                                    \
  53                if (rt_global_debug_component & component)      \
  54                        pr_debug("RTL8192U: " x "\n", ##args);  \
  55        } while (0)
  56
  57#define COMP_TRACE              BIT(0)  /* Function call tracing. */
  58#define COMP_DBG                BIT(1)
  59#define COMP_INIT               BIT(2)  /* Driver initialization/halt/reset. */
  60
  61
  62#define COMP_RECV               BIT(3)  /* Receive data path. */
  63#define COMP_SEND               BIT(4)  /* Send data path. */
  64#define COMP_IO                 BIT(5)
  65/* 802.11 Power Save mode or System/Device Power state. */
  66#define COMP_POWER              BIT(6)
  67/* 802.11 link related: join/start BSS, leave BSS. */
  68#define COMP_EPROM              BIT(7)
  69#define COMP_SWBW               BIT(8)  /* Bandwidth switch. */
  70#define COMP_POWER_TRACKING     BIT(9)  /* 8190 TX Power Tracking */
  71#define COMP_TURBO              BIT(10) /* Turbo Mode */
  72#define COMP_QOS                BIT(11)
  73#define COMP_RATE               BIT(12) /* Rate Adaptive mechanism */
  74#define COMP_RM                 BIT(13) /* Radio Measurement */
  75#define COMP_DIG                BIT(14)
  76#define COMP_PHY                BIT(15)
  77#define COMP_CH                 BIT(16) /* Channel setting debug */
  78#define COMP_TXAGC              BIT(17) /* Tx power */
  79#define COMP_HIPWR              BIT(18) /* High Power Mechanism */
  80#define COMP_HALDM              BIT(19) /* HW Dynamic Mechanism */
  81#define COMP_SEC                BIT(20) /* Event handling */
  82#define COMP_LED                BIT(21)
  83#define COMP_RF                 BIT(22)
  84#define COMP_RXDESC             BIT(23) /* Rx desc information for SD3 debug */
  85
  86/* 11n or 8190 specific code */
  87
  88#define COMP_FIRMWARE           BIT(24) /* Firmware downloading */
  89#define COMP_HT                 BIT(25) /* 802.11n HT related information */
  90#define COMP_AMSDU              BIT(26) /* A-MSDU Debugging */
  91#define COMP_SCAN               BIT(27)
  92#define COMP_DOWN               BIT(29) /* rm driver module */
  93#define COMP_RESET              BIT(30) /* Silent reset */
  94#define COMP_ERR                BIT(31) /* Error out, always on */
  95
  96#define RTL819x_DEBUG
  97#ifdef RTL819x_DEBUG
  98#define RTL8192U_ASSERT(expr) \
  99        do {                                                            \
 100                if (!(expr)) {                                          \
 101                        pr_debug("Assertion failed! %s, %s, %s, line = %d\n", \
 102                                 #expr, __FILE__, __func__, __LINE__);  \
 103                }                                                       \
 104        } while (0)
 105/*
 106 * Debug out data buf.
 107 * If you want to print DATA buffer related BA,
 108 * please set ieee80211_debug_level to DATA|BA
 109 */
 110#define RT_DEBUG_DATA(level, data, datalen) \
 111        do {                                                            \
 112                if ((rt_global_debug_component & (level)) == (level)) { \
 113                        int i;                                          \
 114                        u8 *pdata = (u8 *) data;                        \
 115                        pr_debug("RTL8192U: %s()\n", __func__);         \
 116                        for (i = 0; i < (int)(datalen); i++) {          \
 117                                printk("%2x ", pdata[i]);               \
 118                                if ((i+1)%16 == 0)                      \
 119                                        printk("\n");                   \
 120                        }                                               \
 121                        printk("\n");                                   \
 122                }                                                       \
 123        } while (0)
 124#else
 125#define RTL8192U_ASSERT(expr) do {} while (0)
 126#define RT_DEBUG_DATA(level, data, datalen) do {} while (0)
 127#endif /* RTL8169_DEBUG */
 128
 129
 130/* Queue Select Value in TxDesc */
 131#define QSLT_BK                                 0x1
 132#define QSLT_BE                                 0x0
 133#define QSLT_VI                                 0x4
 134#define QSLT_VO                                 0x6
 135#define QSLT_BEACON                             0x10
 136#define QSLT_HIGH                               0x11
 137#define QSLT_MGNT                               0x12
 138#define QSLT_CMD                                0x13
 139
 140#define DESC90_RATE1M                           0x00
 141#define DESC90_RATE2M                           0x01
 142#define DESC90_RATE5_5M                         0x02
 143#define DESC90_RATE11M                          0x03
 144#define DESC90_RATE6M                           0x04
 145#define DESC90_RATE9M                           0x05
 146#define DESC90_RATE12M                          0x06
 147#define DESC90_RATE18M                          0x07
 148#define DESC90_RATE24M                          0x08
 149#define DESC90_RATE36M                          0x09
 150#define DESC90_RATE48M                          0x0a
 151#define DESC90_RATE54M                          0x0b
 152#define DESC90_RATEMCS0                         0x00
 153#define DESC90_RATEMCS1                         0x01
 154#define DESC90_RATEMCS2                         0x02
 155#define DESC90_RATEMCS3                         0x03
 156#define DESC90_RATEMCS4                         0x04
 157#define DESC90_RATEMCS5                         0x05
 158#define DESC90_RATEMCS6                         0x06
 159#define DESC90_RATEMCS7                         0x07
 160#define DESC90_RATEMCS8                         0x08
 161#define DESC90_RATEMCS9                         0x09
 162#define DESC90_RATEMCS10                        0x0a
 163#define DESC90_RATEMCS11                        0x0b
 164#define DESC90_RATEMCS12                        0x0c
 165#define DESC90_RATEMCS13                        0x0d
 166#define DESC90_RATEMCS14                        0x0e
 167#define DESC90_RATEMCS15                        0x0f
 168#define DESC90_RATEMCS32                        0x20
 169
 170#define RTL819X_DEFAULT_RF_TYPE RF_1T2R
 171
 172#define IEEE80211_WATCH_DOG_TIME    2000
 173#define         PHY_Beacon_RSSI_SLID_WIN_MAX            10
 174/* For Tx Power Tracking */
 175#define         OFDM_Table_Length       19
 176#define CCK_Table_length        12
 177
 178/* For rtl819x */
 179typedef struct _tx_desc_819x_usb {
 180        /* DWORD 0 */
 181        u16     PktSize;
 182        u8      Offset;
 183        u8      Reserved0:3;
 184        u8      CmdInit:1;
 185        u8      LastSeg:1;
 186        u8      FirstSeg:1;
 187        u8      LINIP:1;
 188        u8      OWN:1;
 189
 190        /* DWORD 1 */
 191        u8      TxFWInfoSize;
 192        u8      RATid:3;
 193        u8      DISFB:1;
 194        u8      USERATE:1;
 195        u8      MOREFRAG:1;
 196        u8      NoEnc:1;
 197        u8      PIFS:1;
 198        u8      QueueSelect:5;
 199        u8      NoACM:1;
 200        u8      Reserved1:2;
 201        u8      SecCAMID:5;
 202        u8      SecDescAssign:1;
 203        u8      SecType:2;
 204
 205        /* DWORD 2 */
 206        u16     TxBufferSize;
 207        u8      ResvForPaddingLen:7;
 208        u8      Reserved3:1;
 209        u8      Reserved4;
 210
 211        /* DWORD 3, 4, 5 */
 212        u32     Reserved5;
 213        u32     Reserved6;
 214        u32     Reserved7;
 215} tx_desc_819x_usb, *ptx_desc_819x_usb;
 216
 217#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
 218typedef struct _tx_desc_819x_usb_aggr_subframe {
 219        /* DWORD 0 */
 220        u16     PktSize;
 221        u8      Offset;
 222        u8      TxFWInfoSize;
 223
 224        /* DWORD 1 */
 225        u8      RATid:3;
 226        u8      DISFB:1;
 227        u8      USERATE:1;
 228        u8      MOREFRAG:1;
 229        u8      NoEnc:1;
 230        u8      PIFS:1;
 231        u8      QueueSelect:5;
 232        u8      NoACM:1;
 233        u8      Reserved1:2;
 234        u8      SecCAMID:5;
 235        u8      SecDescAssign:1;
 236        u8      SecType:2;
 237        u8      PacketID:7;
 238        u8      OWN:1;
 239} tx_desc_819x_usb_aggr_subframe, *ptx_desc_819x_usb_aggr_subframe;
 240#endif
 241
 242
 243
 244typedef struct _tx_desc_cmd_819x_usb {
 245        /* DWORD 0 */
 246        u16     Reserved0;
 247        u8      Reserved1;
 248        u8      Reserved2:3;
 249        u8      CmdInit:1;
 250        u8      LastSeg:1;
 251        u8      FirstSeg:1;
 252        u8      LINIP:1;
 253        u8      OWN:1;
 254
 255        /* DOWRD 1 */
 256        u8      TxFWInfoSize;
 257        u8      Reserved3;
 258        u8      QueueSelect;
 259        u8      Reserved4;
 260
 261        /* DOWRD 2 */
 262        u16     TxBufferSize;
 263        u16     Reserved5;
 264
 265        /* DWORD 3, 4, 5 */
 266        u32     Reserved6;
 267        u32     Reserved7;
 268        u32     Reserved8;
 269} tx_desc_cmd_819x_usb, *ptx_desc_cmd_819x_usb;
 270
 271
 272typedef struct _tx_fwinfo_819x_usb {
 273        /* DOWRD 0 */
 274        u8      TxRate:7;
 275        u8      CtsEnable:1;
 276        u8      RtsRate:7;
 277        u8      RtsEnable:1;
 278        u8      TxHT:1;
 279        u8      Short:1;        /* Error out, always on */
 280        u8      TxBandwidth:1;  /* Used for HT MCS rate only */
 281        u8      TxSubCarrier:2; /* Used for legacy OFDM rate only */
 282        u8      STBC:2;
 283        u8      AllowAggregation:1;
 284        /* Interpret RtsRate field as high throughput data rate */
 285        u8      RtsHT:1;
 286        u8      RtsShort:1;     /* Short PLCP for CCK or short GI for 11n MCS */
 287        u8      RtsBandwidth:1; /* Used for HT MCS rate only */
 288        u8      RtsSubcarrier:2;/* Used for legacy OFDM rate only */
 289        u8      RtsSTBC:2;
 290        /* Enable firmware to recalculate and assign packet duration */
 291        u8      EnableCPUDur:1;
 292
 293        /* DWORD 1 */
 294        u32     RxMF:2;
 295        u32     RxAMD:3;
 296        /* 1 indicate Tx info gathered by firmware and returned by Rx Cmd */
 297        u32     TxPerPktInfoFeedback:1;
 298        u32     Reserved1:2;
 299        u32     TxAGCOffSet:4;
 300        u32     TxAGCSign:1;
 301        u32     Tx_INFO_RSVD:6;
 302        u32     PacketID:13;
 303} tx_fwinfo_819x_usb, *ptx_fwinfo_819x_usb;
 304
 305struct rtl8192_rx_info {
 306        struct urb *urb;
 307        struct net_device *dev;
 308        u8 out_pipe;
 309};
 310
 311typedef struct rx_desc_819x_usb {
 312        /* DOWRD 0 */
 313        u16                 Length:14;
 314        u16                 CRC32:1;
 315        u16                 ICV:1;
 316        u8                  RxDrvInfoSize;
 317        u8                  Shift:2;
 318        u8                  PHYStatus:1;
 319        u8                  SWDec:1;
 320        u8                  Reserved1:4;
 321
 322        /* DWORD 1 */
 323        u32                 Reserved2;
 324} rx_desc_819x_usb, *prx_desc_819x_usb;
 325
 326#ifdef USB_RX_AGGREGATION_SUPPORT
 327typedef struct _rx_desc_819x_usb_aggr_subframe {
 328        /* DOWRD 0 */
 329        u16                     Length:14;
 330        u16                     CRC32:1;
 331        u16                     ICV:1;
 332        u8                      Offset;
 333        u8                      RxDrvInfoSize;
 334        /* DOWRD 1 */
 335        u8                      Shift:2;
 336        u8                      PHYStatus:1;
 337        u8                      SWDec:1;
 338        u8                      Reserved1:4;
 339        u8                      Reserved2;
 340        u16                     Reserved3;
 341} rx_desc_819x_usb_aggr_subframe, *prx_desc_819x_usb_aggr_subframe;
 342#endif
 343
 344typedef struct rx_drvinfo_819x_usb {
 345        /* DWORD 0 */
 346        u16                 Reserved1:12;
 347        u16                 PartAggr:1;
 348        u16                 FirstAGGR:1;
 349        u16                 Reserved2:2;
 350
 351        u8                  RxRate:7;
 352        u8                  RxHT:1;
 353
 354        u8                  BW:1;
 355        u8                  SPLCP:1;
 356        u8                  Reserved3:2;
 357        u8                  PAM:1;
 358        u8                  Mcast:1;
 359        u8                  Bcast:1;
 360        u8                  Reserved4:1;
 361
 362        /* DWORD 1 */
 363        u32                  TSFL;
 364
 365} rx_drvinfo_819x_usb, *prx_drvinfo_819x_usb;
 366
 367/* Support till 64 bit bus width OS */
 368#define MAX_DEV_ADDR_SIZE               8
 369/* For RTL8190 */
 370#define MAX_FIRMWARE_INFORMATION_SIZE   32
 371#define MAX_802_11_HEADER_LENGTH        (40 + MAX_FIRMWARE_INFORMATION_SIZE)
 372#define ENCRYPTION_MAX_OVERHEAD         128
 373#define USB_HWDESC_HEADER_LEN           sizeof(tx_desc_819x_usb)
 374#define TX_PACKET_SHIFT_BYTES           (USB_HWDESC_HEADER_LEN + sizeof(tx_fwinfo_819x_usb))
 375#define MAX_FRAGMENT_COUNT              8
 376#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
 377#define MAX_TRANSMIT_BUFFER_SIZE                        32000
 378#else
 379#define MAX_TRANSMIT_BUFFER_SIZE                        8000
 380#endif
 381#ifdef USB_TX_DRIVER_AGGREGATION_ENABLE
 382#define TX_PACKET_DRVAGGR_SUBFRAME_SHIFT_BYTES (sizeof(tx_desc_819x_usb_aggr_subframe) + sizeof(tx_fwinfo_819x_usb))
 383#endif
 384/* Octets for crc32 (FCS, ICV) */
 385#define scrclng                                 4
 386
 387typedef enum rf_optype {
 388        RF_OP_By_SW_3wire = 0,
 389        RF_OP_By_FW,
 390        RF_OP_MAX
 391} rf_op_type;
 392/* 8190 Loopback Mode definition */
 393typedef enum _rtl819xUsb_loopback {
 394        RTL819xU_NO_LOOPBACK = 0,
 395        RTL819xU_MAC_LOOPBACK = 1,
 396        RTL819xU_DMA_LOOPBACK = 2,
 397        RTL819xU_CCK_LOOPBACK = 3,
 398} rtl819xUsb_loopback_e;
 399
 400/* due to rtl8192 firmware */
 401typedef enum _desc_packet_type_e {
 402        DESC_PACKET_TYPE_INIT = 0,
 403        DESC_PACKET_TYPE_NORMAL = 1,
 404} desc_packet_type_e;
 405
 406typedef enum _firmware_status {
 407        FW_STATUS_0_INIT = 0,
 408        FW_STATUS_1_MOVE_BOOT_CODE = 1,
 409        FW_STATUS_2_MOVE_MAIN_CODE = 2,
 410        FW_STATUS_3_TURNON_CPU = 3,
 411        FW_STATUS_4_MOVE_DATA_CODE = 4,
 412        FW_STATUS_5_READY = 5,
 413} firmware_status_e;
 414
 415typedef struct _rt_firmare_seg_container {
 416        u16     seg_size;
 417        u8      *seg_ptr;
 418} fw_seg_container, *pfw_seg_container;
 419typedef struct _rt_firmware {
 420        firmware_status_e firmware_status;
 421        u16               cmdpacket_frag_thresold;
 422#define RTL8190_MAX_FIRMWARE_CODE_SIZE  64000
 423        u8                firmware_buf[RTL8190_MAX_FIRMWARE_CODE_SIZE];
 424        u16               firmware_buf_size;
 425} rt_firmware, *prt_firmware;
 426
 427/* Add this to 9100 bytes to receive A-MSDU from RT-AP */
 428#define MAX_RECEIVE_BUFFER_SIZE 9100
 429
 430typedef struct _rt_firmware_info_819xUsb {
 431        u8              sz_info[16];
 432} rt_firmware_info_819xUsb, *prt_firmware_info_819xUsb;
 433
 434/* Firmware Queue Layout */
 435#define NUM_OF_FIRMWARE_QUEUE           10
 436#define NUM_OF_PAGES_IN_FW              0x100
 437
 438#ifdef USE_ONE_PIPE
 439#define NUM_OF_PAGE_IN_FW_QUEUE_BE      0x000
 440#define NUM_OF_PAGE_IN_FW_QUEUE_BK      0x000
 441#define NUM_OF_PAGE_IN_FW_QUEUE_VI      0x0ff
 442#define NUM_OF_PAGE_IN_FW_QUEUE_VO      0x000
 443#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA    0
 444#define NUM_OF_PAGE_IN_FW_QUEUE_CMD     0x0
 445#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT    0x00
 446#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH    0
 447#define NUM_OF_PAGE_IN_FW_QUEUE_BCN     0x0
 448#define NUM_OF_PAGE_IN_FW_QUEUE_PUB     0x00
 449#else
 450
 451#define NUM_OF_PAGE_IN_FW_QUEUE_BE      0x020
 452#define NUM_OF_PAGE_IN_FW_QUEUE_BK      0x020
 453#define NUM_OF_PAGE_IN_FW_QUEUE_VI      0x040
 454#define NUM_OF_PAGE_IN_FW_QUEUE_VO      0x040
 455#define NUM_OF_PAGE_IN_FW_QUEUE_HCCA    0
 456#define NUM_OF_PAGE_IN_FW_QUEUE_CMD     0x4
 457#define NUM_OF_PAGE_IN_FW_QUEUE_MGNT    0x20
 458#define NUM_OF_PAGE_IN_FW_QUEUE_HIGH    0
 459#define NUM_OF_PAGE_IN_FW_QUEUE_BCN     0x4
 460#define NUM_OF_PAGE_IN_FW_QUEUE_PUB     0x18
 461
 462#endif
 463
 464#define APPLIED_RESERVED_QUEUE_IN_FW    0x80000000
 465#define RSVD_FW_QUEUE_PAGE_BK_SHIFT     0x00
 466#define RSVD_FW_QUEUE_PAGE_BE_SHIFT     0x08
 467#define RSVD_FW_QUEUE_PAGE_VI_SHIFT     0x10
 468#define RSVD_FW_QUEUE_PAGE_VO_SHIFT     0x18
 469#define RSVD_FW_QUEUE_PAGE_MGNT_SHIFT   0x10
 470#define RSVD_FW_QUEUE_PAGE_CMD_SHIFT    0x08
 471#define RSVD_FW_QUEUE_PAGE_BCN_SHIFT    0x00
 472#define RSVD_FW_QUEUE_PAGE_PUB_SHIFT    0x08
 473
 474/*
 475 * =================================================================
 476 * =================================================================
 477 */
 478
 479#define EPROM_93c46 0
 480#define EPROM_93c56 1
 481
 482#define DEFAULT_FRAG_THRESHOLD 2342U
 483#define MIN_FRAG_THRESHOLD     256U
 484#define DEFAULT_BEACONINTERVAL 0x64U
 485#define DEFAULT_BEACON_ESSID "Rtl819xU"
 486
 487#define DEFAULT_SSID ""
 488#define DEFAULT_RETRY_RTS 7
 489#define DEFAULT_RETRY_DATA 7
 490#define PRISM_HDR_SIZE 64
 491
 492#define         PHY_RSSI_SLID_WIN_MAX                           100
 493
 494
 495typedef enum _WIRELESS_MODE {
 496        WIRELESS_MODE_UNKNOWN = 0x00,
 497        WIRELESS_MODE_A = 0x01,
 498        WIRELESS_MODE_B = 0x02,
 499        WIRELESS_MODE_G = 0x04,
 500        WIRELESS_MODE_AUTO = 0x08,
 501        WIRELESS_MODE_N_24G = 0x10,
 502        WIRELESS_MODE_N_5G = 0x20
 503} WIRELESS_MODE;
 504
 505
 506#define RTL_IOCTL_WPA_SUPPLICANT                (SIOCIWFIRSTPRIV + 30)
 507
 508typedef struct buffer {
 509        struct buffer *next;
 510        u32 *buf;
 511
 512} buffer;
 513
 514typedef struct rtl_reg_debug {
 515        unsigned int  cmd;
 516        struct {
 517                unsigned char type;
 518                unsigned char addr;
 519                unsigned char page;
 520                unsigned char length;
 521        } head;
 522        unsigned char buf[0xff];
 523} rtl_reg_debug;
 524
 525
 526
 527
 528
 529
 530typedef struct _rt_9x_tx_rate_history {
 531        u32             cck[4];
 532        u32             ofdm[8];
 533        u32             ht_mcs[4][16];
 534} rt_tx_rahis_t, *prt_tx_rahis_t;
 535typedef struct _RT_SMOOTH_DATA_4RF {
 536        s8    elements[4][100]; /* array to store values */
 537        u32     index;            /* index to current array to store */
 538        u32     TotalNum;         /* num of valid elements */
 539        u32     TotalVal[4];      /* sum of valid elements */
 540} RT_SMOOTH_DATA_4RF, *PRT_SMOOTH_DATA_4RF;
 541
 542/* This maybe changed for D-cut larger aggregation size */
 543#define MAX_8192U_RX_SIZE                       8192
 544/* Stats seems messed up, clean it ASAP */
 545typedef struct Stats {
 546        unsigned long txrdu;
 547        unsigned long rxok;
 548        unsigned long rxframgment;
 549        unsigned long rxurberr;
 550        unsigned long rxstaterr;
 551        /* 0: Total, 1: OK, 2: CRC, 3: ICV */
 552        unsigned long received_rate_histogram[4][32];
 553        /* 0: Long preamble/GI, 1: Short preamble/GI */
 554        unsigned long received_preamble_GI[2][32];
 555        /* level: (<4K), (4K~8K), (8K~16K), (16K~32K), (32K~64K) */
 556        unsigned long rx_AMPDUsize_histogram[5];
 557        /* level: (<5), (5~10), (10~20), (20~40), (>40) */
 558        unsigned long rx_AMPDUnum_histogram[5];
 559        unsigned long numpacket_matchbssid;
 560        unsigned long numpacket_toself;
 561        unsigned long num_process_phyinfo;
 562        unsigned long numqry_phystatus;
 563        unsigned long numqry_phystatusCCK;
 564        unsigned long numqry_phystatusHT;
 565        /* 0: 20M, 1: funn40M, 2: upper20M, 3: lower20M, 4: duplicate */
 566        unsigned long received_bwtype[5];
 567        unsigned long txnperr;
 568        unsigned long txnpdrop;
 569        unsigned long txresumed;
 570        unsigned long txnpokint;
 571        unsigned long txoverflow;
 572        unsigned long txlpokint;
 573        unsigned long txlpdrop;
 574        unsigned long txlperr;
 575        unsigned long txbeokint;
 576        unsigned long txbedrop;
 577        unsigned long txbeerr;
 578        unsigned long txbkokint;
 579        unsigned long txbkdrop;
 580        unsigned long txbkerr;
 581        unsigned long txviokint;
 582        unsigned long txvidrop;
 583        unsigned long txvierr;
 584        unsigned long txvookint;
 585        unsigned long txvodrop;
 586        unsigned long txvoerr;
 587        unsigned long txbeaconokint;
 588        unsigned long txbeacondrop;
 589        unsigned long txbeaconerr;
 590        unsigned long txmanageokint;
 591        unsigned long txmanagedrop;
 592        unsigned long txmanageerr;
 593        unsigned long txdatapkt;
 594        unsigned long txfeedback;
 595        unsigned long txfeedbackok;
 596
 597        unsigned long txoktotal;
 598        unsigned long txokbytestotal;
 599        unsigned long txokinperiod;
 600        unsigned long txmulticast;
 601        unsigned long txbytesmulticast;
 602        unsigned long txbroadcast;
 603        unsigned long txbytesbroadcast;
 604        unsigned long txunicast;
 605        unsigned long txbytesunicast;
 606
 607        unsigned long rxoktotal;
 608        unsigned long rxbytesunicast;
 609        unsigned long txfeedbackfail;
 610        unsigned long txerrtotal;
 611        unsigned long txerrbytestotal;
 612        unsigned long txerrmulticast;
 613        unsigned long txerrbroadcast;
 614        unsigned long txerrunicast;
 615        unsigned long txretrycount;
 616        unsigned long txfeedbackretry;
 617        u8            last_packet_rate;
 618        unsigned long slide_signal_strength[100];
 619        unsigned long slide_evm[100];
 620        /* For recording sliding window's RSSI value */
 621        unsigned long slide_rssi_total;
 622        /* For recording sliding window's EVM value */
 623        unsigned long slide_evm_total;
 624        /* Transformed in dbm. Beautified signal strength for UI, not correct */
 625        long signal_strength;
 626        long signal_quality;
 627        long last_signal_strength_inpercent;
 628        /* Correct smoothed ss in dbm, only used in driver
 629         * to report real power now
 630         */
 631        long recv_signal_power;
 632        u8 rx_rssi_percentage[4];
 633        u8 rx_evm_percentage[2];
 634        long rxSNRdB[4];
 635        rt_tx_rahis_t txrate;
 636        /* For beacon RSSI */
 637        u32 Slide_Beacon_pwdb[100];
 638        u32 Slide_Beacon_Total;
 639        RT_SMOOTH_DATA_4RF              cck_adc_pwdb;
 640
 641        u32     CurrentShowTxate;
 642} Stats;
 643
 644
 645/* Bandwidth Offset */
 646#define HAL_PRIME_CHNL_OFFSET_DONT_CARE         0
 647#define HAL_PRIME_CHNL_OFFSET_LOWER                     1
 648#define HAL_PRIME_CHNL_OFFSET_UPPER                     2
 649
 650
 651typedef struct  ChnlAccessSetting {
 652        u16 SIFS_Timer;
 653        u16 DIFS_Timer;
 654        u16 SlotTimeTimer;
 655        u16 EIFS_Timer;
 656        u16 CWminIndex;
 657        u16 CWmaxIndex;
 658} *PCHANNEL_ACCESS_SETTING, CHANNEL_ACCESS_SETTING;
 659
 660typedef struct _BB_REGISTER_DEFINITION {
 661        /* set software control:        0x870~0x877 [8 bytes]  */
 662        u32 rfintfs;
 663        /* readback data:               0x8e0~0x8e7 [8 bytes]  */
 664        u32 rfintfi;
 665        /* output data:                 0x860~0x86f [16 bytes] */
 666        u32 rfintfo;
 667        /* output enable:               0x860~0x86f [16 bytes] */
 668        u32 rfintfe;
 669        /* LSSI data:                   0x840~0x84f [16 bytes] */
 670        u32 rf3wireOffset;
 671        /* BB Band Select:              0x878~0x87f [8 bytes]  */
 672        u32 rfLSSI_Select;
 673        /* Tx gain stage:               0x80c~0x80f [4 bytes]  */
 674        u32 rfTxGainStage;
 675        /* wire parameter control1:     0x820~0x823, 0x828~0x82b,
 676         *                              0x830~0x833, 0x838~0x83b [16 bytes]
 677         */
 678        u32 rfHSSIPara1;
 679        /* wire parameter control2:     0x824~0x827, 0x82c~0x82f,
 680         *                              0x834~0x837, 0x83c~0x83f [16 bytes]
 681         */
 682        u32 rfHSSIPara2;
 683        /* Tx Rx antenna control:       0x858~0x85f [16 bytes] */
 684        u32 rfSwitchControl;
 685        /* AGC parameter control1:      0xc50~0xc53, 0xc58~0xc5b,
 686         *                              0xc60~0xc63, 0xc68~0xc6b [16 bytes]
 687         */
 688        u32 rfAGCControl1;
 689        /* AGC parameter control2:      0xc54~0xc57, 0xc5c~0xc5f,
 690         *                              0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
 691         */
 692        u32 rfAGCControl2;
 693        /* OFDM Rx IQ imbalance matrix: 0xc14~0xc17, 0xc1c~0xc1f,
 694         *                              0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
 695         */
 696        u32 rfRxIQImbalance;
 697        /* Rx IQ DC offset and Rx digital filter, Rx DC notch filter:
 698         *                              0xc10~0xc13, 0xc18~0xc1b,
 699         *                              0xc20~0xc23, 0xc28~0xc2b [16 bytes]
 700         */
 701        u32 rfRxAFE;
 702        /* OFDM Tx IQ imbalance matrix: 0xc80~0xc83, 0xc88~0xc8b,
 703         *                              0xc90~0xc93, 0xc98~0xc9b [16 bytes]
 704         */
 705        u32 rfTxIQImbalance;
 706        /* Tx IQ DC Offset and Tx DFIR type:
 707         *                              0xc84~0xc87, 0xc8c~0xc8f,
 708         *                              0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
 709         */
 710        u32 rfTxAFE;
 711        /* LSSI RF readback data:       0x8a0~0x8af [16 bytes] */
 712        u32 rfLSSIReadBack;
 713} BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
 714
 715typedef enum _RT_RF_TYPE_819xU {
 716        RF_TYPE_MIN = 0,
 717        RF_8225,
 718        RF_8256,
 719        RF_8258,
 720        RF_PSEUDO_11N = 4,
 721} RT_RF_TYPE_819xU, *PRT_RF_TYPE_819xU;
 722
 723typedef struct _rate_adaptive {
 724        u8                              rate_adaptive_disabled;
 725        u8                              ratr_state;
 726        u16                             reserve;
 727
 728        u32                             high_rssi_thresh_for_ra;
 729        u32                             high2low_rssi_thresh_for_ra;
 730        u8                              low2high_rssi_thresh_for_ra40M;
 731        u32                             low_rssi_thresh_for_ra40M;
 732        u8                              low2high_rssi_thresh_for_ra20M;
 733        u32                             low_rssi_thresh_for_ra20M;
 734        u32                             upper_rssi_threshold_ratr;
 735        u32                             middle_rssi_threshold_ratr;
 736        u32                             low_rssi_threshold_ratr;
 737        u32                             low_rssi_threshold_ratr_40M;
 738        u32                             low_rssi_threshold_ratr_20M;
 739        u8                              ping_rssi_enable;
 740        u32                             ping_rssi_ratr;
 741        u32                             ping_rssi_thresh_for_ra;
 742        u32                             last_ratr;
 743
 744} rate_adaptive, *prate_adaptive;
 745
 746#define TxBBGainTableLength 37
 747#define CCKTxBBGainTableLength 23
 748
 749typedef struct _txbbgain_struct {
 750        long    txbb_iq_amplifygain;
 751        u32     txbbgain_value;
 752} txbbgain_struct, *ptxbbgain_struct;
 753
 754typedef struct _ccktxbbgain_struct {
 755        /* The value is from a22 to a29, one byte one time is much safer */
 756        u8      ccktxbb_valuearray[8];
 757} ccktxbbgain_struct, *pccktxbbgain_struct;
 758
 759
 760typedef struct _init_gain {
 761        u8                              xaagccore1;
 762        u8                              xbagccore1;
 763        u8                              xcagccore1;
 764        u8                              xdagccore1;
 765        u8                              cca;
 766
 767} init_gain, *pinit_gain;
 768
 769typedef struct _phy_ofdm_rx_status_report_819xusb {
 770        u8      trsw_gain_X[4];
 771        u8      pwdb_all;
 772        u8      cfosho_X[4];
 773        u8      cfotail_X[4];
 774        u8      rxevm_X[2];
 775        u8      rxsnr_X[4];
 776        u8      pdsnr_X[2];
 777        u8      csi_current_X[2];
 778        u8      csi_target_X[2];
 779        u8      sigevm;
 780        u8      max_ex_pwr;
 781        u8      sgi_en;
 782        u8  rxsc_sgien_exflg;
 783} phy_sts_ofdm_819xusb_t;
 784
 785typedef struct _phy_cck_rx_status_report_819xusb {
 786        /* For CCK rate descriptor. This is an unsigned 8:1 variable.
 787         * LSB bit presend 0.5. And MSB 7 bts presend a signed value.
 788         * Range from -64~+63.5.
 789         */
 790        u8      adc_pwdb_X[4];
 791        u8      sq_rpt;
 792        u8      cck_agc_rpt;
 793} phy_sts_cck_819xusb_t;
 794
 795
 796struct phy_ofdm_rx_status_rxsc_sgien_exintfflag {
 797        u8                      reserved:4;
 798        u8                      rxsc:2;
 799        u8                      sgi_en:1;
 800        u8                      ex_intf_flag:1;
 801};
 802
 803typedef enum _RT_CUSTOMER_ID {
 804        RT_CID_DEFAULT = 0,
 805        RT_CID_8187_ALPHA0 = 1,
 806        RT_CID_8187_SERCOMM_PS = 2,
 807        RT_CID_8187_HW_LED = 3,
 808        RT_CID_8187_NETGEAR = 4,
 809        RT_CID_WHQL = 5,
 810        RT_CID_819x_CAMEO  = 6,
 811        RT_CID_819x_RUNTOP = 7,
 812        RT_CID_819x_Senao = 8,
 813        RT_CID_TOSHIBA = 9,
 814        RT_CID_819x_Netcore = 10,
 815        RT_CID_Nettronix = 11,
 816        RT_CID_DLINK = 12,
 817        RT_CID_PRONET = 13,
 818} RT_CUSTOMER_ID, *PRT_CUSTOMER_ID;
 819
 820/*
 821 * ==========================================================================
 822 * LED customization.
 823 * ==========================================================================
 824 */
 825
 826typedef enum _LED_STRATEGY_8190 {
 827        SW_LED_MODE0, /* SW control 1 LED via GPIO0. It is default option. */
 828        SW_LED_MODE1, /* SW control for PCI Express */
 829        SW_LED_MODE2, /* SW control for Cameo. */
 830        SW_LED_MODE3, /* SW control for RunTop. */
 831        SW_LED_MODE4, /* SW control for Netcore. */
 832        /* HW control 2 LEDs, LED0 and LED1 (4 different control modes) */
 833        HW_LED,
 834} LED_STRATEGY_8190, *PLED_STRATEGY_8190;
 835
 836typedef enum _RESET_TYPE {
 837        RESET_TYPE_NORESET = 0x00,
 838        RESET_TYPE_NORMAL = 0x01,
 839        RESET_TYPE_SILENT = 0x02
 840} RESET_TYPE;
 841
 842/* The simple tx command OP code. */
 843typedef enum _tag_TxCmd_Config_Index {
 844        TXCMD_TXRA_HISTORY_CTRL                         = 0xFF900000,
 845        TXCMD_RESET_TX_PKT_BUFF                         = 0xFF900001,
 846        TXCMD_RESET_RX_PKT_BUFF                         = 0xFF900002,
 847        TXCMD_SET_TX_DURATION                           = 0xFF900003,
 848        TXCMD_SET_RX_RSSI                                               = 0xFF900004,
 849        TXCMD_SET_TX_PWR_TRACKING                       = 0xFF900005,
 850        TXCMD_XXXX_CTRL,
 851} DCMD_TXCMD_OP;
 852
 853typedef struct r8192_priv {
 854        struct usb_device *udev;
 855        /* For maintain info from eeprom */
 856        short epromtype;
 857        u16 eeprom_vid;
 858        u16 eeprom_pid;
 859        u8  eeprom_CustomerID;
 860        u8  eeprom_ChannelPlan;
 861        RT_CUSTOMER_ID CustomerID;
 862        LED_STRATEGY_8190       LedStrategy;
 863        u8  txqueue_to_outpipemap[9];
 864        int irq;
 865        struct ieee80211_device *ieee80211;
 866
 867        /* O: rtl8192, 1: rtl8185 V B/C, 2: rtl8185 V D */
 868        short card_8192;
 869        /* If TCR reports card V B/C, this discriminates */
 870        u8 card_8192_version;
 871        short enable_gpio0;
 872        enum card_type {
 873                PCI, MINIPCI, CARDBUS, USB
 874        } card_type;
 875        short hw_plcp_len;
 876        short plcp_preamble_mode;
 877
 878        spinlock_t irq_lock;
 879        spinlock_t tx_lock;
 880        struct mutex mutex;
 881
 882        u16 irq_mask;
 883        short chan;
 884        short sens;
 885        short max_sens;
 886
 887
 888        short up;
 889        /* If 1, allow bad crc frame, reception in monitor mode */
 890        short crcmon;
 891
 892        struct mutex wx_mutex;
 893
 894        u8 rf_type;                     /* 0: 1T2R, 1: 2T4R */
 895        RT_RF_TYPE_819xU rf_chip;
 896
 897        short (*rf_set_sens)(struct net_device *dev, short sens);
 898        u8 (*rf_set_chan)(struct net_device *dev, u8 ch);
 899        void (*rf_close)(struct net_device *dev);
 900        void (*rf_init)(struct net_device *dev);
 901        short promisc;
 902        /* Stats */
 903        struct Stats stats;
 904        struct iw_statistics wstats;
 905
 906        /* RX stuff */
 907        struct urb **rx_urb;
 908        struct urb **rx_cmd_urb;
 909#ifdef THOMAS_BEACON
 910        u32 *oldaddr;
 911#endif
 912#ifdef THOMAS_TASKLET
 913        atomic_t irt_counter; /* count for irq_rx_tasklet */
 914#endif
 915#ifdef JACKSON_NEW_RX
 916        struct sk_buff **pp_rxskb;
 917        int     rx_inx;
 918#endif
 919
 920       struct sk_buff_head rx_queue;
 921       struct sk_buff_head skb_queue;
 922       struct work_struct qos_activate;
 923        short  tx_urb_index;
 924        atomic_t tx_pending[0x10]; /* UART_PRIORITY + 1 */
 925
 926
 927        struct tasklet_struct irq_rx_tasklet;
 928        struct urb *rxurb_task;
 929
 930        /* Tx Related variables */
 931        u16     ShortRetryLimit;
 932        u16     LongRetryLimit;
 933        u32     TransmitConfig;
 934        u8      RegCWinMin;     /* For turbo mode CW adaptive */
 935
 936        u32     LastRxDescTSFHigh;
 937        u32     LastRxDescTSFLow;
 938
 939
 940        /* Rx Related variables */
 941        u16     EarlyRxThreshold;
 942        u32     ReceiveConfig;
 943        u8      AcmControl;
 944
 945        u8      RFProgType;
 946
 947        u8 retry_data;
 948        u8 retry_rts;
 949        u16 rts;
 950
 951        struct  ChnlAccessSetting  ChannelAccessSetting;
 952        struct work_struct reset_wq;
 953
 954/**********************************************************/
 955        /* For rtl819xUsb */
 956        u16     basic_rate;
 957        u8      short_preamble;
 958        u8      slot_time;
 959        bool    bDcut;
 960        bool bCurrentRxAggrEnable;
 961        u8 Rf_Mode;     /* For Firmware RF -R/W switch */
 962        prt_firmware            pFirmware;
 963        rtl819xUsb_loopback_e   LoopbackMode;
 964        u16 EEPROMTxPowerDiff;
 965        u8 EEPROMThermalMeter;
 966        u8 EEPROMPwDiff;
 967        u8 EEPROMCrystalCap;
 968        u8 EEPROM_Def_Ver;
 969        u8 EEPROMTxPowerLevelCCK;               /* CCK channel 1~14 */
 970        u8 EEPROMTxPowerLevelCCK_V1[3];
 971        u8 EEPROMTxPowerLevelOFDM24G[3];        /* OFDM 2.4G channel 1~14 */
 972        u8 EEPROMTxPowerLevelOFDM5G[24];        /* OFDM 5G */
 973
 974        /* PHY related */
 975        BB_REGISTER_DEFINITION_T PHYRegDef[4];  /* Radio A/B/C/D */
 976        /* Read/write are allow for following hardware information variables */
 977        u32     MCSTxPowerLevelOriginalOffset[6];
 978        u32     CCKTxPowerLevelOriginalOffset;
 979        u8      TxPowerLevelCCK[14];            /* CCK channel 1~14 */
 980        u8      TxPowerLevelOFDM24G[14];        /* OFDM 2.4G channel 1~14 */
 981        u8      TxPowerLevelOFDM5G[14];         /* OFDM 5G */
 982        u32     Pwr_Track;
 983        u8      TxPowerDiff;
 984        u8      AntennaTxPwDiff[2]; /* Antenna gain offset, 0: B, 1: C, 2: D */
 985        u8      CrystalCap;
 986        u8      ThermalMeter[2];    /* index 0: RFIC0, index 1: RFIC1 */
 987
 988        u8      CckPwEnl;
 989        /* Use to calculate PWBD */
 990        u8      bCckHighPower;
 991        long    undecorated_smoothed_pwdb;
 992
 993        /* For set channel */
 994        u8      SwChnlInProgress;
 995        u8      SwChnlStage;
 996        u8      SwChnlStep;
 997        u8      SetBWModeInProgress;
 998        HT_CHANNEL_WIDTH                CurrentChannelBW;
 999        u8      ChannelPlan;
1000        /* 8190 40MHz mode */

1001        /* Control channel sub-carrier */
1002        u8      nCur40MhzPrimeSC;
1003        /* Test for shorten RF configuration time.
1004         * We save RF reg0 in this variable to reduce RF reading.
1005         */
1006        u32                                     RfReg0Value[4];
1007        u8                                      NumTotalRFPath;
1008        bool                            brfpath_rxenable[4];
1009        /* RF set related */
1010        bool                            SetRFPowerStateInProgress;
1011        struct timer_list watch_dog_timer;
1012
1013        /* For dynamic mechanism */
1014        /* Tx Power Control for Near/Far Range */
1015        bool    bdynamic_txpower;
1016        bool    bDynamicTxHighPower;
1017        bool    bDynamicTxLowPower;
1018        bool    bLastDTPFlag_High;
1019        bool    bLastDTPFlag_Low;
1020
1021        bool    bstore_last_dtpflag;
1022        /* Define to discriminate on High power State or
1023         * on sitesurvey to change Tx gain index
1024         */
1025        bool    bstart_txctrl_bydtp;
1026        rate_adaptive rate_adaptive;
1027        /* TX power tracking
1028         * OPEN/CLOSE TX POWER TRACKING
1029         */
1030        txbbgain_struct txbbgain_table[TxBBGainTableLength];
1031        u8              txpower_count; /* For 6 sec do tracking again */
1032        bool            btxpower_trackingInit;
1033        u8              OFDM_index;
1034        u8              CCK_index;
1035        /* CCK TX Power Tracking */
1036        ccktxbbgain_struct      cck_txbbgain_table[CCKTxBBGainTableLength];
1037        ccktxbbgain_struct      cck_txbbgain_ch14_table[CCKTxBBGainTableLength];
1038        u8 rfa_txpowertrackingindex;
1039        u8 rfa_txpowertrackingindex_real;
1040        u8 rfa_txpowertracking_default;
1041        u8 rfc_txpowertrackingindex;
1042        u8 rfc_txpowertrackingindex_real;
1043
1044        s8 cck_present_attenuation;
1045        u8 cck_present_attenuation_20Mdefault;
1046        u8 cck_present_attenuation_40Mdefault;
1047        s8 cck_present_attenuation_difference;
1048        bool btxpower_tracking;
1049        bool bcck_in_ch14;
1050        bool btxpowerdata_readfromEEPORM;
1051        u16     TSSI_13dBm;
1052        init_gain initgain_backup;
1053        u8 DefaultInitialGain[4];
1054        /* For EDCA Turbo mode */
1055        bool            bis_any_nonbepkts;
1056        bool            bcurrent_turbo_EDCA;
1057        bool            bis_cur_rdlstate;
1058        struct timer_list fsync_timer;
1059        bool bfsync_processing; /* 500ms Fsync timer is active or not */
1060        u32     rate_record;
1061        u32     rateCountDiffRecord;
1062        u32     ContinueDiffCount;
1063        bool bswitch_fsync;
1064
1065        u8      framesync;
1066        u32     framesyncC34;
1067        u8      framesyncMonitor;
1068        u16     nrxAMPDU_size;
1069        u8      nrxAMPDU_aggr_num;
1070
1071        /* For gpio */
1072         bool bHwRadioOff;
1073
1074        u32 reset_count;
1075        bool bpbc_pressed;
1076        u32 txpower_checkcnt;
1077        u32 txpower_tracking_callback_cnt;
1078        u8 thermal_read_val[40];
1079        u8 thermal_readback_index;
1080        u32 ccktxpower_adjustcnt_not_ch14;
1081        u32 ccktxpower_adjustcnt_ch14;
1082        u8 tx_fwinfo_force_subcarriermode;
1083        u8 tx_fwinfo_force_subcarrierval;
1084        /* For silent reset */
1085        RESET_TYPE      ResetProgress;
1086        bool            bForcedSilentReset;
1087        bool            bDisableNormalResetCheck;
1088        u16             TxCounter;
1089        u16             RxCounter;
1090        int             IrpPendingCount;
1091        bool            bResetInProgress;
1092        bool            force_reset;
1093        u8              InitialGainOperateType;
1094
1095        u16             SifsTime;
1096
1097        /* Define work item */
1098
1099        struct delayed_work update_beacon_wq;
1100        struct delayed_work watch_dog_wq;
1101        struct delayed_work txpower_tracking_wq;
1102        struct delayed_work rfpath_check_wq;
1103        struct delayed_work gpio_change_rf_wq;
1104        struct delayed_work initialgain_operate_wq;
1105        struct workqueue_struct *priv_wq;
1106} r8192_priv;
1107
1108/* For rtl8187B */
1109typedef enum{
1110        BULK_PRIORITY = 0x01,
1111        LOW_PRIORITY,
1112        NORM_PRIORITY,
1113        VO_PRIORITY,
1114        VI_PRIORITY,
1115        BE_PRIORITY,
1116        BK_PRIORITY,
1117        RSVD2,
1118        RSVD3,
1119        BEACON_PRIORITY,
1120        HIGH_PRIORITY,
1121        MANAGE_PRIORITY,
1122        RSVD4,
1123        RSVD5,
1124        UART_PRIORITY
1125} priority_t;
1126
1127typedef enum {
1128        NIC_8192U = 1,
1129        NIC_8190P = 2,
1130        NIC_8192E = 3,
1131} nic_t;
1132
1133bool init_firmware(struct net_device *dev);
1134short rtl819xU_tx_cmd(struct net_device *dev, struct sk_buff *skb);
1135short rtl8192_tx(struct net_device *dev, struct sk_buff *skb);
1136
1137u32 read_cam(struct net_device *dev, u8 addr);
1138void write_cam(struct net_device *dev, u8 addr, u32 data);
1139
1140int read_nic_byte(struct net_device *dev, int x, u8 *data);
1141int read_nic_byte_E(struct net_device *dev, int x, u8 *data);
1142int read_nic_dword(struct net_device *dev, int x, u32 *data);
1143int read_nic_word(struct net_device *dev, int x, u16 *data);
1144int write_nic_byte(struct net_device *dev, int x, u8 y);
1145int write_nic_byte_E(struct net_device *dev, int x, u8 y);
1146int write_nic_word(struct net_device *dev, int x, u16 y);
1147int write_nic_dword(struct net_device *dev, int x, u32 y);
1148void force_pci_posting(struct net_device *dev);
1149
1150void rtl8192_rtx_disable(struct net_device *dev);
1151void rtl8192_rx_enable(struct net_device *dev);
1152void rtl8192_tx_enable(struct net_device *dev);
1153
1154void rtl8192_disassociate(struct net_device *dev);
1155void rtl8185_set_rf_pins_enable(struct net_device *dev, u32 a);
1156
1157void rtl8192_set_anaparam(struct net_device *dev, u32 a);
1158void rtl8185_set_anaparam2(struct net_device *dev, u32 a);
1159void rtl8192_update_msr(struct net_device *dev);
1160int rtl8192_down(struct net_device *dev);
1161int rtl8192_up(struct net_device *dev);
1162void rtl8192_commit(struct net_device *dev);
1163void rtl8192_set_chan(struct net_device *dev, short ch);
1164void write_phy(struct net_device *dev, u8 adr, u8 data);
1165void write_phy_cck(struct net_device *dev, u8 adr, u32 data);
1166void write_phy_ofdm(struct net_device *dev, u8 adr, u32 data);
1167void rtl8185_tx_antenna(struct net_device *dev, u8 ant);
1168void rtl8192_set_rxconf(struct net_device *dev);
1169void rtl819xusb_beacon_tx(struct net_device *dev, u16 tx_rate);
1170
1171void EnableHWSecurityConfig8192(struct net_device *dev);
1172void setKey(struct net_device *dev, u8 EntryNo, u8 KeyIndex, u16 KeyType, u8 *MacAddr, u8 DefaultKey, u32 *KeyContent);
1173
1174
1175#endif
1176