1#ifndef DDK750_DISPLAY_H__ 2#define DDK750_DISPLAY_H__ 3 4/* 5 * panel path select 6 * 80000[29:28] 7 */ 8 9#define PNL_2_OFFSET 0 10#define PNL_2_MASK (3 << PNL_2_OFFSET) 11#define PNL_2_USAGE (PNL_2_MASK << 16) 12#define PNL_2_PRI ((0 << PNL_2_OFFSET) | PNL_2_USAGE) 13#define PNL_2_SEC ((2 << PNL_2_OFFSET) | PNL_2_USAGE) 14 15/* 16 * primary timing & plane enable bit 17 * 1: 80000[8] & 80000[2] on 18 * 0: both off 19 */ 20#define PRI_TP_OFFSET 4 21#define PRI_TP_MASK BIT(PRI_TP_OFFSET) 22#define PRI_TP_USAGE (PRI_TP_MASK << 16) 23#define PRI_TP_ON ((0x1 << PRI_TP_OFFSET) | PRI_TP_USAGE) 24#define PRI_TP_OFF ((0x0 << PRI_TP_OFFSET) | PRI_TP_USAGE) 25 26/* 27 * panel sequency status 28 * 80000[27:24] 29 */ 30#define PNL_SEQ_OFFSET 6 31#define PNL_SEQ_MASK BIT(PNL_SEQ_OFFSET) 32#define PNL_SEQ_USAGE (PNL_SEQ_MASK << 16) 33#define PNL_SEQ_ON (BIT(PNL_SEQ_OFFSET) | PNL_SEQ_USAGE) 34#define PNL_SEQ_OFF ((0 << PNL_SEQ_OFFSET) | PNL_SEQ_USAGE) 35 36/* 37 * dual digital output 38 * 80000[19] 39 */ 40#define DUAL_TFT_OFFSET 8 41#define DUAL_TFT_MASK BIT(DUAL_TFT_OFFSET) 42#define DUAL_TFT_USAGE (DUAL_TFT_MASK << 16) 43#define DUAL_TFT_ON (BIT(DUAL_TFT_OFFSET) | DUAL_TFT_USAGE) 44#define DUAL_TFT_OFF ((0 << DUAL_TFT_OFFSET) | DUAL_TFT_USAGE) 45 46/* 47 * secondary timing & plane enable bit 48 * 1:80200[8] & 80200[2] on 49 * 0: both off 50 */ 51#define SEC_TP_OFFSET 5 52#define SEC_TP_MASK BIT(SEC_TP_OFFSET) 53#define SEC_TP_USAGE (SEC_TP_MASK << 16) 54#define SEC_TP_ON ((0x1 << SEC_TP_OFFSET) | SEC_TP_USAGE) 55#define SEC_TP_OFF ((0x0 << SEC_TP_OFFSET) | SEC_TP_USAGE) 56 57/* 58 * crt path select 59 * 80200[19:18] 60 */ 61#define CRT_2_OFFSET 2 62#define CRT_2_MASK (3 << CRT_2_OFFSET) 63#define CRT_2_USAGE (CRT_2_MASK << 16) 64#define CRT_2_PRI ((0x0 << CRT_2_OFFSET) | CRT_2_USAGE) 65#define CRT_2_SEC ((0x2 << CRT_2_OFFSET) | CRT_2_USAGE) 66 67/* 68 * DAC affect both DVI and DSUB 69 * 4[20] 70 */ 71#define DAC_OFFSET 7 72#define DAC_MASK BIT(DAC_OFFSET) 73#define DAC_USAGE (DAC_MASK << 16) 74#define DAC_ON ((0x0 << DAC_OFFSET) | DAC_USAGE) 75#define DAC_OFF ((0x1 << DAC_OFFSET) | DAC_USAGE) 76 77/* 78 * DPMS only affect D-SUB head 79 * 0[31:30] 80 */ 81#define DPMS_OFFSET 9 82#define DPMS_MASK (3 << DPMS_OFFSET) 83#define DPMS_USAGE (DPMS_MASK << 16) 84#define DPMS_OFF ((3 << DPMS_OFFSET) | DPMS_USAGE) 85#define DPMS_ON ((0 << DPMS_OFFSET) | DPMS_USAGE) 86 87/* 88 * LCD1 means panel path TFT1 & panel path DVI (so enable DAC) 89 * CRT means crt path DSUB 90 */ 91typedef enum _disp_output_t { 92 do_LCD1_PRI = PNL_2_PRI | PRI_TP_ON | PNL_SEQ_ON | DAC_ON, 93 do_LCD1_SEC = PNL_2_SEC | SEC_TP_ON | PNL_SEQ_ON | DAC_ON, 94 do_LCD2_PRI = CRT_2_PRI | PRI_TP_ON | DUAL_TFT_ON, 95 do_LCD2_SEC = CRT_2_SEC | SEC_TP_ON | DUAL_TFT_ON, 96 /* 97 * do_DSUB_PRI = CRT_2_PRI | PRI_TP_ON | DPMS_ON|DAC_ON, 98 * do_DSUB_SEC = CRT_2_SEC | SEC_TP_ON | DPMS_ON|DAC_ON, 99 */ 100 do_CRT_PRI = CRT_2_PRI | PRI_TP_ON | DPMS_ON | DAC_ON, 101 do_CRT_SEC = CRT_2_SEC | SEC_TP_ON | DPMS_ON | DAC_ON, 102} 103disp_output_t; 104 105void ddk750_setLogicalDispOut(disp_output_t output); 106 107#endif 108