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7#ifndef DSL3510_H_
8#define DSL3510_H_
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10#include <linux/idr.h>
11#include <linux/mutex.h>
12#include <linux/workqueue.h>
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29struct tb_nhi {
30 struct mutex lock;
31 struct pci_dev *pdev;
32 void __iomem *iobase;
33 struct tb_ring **tx_rings;
34 struct tb_ring **rx_rings;
35 struct ida msix_ida;
36 bool going_away;
37 struct work_struct interrupt_work;
38 u32 hop_count;
39};
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60struct tb_ring {
61 struct mutex lock;
62 struct tb_nhi *nhi;
63 int size;
64 int hop;
65 int head;
66 int tail;
67 struct ring_desc *descriptors;
68 dma_addr_t descriptors_dma;
69 struct list_head queue;
70 struct list_head in_flight;
71 struct work_struct work;
72 bool is_tx:1;
73 bool running:1;
74 int irq;
75 u8 vector;
76 unsigned int flags;
77};
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80#define RING_FLAG_NO_SUSPEND BIT(0)
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82struct ring_frame;
83typedef void (*ring_cb)(struct tb_ring*, struct ring_frame*, bool canceled);
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88struct ring_frame {
89 dma_addr_t buffer_phy;
90 ring_cb callback;
91 struct list_head list;
92 u32 size:12;
93 u32 flags:12;
94 u32 eof:4;
95 u32 sof:4;
96};
97
98#define TB_FRAME_SIZE 0x100
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100struct tb_ring *ring_alloc_tx(struct tb_nhi *nhi, int hop, int size,
101 unsigned int flags);
102struct tb_ring *ring_alloc_rx(struct tb_nhi *nhi, int hop, int size,
103 unsigned int flags);
104void ring_start(struct tb_ring *ring);
105void ring_stop(struct tb_ring *ring);
106void ring_free(struct tb_ring *ring);
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108int __ring_enqueue(struct tb_ring *ring, struct ring_frame *frame);
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124static inline int ring_rx(struct tb_ring *ring, struct ring_frame *frame)
125{
126 WARN_ON(ring->is_tx);
127 return __ring_enqueue(ring, frame);
128}
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143static inline int ring_tx(struct tb_ring *ring, struct ring_frame *frame)
144{
145 WARN_ON(!ring->is_tx);
146 return __ring_enqueue(ring, frame);
147}
148
149enum nhi_fw_mode {
150 NHI_FW_SAFE_MODE,
151 NHI_FW_AUTH_MODE,
152 NHI_FW_EP_MODE,
153 NHI_FW_CM_MODE,
154};
155
156enum nhi_mailbox_cmd {
157 NHI_MAILBOX_SAVE_DEVS = 0x05,
158 NHI_MAILBOX_DISCONNECT_PCIE_PATHS = 0x06,
159 NHI_MAILBOX_DRV_UNLOADS = 0x07,
160 NHI_MAILBOX_ALLOW_ALL_DEVS = 0x23,
161};
162
163int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data);
164enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi);
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171#define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_NHI 0x157d
172#define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_BRIDGE 0x157e
173#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI 0x15bf
174#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE 0x15c0
175#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI 0x15d2
176#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE 0x15d3
177#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI 0x15d9
178#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE 0x15da
179#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI 0x15dc
180#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI 0x15dd
181#define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI 0x15de
182
183#endif
184