1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29#undef DEBUG_DZ
30
31#if defined(CONFIG_SERIAL_DZ_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
32#define SUPPORT_SYSRQ
33#endif
34
35#include <linux/bitops.h>
36#include <linux/compiler.h>
37#include <linux/console.h>
38#include <linux/delay.h>
39#include <linux/errno.h>
40#include <linux/init.h>
41#include <linux/interrupt.h>
42#include <linux/ioport.h>
43#include <linux/kernel.h>
44#include <linux/major.h>
45#include <linux/module.h>
46#include <linux/serial.h>
47#include <linux/serial_core.h>
48#include <linux/sysrq.h>
49#include <linux/tty.h>
50#include <linux/tty_flip.h>
51
52#include <linux/atomic.h>
53#include <asm/bootinfo.h>
54#include <asm/io.h>
55
56#include <asm/dec/interrupts.h>
57#include <asm/dec/kn01.h>
58#include <asm/dec/kn02.h>
59#include <asm/dec/machtype.h>
60#include <asm/dec/prom.h>
61#include <asm/dec/system.h>
62
63#include "dz.h"
64
65
66MODULE_DESCRIPTION("DECstation DZ serial driver");
67MODULE_LICENSE("GPL");
68
69
70static char dz_name[] __initdata = "DECstation DZ serial driver version ";
71static char dz_version[] __initdata = "1.04";
72
73struct dz_port {
74 struct dz_mux *mux;
75 struct uart_port port;
76 unsigned int cflag;
77};
78
79struct dz_mux {
80 struct dz_port dport[DZ_NB_PORT];
81 atomic_t map_guard;
82 atomic_t irq_guard;
83 int initialised;
84};
85
86static struct dz_mux dz_mux;
87
88static inline struct dz_port *to_dport(struct uart_port *uport)
89{
90 return container_of(uport, struct dz_port, port);
91}
92
93
94
95
96
97
98
99
100
101
102static u16 dz_in(struct dz_port *dport, unsigned offset)
103{
104 void __iomem *addr = dport->port.membase + offset;
105
106 return readw(addr);
107}
108
109static void dz_out(struct dz_port *dport, unsigned offset, u16 value)
110{
111 void __iomem *addr = dport->port.membase + offset;
112
113 writew(value, addr);
114}
115
116
117
118
119
120
121
122
123
124
125
126static void dz_stop_tx(struct uart_port *uport)
127{
128 struct dz_port *dport = to_dport(uport);
129 u16 tmp, mask = 1 << dport->port.line;
130
131 tmp = dz_in(dport, DZ_TCR);
132 tmp &= ~mask;
133 dz_out(dport, DZ_TCR, tmp);
134}
135
136static void dz_start_tx(struct uart_port *uport)
137{
138 struct dz_port *dport = to_dport(uport);
139 u16 tmp, mask = 1 << dport->port.line;
140
141 tmp = dz_in(dport, DZ_TCR);
142 tmp |= mask;
143 dz_out(dport, DZ_TCR, tmp);
144}
145
146static void dz_stop_rx(struct uart_port *uport)
147{
148 struct dz_port *dport = to_dport(uport);
149
150 dport->cflag &= ~DZ_RXENAB;
151 dz_out(dport, DZ_LPR, dport->cflag);
152}
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181static inline void dz_receive_chars(struct dz_mux *mux)
182{
183 struct uart_port *uport;
184 struct dz_port *dport = &mux->dport[0];
185 struct uart_icount *icount;
186 int lines_rx[DZ_NB_PORT] = { [0 ... DZ_NB_PORT - 1] = 0 };
187 unsigned char ch, flag;
188 u16 status;
189 int i;
190
191 while ((status = dz_in(dport, DZ_RBUF)) & DZ_DVAL) {
192 dport = &mux->dport[LINE(status)];
193 uport = &dport->port;
194
195 ch = UCHAR(status);
196 flag = TTY_NORMAL;
197
198 icount = &uport->icount;
199 icount->rx++;
200
201 if (unlikely(status & (DZ_OERR | DZ_FERR | DZ_PERR))) {
202
203
204
205
206
207
208
209 if (!ch) {
210 status |= (status & DZ_FERR) >>
211 (ffs(DZ_FERR) - ffs(DZ_BREAK));
212 status &= ~DZ_FERR;
213 }
214
215
216 if (status & DZ_BREAK) {
217 icount->brk++;
218 if (uart_handle_break(uport))
219 continue;
220 } else if (status & DZ_FERR)
221 icount->frame++;
222 else if (status & DZ_PERR)
223 icount->parity++;
224 if (status & DZ_OERR)
225 icount->overrun++;
226
227 status &= uport->read_status_mask;
228 if (status & DZ_BREAK)
229 flag = TTY_BREAK;
230 else if (status & DZ_FERR)
231 flag = TTY_FRAME;
232 else if (status & DZ_PERR)
233 flag = TTY_PARITY;
234
235 }
236
237 if (uart_handle_sysrq_char(uport, ch))
238 continue;
239
240 uart_insert_char(uport, status, DZ_OERR, ch, flag);
241 lines_rx[LINE(status)] = 1;
242 }
243 for (i = 0; i < DZ_NB_PORT; i++)
244 if (lines_rx[i])
245 tty_flip_buffer_push(&mux->dport[i].port.state->port);
246}
247
248
249
250
251
252
253
254
255static inline void dz_transmit_chars(struct dz_mux *mux)
256{
257 struct dz_port *dport = &mux->dport[0];
258 struct circ_buf *xmit;
259 unsigned char tmp;
260 u16 status;
261
262 status = dz_in(dport, DZ_CSR);
263 dport = &mux->dport[LINE(status)];
264 xmit = &dport->port.state->xmit;
265
266 if (dport->port.x_char) {
267 dz_out(dport, DZ_TDR, dport->port.x_char);
268 dport->port.icount.tx++;
269 dport->port.x_char = 0;
270 return;
271 }
272
273 if (uart_circ_empty(xmit) || uart_tx_stopped(&dport->port)) {
274 spin_lock(&dport->port.lock);
275 dz_stop_tx(&dport->port);
276 spin_unlock(&dport->port.lock);
277 return;
278 }
279
280
281
282
283
284 tmp = xmit->buf[xmit->tail];
285 xmit->tail = (xmit->tail + 1) & (DZ_XMIT_SIZE - 1);
286 dz_out(dport, DZ_TDR, tmp);
287 dport->port.icount.tx++;
288
289 if (uart_circ_chars_pending(xmit) < DZ_WAKEUP_CHARS)
290 uart_write_wakeup(&dport->port);
291
292
293 if (uart_circ_empty(xmit)) {
294 spin_lock(&dport->port.lock);
295 dz_stop_tx(&dport->port);
296 spin_unlock(&dport->port.lock);
297 }
298}
299
300
301
302
303
304
305
306
307
308static inline void check_modem_status(struct dz_port *dport)
309{
310
311
312
313
314
315 u16 status;
316
317
318 if (dport->port.line != DZ_MODEM)
319 return;
320
321 status = dz_in(dport, DZ_MSR);
322
323
324 if (status)
325 dport->port.icount.dsr++;
326}
327
328
329
330
331
332
333
334
335
336static irqreturn_t dz_interrupt(int irq, void *dev_id)
337{
338 struct dz_mux *mux = dev_id;
339 struct dz_port *dport = &mux->dport[0];
340 u16 status;
341
342
343 status = dz_in(dport, DZ_CSR);
344
345 if ((status & (DZ_RDONE | DZ_RIE)) == (DZ_RDONE | DZ_RIE))
346 dz_receive_chars(mux);
347
348 if ((status & (DZ_TRDY | DZ_TIE)) == (DZ_TRDY | DZ_TIE))
349 dz_transmit_chars(mux);
350
351 return IRQ_HANDLED;
352}
353
354
355
356
357
358
359
360static unsigned int dz_get_mctrl(struct uart_port *uport)
361{
362
363
364
365 struct dz_port *dport = to_dport(uport);
366 unsigned int mctrl = TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
367
368 if (dport->port.line == DZ_MODEM) {
369 if (dz_in(dport, DZ_MSR) & DZ_MODEM_DSR)
370 mctrl &= ~TIOCM_DSR;
371 }
372
373 return mctrl;
374}
375
376static void dz_set_mctrl(struct uart_port *uport, unsigned int mctrl)
377{
378
379
380
381 struct dz_port *dport = to_dport(uport);
382 u16 tmp;
383
384 if (dport->port.line == DZ_MODEM) {
385 tmp = dz_in(dport, DZ_TCR);
386 if (mctrl & TIOCM_DTR)
387 tmp &= ~DZ_MODEM_DTR;
388 else
389 tmp |= DZ_MODEM_DTR;
390 dz_out(dport, DZ_TCR, tmp);
391 }
392}
393
394
395
396
397
398
399
400
401static int dz_startup(struct uart_port *uport)
402{
403 struct dz_port *dport = to_dport(uport);
404 struct dz_mux *mux = dport->mux;
405 unsigned long flags;
406 int irq_guard;
407 int ret;
408 u16 tmp;
409
410 irq_guard = atomic_add_return(1, &mux->irq_guard);
411 if (irq_guard != 1)
412 return 0;
413
414 ret = request_irq(dport->port.irq, dz_interrupt,
415 IRQF_SHARED, "dz", mux);
416 if (ret) {
417 atomic_add(-1, &mux->irq_guard);
418 printk(KERN_ERR "dz: Cannot get IRQ %d!\n", dport->port.irq);
419 return ret;
420 }
421
422 spin_lock_irqsave(&dport->port.lock, flags);
423
424
425 tmp = dz_in(dport, DZ_CSR);
426 tmp |= DZ_RIE | DZ_TIE;
427 dz_out(dport, DZ_CSR, tmp);
428
429 spin_unlock_irqrestore(&dport->port.lock, flags);
430
431 return 0;
432}
433
434
435
436
437
438
439
440
441
442static void dz_shutdown(struct uart_port *uport)
443{
444 struct dz_port *dport = to_dport(uport);
445 struct dz_mux *mux = dport->mux;
446 unsigned long flags;
447 int irq_guard;
448 u16 tmp;
449
450 spin_lock_irqsave(&dport->port.lock, flags);
451 dz_stop_tx(&dport->port);
452 spin_unlock_irqrestore(&dport->port.lock, flags);
453
454 irq_guard = atomic_add_return(-1, &mux->irq_guard);
455 if (!irq_guard) {
456
457 tmp = dz_in(dport, DZ_CSR);
458 tmp &= ~(DZ_RIE | DZ_TIE);
459 dz_out(dport, DZ_CSR, tmp);
460
461 free_irq(dport->port.irq, mux);
462 }
463}
464
465
466
467
468
469
470
471
472
473
474
475
476
477static unsigned int dz_tx_empty(struct uart_port *uport)
478{
479 struct dz_port *dport = to_dport(uport);
480 unsigned short tmp, mask = 1 << dport->port.line;
481
482 tmp = dz_in(dport, DZ_TCR);
483 tmp &= mask;
484
485 return tmp ? 0 : TIOCSER_TEMT;
486}
487
488static void dz_break_ctl(struct uart_port *uport, int break_state)
489{
490
491
492
493
494 struct dz_port *dport = to_dport(uport);
495 unsigned long flags;
496 unsigned short tmp, mask = 1 << dport->port.line;
497
498 spin_lock_irqsave(&uport->lock, flags);
499 tmp = dz_in(dport, DZ_TCR);
500 if (break_state)
501 tmp |= mask;
502 else
503 tmp &= ~mask;
504 dz_out(dport, DZ_TCR, tmp);
505 spin_unlock_irqrestore(&uport->lock, flags);
506}
507
508static int dz_encode_baud_rate(unsigned int baud)
509{
510 switch (baud) {
511 case 50:
512 return DZ_B50;
513 case 75:
514 return DZ_B75;
515 case 110:
516 return DZ_B110;
517 case 134:
518 return DZ_B134;
519 case 150:
520 return DZ_B150;
521 case 300:
522 return DZ_B300;
523 case 600:
524 return DZ_B600;
525 case 1200:
526 return DZ_B1200;
527 case 1800:
528 return DZ_B1800;
529 case 2000:
530 return DZ_B2000;
531 case 2400:
532 return DZ_B2400;
533 case 3600:
534 return DZ_B3600;
535 case 4800:
536 return DZ_B4800;
537 case 7200:
538 return DZ_B7200;
539 case 9600:
540 return DZ_B9600;
541 default:
542 return -1;
543 }
544}
545
546
547static void dz_reset(struct dz_port *dport)
548{
549 struct dz_mux *mux = dport->mux;
550
551 if (mux->initialised)
552 return;
553
554 dz_out(dport, DZ_CSR, DZ_CLR);
555 while (dz_in(dport, DZ_CSR) & DZ_CLR);
556 iob();
557
558
559 dz_out(dport, DZ_CSR, DZ_MSE);
560
561 mux->initialised = 1;
562}
563
564static void dz_set_termios(struct uart_port *uport, struct ktermios *termios,
565 struct ktermios *old_termios)
566{
567 struct dz_port *dport = to_dport(uport);
568 unsigned long flags;
569 unsigned int cflag, baud;
570 int bflag;
571
572 cflag = dport->port.line;
573
574 switch (termios->c_cflag & CSIZE) {
575 case CS5:
576 cflag |= DZ_CS5;
577 break;
578 case CS6:
579 cflag |= DZ_CS6;
580 break;
581 case CS7:
582 cflag |= DZ_CS7;
583 break;
584 case CS8:
585 default:
586 cflag |= DZ_CS8;
587 }
588
589 if (termios->c_cflag & CSTOPB)
590 cflag |= DZ_CSTOPB;
591 if (termios->c_cflag & PARENB)
592 cflag |= DZ_PARENB;
593 if (termios->c_cflag & PARODD)
594 cflag |= DZ_PARODD;
595
596 baud = uart_get_baud_rate(uport, termios, old_termios, 50, 9600);
597 bflag = dz_encode_baud_rate(baud);
598 if (bflag < 0) {
599 baud = uart_get_baud_rate(uport, old_termios, NULL, 50, 9600);
600 bflag = dz_encode_baud_rate(baud);
601 if (bflag < 0) {
602 baud = 9600;
603 bflag = DZ_B9600;
604 }
605 tty_termios_encode_baud_rate(termios, baud, baud);
606 }
607 cflag |= bflag;
608
609 if (termios->c_cflag & CREAD)
610 cflag |= DZ_RXENAB;
611
612 spin_lock_irqsave(&dport->port.lock, flags);
613
614 uart_update_timeout(uport, termios->c_cflag, baud);
615
616 dz_out(dport, DZ_LPR, cflag);
617 dport->cflag = cflag;
618
619
620 dport->port.read_status_mask = DZ_OERR;
621 if (termios->c_iflag & INPCK)
622 dport->port.read_status_mask |= DZ_FERR | DZ_PERR;
623 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
624 dport->port.read_status_mask |= DZ_BREAK;
625
626
627 uport->ignore_status_mask = 0;
628 if ((termios->c_iflag & (IGNPAR | IGNBRK)) == (IGNPAR | IGNBRK))
629 dport->port.ignore_status_mask |= DZ_OERR;
630 if (termios->c_iflag & IGNPAR)
631 dport->port.ignore_status_mask |= DZ_FERR | DZ_PERR;
632 if (termios->c_iflag & IGNBRK)
633 dport->port.ignore_status_mask |= DZ_BREAK;
634
635 spin_unlock_irqrestore(&dport->port.lock, flags);
636}
637
638
639
640
641
642
643static void dz_pm(struct uart_port *uport, unsigned int state,
644 unsigned int oldstate)
645{
646 struct dz_port *dport = to_dport(uport);
647 unsigned long flags;
648
649 spin_lock_irqsave(&dport->port.lock, flags);
650 if (state < 3)
651 dz_start_tx(&dport->port);
652 else
653 dz_stop_tx(&dport->port);
654 spin_unlock_irqrestore(&dport->port.lock, flags);
655}
656
657
658static const char *dz_type(struct uart_port *uport)
659{
660 return "DZ";
661}
662
663static void dz_release_port(struct uart_port *uport)
664{
665 struct dz_mux *mux = to_dport(uport)->mux;
666 int map_guard;
667
668 iounmap(uport->membase);
669 uport->membase = NULL;
670
671 map_guard = atomic_add_return(-1, &mux->map_guard);
672 if (!map_guard)
673 release_mem_region(uport->mapbase, dec_kn_slot_size);
674}
675
676static int dz_map_port(struct uart_port *uport)
677{
678 if (!uport->membase)
679 uport->membase = ioremap_nocache(uport->mapbase,
680 dec_kn_slot_size);
681 if (!uport->membase) {
682 printk(KERN_ERR "dz: Cannot map MMIO\n");
683 return -ENOMEM;
684 }
685 return 0;
686}
687
688static int dz_request_port(struct uart_port *uport)
689{
690 struct dz_mux *mux = to_dport(uport)->mux;
691 int map_guard;
692 int ret;
693
694 map_guard = atomic_add_return(1, &mux->map_guard);
695 if (map_guard == 1) {
696 if (!request_mem_region(uport->mapbase, dec_kn_slot_size,
697 "dz")) {
698 atomic_add(-1, &mux->map_guard);
699 printk(KERN_ERR
700 "dz: Unable to reserve MMIO resource\n");
701 return -EBUSY;
702 }
703 }
704 ret = dz_map_port(uport);
705 if (ret) {
706 map_guard = atomic_add_return(-1, &mux->map_guard);
707 if (!map_guard)
708 release_mem_region(uport->mapbase, dec_kn_slot_size);
709 return ret;
710 }
711 return 0;
712}
713
714static void dz_config_port(struct uart_port *uport, int flags)
715{
716 struct dz_port *dport = to_dport(uport);
717
718 if (flags & UART_CONFIG_TYPE) {
719 if (dz_request_port(uport))
720 return;
721
722 uport->type = PORT_DZ;
723
724 dz_reset(dport);
725 }
726}
727
728
729
730
731static int dz_verify_port(struct uart_port *uport, struct serial_struct *ser)
732{
733 int ret = 0;
734
735 if (ser->type != PORT_UNKNOWN && ser->type != PORT_DZ)
736 ret = -EINVAL;
737 if (ser->irq != uport->irq)
738 ret = -EINVAL;
739 return ret;
740}
741
742static const struct uart_ops dz_ops = {
743 .tx_empty = dz_tx_empty,
744 .get_mctrl = dz_get_mctrl,
745 .set_mctrl = dz_set_mctrl,
746 .stop_tx = dz_stop_tx,
747 .start_tx = dz_start_tx,
748 .stop_rx = dz_stop_rx,
749 .break_ctl = dz_break_ctl,
750 .startup = dz_startup,
751 .shutdown = dz_shutdown,
752 .set_termios = dz_set_termios,
753 .pm = dz_pm,
754 .type = dz_type,
755 .release_port = dz_release_port,
756 .request_port = dz_request_port,
757 .config_port = dz_config_port,
758 .verify_port = dz_verify_port,
759};
760
761static void __init dz_init_ports(void)
762{
763 static int first = 1;
764 unsigned long base;
765 int line;
766
767 if (!first)
768 return;
769 first = 0;
770
771 if (mips_machtype == MACH_DS23100 || mips_machtype == MACH_DS5100)
772 base = dec_kn_slot_base + KN01_DZ11;
773 else
774 base = dec_kn_slot_base + KN02_DZ11;
775
776 for (line = 0; line < DZ_NB_PORT; line++) {
777 struct dz_port *dport = &dz_mux.dport[line];
778 struct uart_port *uport = &dport->port;
779
780 dport->mux = &dz_mux;
781
782 uport->irq = dec_interrupt[DEC_IRQ_DZ11];
783 uport->fifosize = 1;
784 uport->iotype = UPIO_MEM;
785 uport->flags = UPF_BOOT_AUTOCONF;
786 uport->ops = &dz_ops;
787 uport->line = line;
788 uport->mapbase = base;
789 }
790}
791
792#ifdef CONFIG_SERIAL_DZ_CONSOLE
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807static void dz_console_putchar(struct uart_port *uport, int ch)
808{
809 struct dz_port *dport = to_dport(uport);
810 unsigned long flags;
811 unsigned short csr, tcr, trdy, mask;
812 int loops = 10000;
813
814 spin_lock_irqsave(&dport->port.lock, flags);
815 csr = dz_in(dport, DZ_CSR);
816 dz_out(dport, DZ_CSR, csr & ~DZ_TIE);
817 tcr = dz_in(dport, DZ_TCR);
818 tcr |= 1 << dport->port.line;
819 mask = tcr;
820 dz_out(dport, DZ_TCR, mask);
821 iob();
822 spin_unlock_irqrestore(&dport->port.lock, flags);
823
824 do {
825 trdy = dz_in(dport, DZ_CSR);
826 if (!(trdy & DZ_TRDY))
827 continue;
828 trdy = (trdy & DZ_TLINE) >> 8;
829 if (trdy == dport->port.line)
830 break;
831 mask &= ~(1 << trdy);
832 dz_out(dport, DZ_TCR, mask);
833 iob();
834 udelay(2);
835 } while (--loops);
836
837 if (loops)
838 dz_out(dport, DZ_TDR, ch);
839
840 dz_out(dport, DZ_TCR, tcr);
841 dz_out(dport, DZ_CSR, csr);
842}
843
844
845
846
847
848
849
850
851
852static void dz_console_print(struct console *co,
853 const char *str,
854 unsigned int count)
855{
856 struct dz_port *dport = &dz_mux.dport[co->index];
857#ifdef DEBUG_DZ
858 prom_printf((char *) str);
859#endif
860 uart_console_write(&dport->port, str, count, dz_console_putchar);
861}
862
863static int __init dz_console_setup(struct console *co, char *options)
864{
865 struct dz_port *dport = &dz_mux.dport[co->index];
866 struct uart_port *uport = &dport->port;
867 int baud = 9600;
868 int bits = 8;
869 int parity = 'n';
870 int flow = 'n';
871 int ret;
872
873 ret = dz_map_port(uport);
874 if (ret)
875 return ret;
876
877 spin_lock_init(&dport->port.lock);
878
879 dz_reset(dport);
880 dz_pm(uport, 0, -1);
881
882 if (options)
883 uart_parse_options(options, &baud, &parity, &bits, &flow);
884
885 return uart_set_options(&dport->port, co, baud, parity, bits, flow);
886}
887
888static struct uart_driver dz_reg;
889static struct console dz_console = {
890 .name = "ttyS",
891 .write = dz_console_print,
892 .device = uart_console_device,
893 .setup = dz_console_setup,
894 .flags = CON_PRINTBUFFER,
895 .index = -1,
896 .data = &dz_reg,
897};
898
899static int __init dz_serial_console_init(void)
900{
901 if (!IOASIC) {
902 dz_init_ports();
903 register_console(&dz_console);
904 return 0;
905 } else
906 return -ENXIO;
907}
908
909console_initcall(dz_serial_console_init);
910
911#define SERIAL_DZ_CONSOLE &dz_console
912#else
913#define SERIAL_DZ_CONSOLE NULL
914#endif
915
916static struct uart_driver dz_reg = {
917 .owner = THIS_MODULE,
918 .driver_name = "serial",
919 .dev_name = "ttyS",
920 .major = TTY_MAJOR,
921 .minor = 64,
922 .nr = DZ_NB_PORT,
923 .cons = SERIAL_DZ_CONSOLE,
924};
925
926static int __init dz_init(void)
927{
928 int ret, i;
929
930 if (IOASIC)
931 return -ENXIO;
932
933 printk("%s%s\n", dz_name, dz_version);
934
935 dz_init_ports();
936
937 ret = uart_register_driver(&dz_reg);
938 if (ret)
939 return ret;
940
941 for (i = 0; i < DZ_NB_PORT; i++)
942 uart_add_one_port(&dz_reg, &dz_mux.dport[i].port);
943
944 return 0;
945}
946
947module_init(dz_init);
948