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16#include <linux/bitops.h>
17#include <linux/clk.h>
18#include <linux/delay.h>
19#include <linux/device.h>
20#include <linux/gpio/driver.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/regmap.h>
25#include <linux/serial_core.h>
26#include <linux/serial.h>
27#include <linux/tty.h>
28#include <linux/tty_flip.h>
29#include <linux/spi/spi.h>
30#include <linux/uaccess.h>
31
32#define MAX310X_NAME "max310x"
33#define MAX310X_MAJOR 204
34#define MAX310X_MINOR 209
35#define MAX310X_UART_NRMAX 16
36
37
38#define MAX310X_RHR_REG (0x00)
39#define MAX310X_THR_REG (0x00)
40#define MAX310X_IRQEN_REG (0x01)
41#define MAX310X_IRQSTS_REG (0x02)
42#define MAX310X_LSR_IRQEN_REG (0x03)
43#define MAX310X_LSR_IRQSTS_REG (0x04)
44#define MAX310X_REG_05 (0x05)
45#define MAX310X_SPCHR_IRQEN_REG MAX310X_REG_05
46#define MAX310X_SPCHR_IRQSTS_REG (0x06)
47#define MAX310X_STS_IRQEN_REG (0x07)
48#define MAX310X_STS_IRQSTS_REG (0x08)
49#define MAX310X_MODE1_REG (0x09)
50#define MAX310X_MODE2_REG (0x0a)
51#define MAX310X_LCR_REG (0x0b)
52#define MAX310X_RXTO_REG (0x0c)
53#define MAX310X_HDPIXDELAY_REG (0x0d)
54#define MAX310X_IRDA_REG (0x0e)
55#define MAX310X_FLOWLVL_REG (0x0f)
56#define MAX310X_FIFOTRIGLVL_REG (0x10)
57#define MAX310X_TXFIFOLVL_REG (0x11)
58#define MAX310X_RXFIFOLVL_REG (0x12)
59#define MAX310X_FLOWCTRL_REG (0x13)
60#define MAX310X_XON1_REG (0x14)
61#define MAX310X_XON2_REG (0x15)
62#define MAX310X_XOFF1_REG (0x16)
63#define MAX310X_XOFF2_REG (0x17)
64#define MAX310X_GPIOCFG_REG (0x18)
65#define MAX310X_GPIODATA_REG (0x19)
66#define MAX310X_PLLCFG_REG (0x1a)
67#define MAX310X_BRGCFG_REG (0x1b)
68#define MAX310X_BRGDIVLSB_REG (0x1c)
69#define MAX310X_BRGDIVMSB_REG (0x1d)
70#define MAX310X_CLKSRC_REG (0x1e)
71#define MAX310X_REG_1F (0x1f)
72
73#define MAX310X_REVID_REG MAX310X_REG_1F
74
75#define MAX310X_GLOBALIRQ_REG MAX310X_REG_1F
76#define MAX310X_GLOBALCMD_REG MAX310X_REG_1F
77
78
79#define MAX310X_REVID_EXTREG MAX310X_REG_05
80
81
82#define MAX310X_IRQ_LSR_BIT (1 << 0)
83#define MAX310X_IRQ_SPCHR_BIT (1 << 1)
84#define MAX310X_IRQ_STS_BIT (1 << 2)
85#define MAX310X_IRQ_RXFIFO_BIT (1 << 3)
86#define MAX310X_IRQ_TXFIFO_BIT (1 << 4)
87#define MAX310X_IRQ_TXEMPTY_BIT (1 << 5)
88#define MAX310X_IRQ_RXEMPTY_BIT (1 << 6)
89#define MAX310X_IRQ_CTS_BIT (1 << 7)
90
91
92#define MAX310X_LSR_RXTO_BIT (1 << 0)
93#define MAX310X_LSR_RXOVR_BIT (1 << 1)
94#define MAX310X_LSR_RXPAR_BIT (1 << 2)
95#define MAX310X_LSR_FRERR_BIT (1 << 3)
96#define MAX310X_LSR_RXBRK_BIT (1 << 4)
97#define MAX310X_LSR_RXNOISE_BIT (1 << 5)
98#define MAX310X_LSR_CTS_BIT (1 << 7)
99
100
101#define MAX310X_SPCHR_XON1_BIT (1 << 0)
102#define MAX310X_SPCHR_XON2_BIT (1 << 1)
103#define MAX310X_SPCHR_XOFF1_BIT (1 << 2)
104#define MAX310X_SPCHR_XOFF2_BIT (1 << 3)
105#define MAX310X_SPCHR_BREAK_BIT (1 << 4)
106#define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5)
107
108
109#define MAX310X_STS_GPIO0_BIT (1 << 0)
110#define MAX310X_STS_GPIO1_BIT (1 << 1)
111#define MAX310X_STS_GPIO2_BIT (1 << 2)
112#define MAX310X_STS_GPIO3_BIT (1 << 3)
113#define MAX310X_STS_CLKREADY_BIT (1 << 5)
114#define MAX310X_STS_SLEEP_BIT (1 << 6)
115
116
117#define MAX310X_MODE1_RXDIS_BIT (1 << 0)
118#define MAX310X_MODE1_TXDIS_BIT (1 << 1)
119#define MAX310X_MODE1_TXHIZ_BIT (1 << 2)
120#define MAX310X_MODE1_RTSHIZ_BIT (1 << 3)
121#define MAX310X_MODE1_TRNSCVCTRL_BIT (1 << 4)
122#define MAX310X_MODE1_FORCESLEEP_BIT (1 << 5)
123#define MAX310X_MODE1_AUTOSLEEP_BIT (1 << 6)
124#define MAX310X_MODE1_IRQSEL_BIT (1 << 7)
125
126
127#define MAX310X_MODE2_RST_BIT (1 << 0)
128#define MAX310X_MODE2_FIFORST_BIT (1 << 1)
129#define MAX310X_MODE2_RXTRIGINV_BIT (1 << 2)
130#define MAX310X_MODE2_RXEMPTINV_BIT (1 << 3)
131#define MAX310X_MODE2_SPCHR_BIT (1 << 4)
132#define MAX310X_MODE2_LOOPBACK_BIT (1 << 5)
133#define MAX310X_MODE2_MULTIDROP_BIT (1 << 6)
134#define MAX310X_MODE2_ECHOSUPR_BIT (1 << 7)
135
136
137#define MAX310X_LCR_LENGTH0_BIT (1 << 0)
138#define MAX310X_LCR_LENGTH1_BIT (1 << 1)
139
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145
146#define MAX310X_LCR_STOPLEN_BIT (1 << 2)
147
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153
154#define MAX310X_LCR_PARITY_BIT (1 << 3)
155#define MAX310X_LCR_EVENPARITY_BIT (1 << 4)
156#define MAX310X_LCR_FORCEPARITY_BIT (1 << 5)
157#define MAX310X_LCR_TXBREAK_BIT (1 << 6)
158#define MAX310X_LCR_RTS_BIT (1 << 7)
159
160
161#define MAX310X_IRDA_IRDAEN_BIT (1 << 0)
162#define MAX310X_IRDA_SIR_BIT (1 << 1)
163
164
165#define MAX310X_FLOWLVL_HALT_MASK (0x000f)
166#define MAX310X_FLOWLVL_RES_MASK (0x00f0)
167#define MAX310X_FLOWLVL_HALT(words) ((words / 8) & 0x0f)
168#define MAX310X_FLOWLVL_RES(words) (((words / 8) & 0x0f) << 4)
169
170
171#define MAX310X_FIFOTRIGLVL_TX_MASK (0x0f)
172#define MAX310X_FIFOTRIGLVL_RX_MASK (0xf0)
173#define MAX310X_FIFOTRIGLVL_TX(words) ((words / 8) & 0x0f)
174#define MAX310X_FIFOTRIGLVL_RX(words) (((words / 8) & 0x0f) << 4)
175
176
177#define MAX310X_FLOWCTRL_AUTORTS_BIT (1 << 0)
178#define MAX310X_FLOWCTRL_AUTOCTS_BIT (1 << 1)
179#define MAX310X_FLOWCTRL_GPIADDR_BIT (1 << 2)
180
181
182
183#define MAX310X_FLOWCTRL_SWFLOWEN_BIT (1 << 3)
184#define MAX310X_FLOWCTRL_SWFLOW0_BIT (1 << 4)
185#define MAX310X_FLOWCTRL_SWFLOW1_BIT (1 << 5)
186
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201
202
203#define MAX310X_FLOWCTRL_SWFLOW2_BIT (1 << 6)
204#define MAX310X_FLOWCTRL_SWFLOW3_BIT (1 << 7)
205
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217
218
219#define MAX310X_PLLCFG_PREDIV_MASK (0x3f)
220#define MAX310X_PLLCFG_PLLFACTOR_MASK (0xc0)
221
222
223#define MAX310X_BRGCFG_2XMODE_BIT (1 << 4)
224#define MAX310X_BRGCFG_4XMODE_BIT (1 << 5)
225
226
227#define MAX310X_CLKSRC_CRYST_BIT (1 << 1)
228#define MAX310X_CLKSRC_PLL_BIT (1 << 2)
229#define MAX310X_CLKSRC_PLLBYP_BIT (1 << 3)
230#define MAX310X_CLKSRC_EXTCLK_BIT (1 << 4)
231#define MAX310X_CLKSRC_CLK2RTS_BIT (1 << 7)
232
233
234#define MAX310X_EXTREG_ENBL (0xce)
235#define MAX310X_EXTREG_DSBL (0xcd)
236
237
238#define MAX310X_FIFO_SIZE (128)
239#define MAX310x_REV_MASK (0xf8)
240
241
242#define MAX3107_REV_ID (0xa0)
243
244
245#define MAX3109_REV_ID (0xc0)
246
247
248#define MAX14830_BRGCFG_CLKDIS_BIT (1 << 6)
249#define MAX14830_REV_ID (0xb0)
250
251struct max310x_devtype {
252 char name[9];
253 int nr;
254 int (*detect)(struct device *);
255 void (*power)(struct uart_port *, int);
256};
257
258struct max310x_one {
259 struct uart_port port;
260 struct work_struct tx_work;
261 struct work_struct md_work;
262 struct work_struct rs_work;
263};
264
265struct max310x_port {
266 struct max310x_devtype *devtype;
267 struct regmap *regmap;
268 struct mutex mutex;
269 struct clk *clk;
270#ifdef CONFIG_GPIOLIB
271 struct gpio_chip gpio;
272#endif
273 struct max310x_one p[0];
274};
275
276static struct uart_driver max310x_uart = {
277 .owner = THIS_MODULE,
278 .driver_name = MAX310X_NAME,
279 .dev_name = "ttyMAX",
280 .major = MAX310X_MAJOR,
281 .minor = MAX310X_MINOR,
282 .nr = MAX310X_UART_NRMAX,
283};
284
285static DECLARE_BITMAP(max310x_lines, MAX310X_UART_NRMAX);
286
287static u8 max310x_port_read(struct uart_port *port, u8 reg)
288{
289 struct max310x_port *s = dev_get_drvdata(port->dev);
290 unsigned int val = 0;
291
292 regmap_read(s->regmap, port->iobase + reg, &val);
293
294 return val;
295}
296
297static void max310x_port_write(struct uart_port *port, u8 reg, u8 val)
298{
299 struct max310x_port *s = dev_get_drvdata(port->dev);
300
301 regmap_write(s->regmap, port->iobase + reg, val);
302}
303
304static void max310x_port_update(struct uart_port *port, u8 reg, u8 mask, u8 val)
305{
306 struct max310x_port *s = dev_get_drvdata(port->dev);
307
308 regmap_update_bits(s->regmap, port->iobase + reg, mask, val);
309}
310
311static int max3107_detect(struct device *dev)
312{
313 struct max310x_port *s = dev_get_drvdata(dev);
314 unsigned int val = 0;
315 int ret;
316
317 ret = regmap_read(s->regmap, MAX310X_REVID_REG, &val);
318 if (ret)
319 return ret;
320
321 if (((val & MAX310x_REV_MASK) != MAX3107_REV_ID)) {
322 dev_err(dev,
323 "%s ID 0x%02x does not match\n", s->devtype->name, val);
324 return -ENODEV;
325 }
326
327 return 0;
328}
329
330static int max3108_detect(struct device *dev)
331{
332 struct max310x_port *s = dev_get_drvdata(dev);
333 unsigned int val = 0;
334 int ret;
335
336
337
338
339 ret = regmap_read(s->regmap, MAX310X_CLKSRC_REG, &val);
340 if (ret)
341 return ret;
342
343 if (val != (MAX310X_CLKSRC_EXTCLK_BIT | MAX310X_CLKSRC_PLLBYP_BIT)) {
344 dev_err(dev, "%s not present\n", s->devtype->name);
345 return -ENODEV;
346 }
347
348 return 0;
349}
350
351static int max3109_detect(struct device *dev)
352{
353 struct max310x_port *s = dev_get_drvdata(dev);
354 unsigned int val = 0;
355 int ret;
356
357 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG,
358 MAX310X_EXTREG_ENBL);
359 if (ret)
360 return ret;
361
362 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val);
363 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL);
364 if (((val & MAX310x_REV_MASK) != MAX3109_REV_ID)) {
365 dev_err(dev,
366 "%s ID 0x%02x does not match\n", s->devtype->name, val);
367 return -ENODEV;
368 }
369
370 return 0;
371}
372
373static void max310x_power(struct uart_port *port, int on)
374{
375 max310x_port_update(port, MAX310X_MODE1_REG,
376 MAX310X_MODE1_FORCESLEEP_BIT,
377 on ? 0 : MAX310X_MODE1_FORCESLEEP_BIT);
378 if (on)
379 msleep(50);
380}
381
382static int max14830_detect(struct device *dev)
383{
384 struct max310x_port *s = dev_get_drvdata(dev);
385 unsigned int val = 0;
386 int ret;
387
388 ret = regmap_write(s->regmap, MAX310X_GLOBALCMD_REG,
389 MAX310X_EXTREG_ENBL);
390 if (ret)
391 return ret;
392
393 regmap_read(s->regmap, MAX310X_REVID_EXTREG, &val);
394 regmap_write(s->regmap, MAX310X_GLOBALCMD_REG, MAX310X_EXTREG_DSBL);
395 if (((val & MAX310x_REV_MASK) != MAX14830_REV_ID)) {
396 dev_err(dev,
397 "%s ID 0x%02x does not match\n", s->devtype->name, val);
398 return -ENODEV;
399 }
400
401 return 0;
402}
403
404static void max14830_power(struct uart_port *port, int on)
405{
406 max310x_port_update(port, MAX310X_BRGCFG_REG,
407 MAX14830_BRGCFG_CLKDIS_BIT,
408 on ? 0 : MAX14830_BRGCFG_CLKDIS_BIT);
409 if (on)
410 msleep(50);
411}
412
413static const struct max310x_devtype max3107_devtype = {
414 .name = "MAX3107",
415 .nr = 1,
416 .detect = max3107_detect,
417 .power = max310x_power,
418};
419
420static const struct max310x_devtype max3108_devtype = {
421 .name = "MAX3108",
422 .nr = 1,
423 .detect = max3108_detect,
424 .power = max310x_power,
425};
426
427static const struct max310x_devtype max3109_devtype = {
428 .name = "MAX3109",
429 .nr = 2,
430 .detect = max3109_detect,
431 .power = max310x_power,
432};
433
434static const struct max310x_devtype max14830_devtype = {
435 .name = "MAX14830",
436 .nr = 4,
437 .detect = max14830_detect,
438 .power = max14830_power,
439};
440
441static bool max310x_reg_writeable(struct device *dev, unsigned int reg)
442{
443 switch (reg & 0x1f) {
444 case MAX310X_IRQSTS_REG:
445 case MAX310X_LSR_IRQSTS_REG:
446 case MAX310X_SPCHR_IRQSTS_REG:
447 case MAX310X_STS_IRQSTS_REG:
448 case MAX310X_TXFIFOLVL_REG:
449 case MAX310X_RXFIFOLVL_REG:
450 return false;
451 default:
452 break;
453 }
454
455 return true;
456}
457
458static bool max310x_reg_volatile(struct device *dev, unsigned int reg)
459{
460 switch (reg & 0x1f) {
461 case MAX310X_RHR_REG:
462 case MAX310X_IRQSTS_REG:
463 case MAX310X_LSR_IRQSTS_REG:
464 case MAX310X_SPCHR_IRQSTS_REG:
465 case MAX310X_STS_IRQSTS_REG:
466 case MAX310X_TXFIFOLVL_REG:
467 case MAX310X_RXFIFOLVL_REG:
468 case MAX310X_GPIODATA_REG:
469 case MAX310X_BRGDIVLSB_REG:
470 case MAX310X_REG_05:
471 case MAX310X_REG_1F:
472 return true;
473 default:
474 break;
475 }
476
477 return false;
478}
479
480static bool max310x_reg_precious(struct device *dev, unsigned int reg)
481{
482 switch (reg & 0x1f) {
483 case MAX310X_RHR_REG:
484 case MAX310X_IRQSTS_REG:
485 case MAX310X_SPCHR_IRQSTS_REG:
486 case MAX310X_STS_IRQSTS_REG:
487 return true;
488 default:
489 break;
490 }
491
492 return false;
493}
494
495static int max310x_set_baud(struct uart_port *port, int baud)
496{
497 unsigned int mode = 0, clk = port->uartclk, div = clk / baud;
498
499
500 if (div < 16)
501 div = 16;
502
503 if (clk % baud && (div / 16) < 0x8000) {
504
505 mode = MAX310X_BRGCFG_2XMODE_BIT;
506 clk = port->uartclk * 2;
507 div = clk / baud;
508
509 if (clk % baud && (div / 16) < 0x8000) {
510
511 mode = MAX310X_BRGCFG_4XMODE_BIT;
512 clk = port->uartclk * 4;
513 div = clk / baud;
514 }
515 }
516
517 max310x_port_write(port, MAX310X_BRGDIVMSB_REG, (div / 16) >> 8);
518 max310x_port_write(port, MAX310X_BRGDIVLSB_REG, div / 16);
519 max310x_port_write(port, MAX310X_BRGCFG_REG, (div % 16) | mode);
520
521 return DIV_ROUND_CLOSEST(clk, div);
522}
523
524static int max310x_update_best_err(unsigned long f, long *besterr)
525{
526
527 long err = f % (115200 * 16);
528
529 if ((*besterr < 0) || (*besterr > err)) {
530 *besterr = err;
531 return 0;
532 }
533
534 return 1;
535}
536
537static int max310x_set_ref_clk(struct max310x_port *s, unsigned long freq,
538 bool xtal)
539{
540 unsigned int div, clksrc, pllcfg = 0;
541 long besterr = -1;
542 unsigned long fdiv, fmul, bestfreq = freq;
543
544
545 max310x_update_best_err(freq, &besterr);
546
547
548 for (div = 1; (div <= 63) && besterr; div++) {
549 fdiv = DIV_ROUND_CLOSEST(freq, div);
550
551
552 fmul = fdiv * 6;
553 if ((fdiv >= 500000) && (fdiv <= 800000))
554 if (!max310x_update_best_err(fmul, &besterr)) {
555 pllcfg = (0 << 6) | div;
556 bestfreq = fmul;
557 }
558
559 fmul = fdiv * 48;
560 if ((fdiv >= 850000) && (fdiv <= 1200000))
561 if (!max310x_update_best_err(fmul, &besterr)) {
562 pllcfg = (1 << 6) | div;
563 bestfreq = fmul;
564 }
565
566 fmul = fdiv * 96;
567 if ((fdiv >= 425000) && (fdiv <= 1000000))
568 if (!max310x_update_best_err(fmul, &besterr)) {
569 pllcfg = (2 << 6) | div;
570 bestfreq = fmul;
571 }
572
573 fmul = fdiv * 144;
574 if ((fdiv >= 390000) && (fdiv <= 667000))
575 if (!max310x_update_best_err(fmul, &besterr)) {
576 pllcfg = (3 << 6) | div;
577 bestfreq = fmul;
578 }
579 }
580
581
582 clksrc = xtal ? MAX310X_CLKSRC_CRYST_BIT : MAX310X_CLKSRC_EXTCLK_BIT;
583
584
585 if (pllcfg) {
586 clksrc |= MAX310X_CLKSRC_PLL_BIT;
587 regmap_write(s->regmap, MAX310X_PLLCFG_REG, pllcfg);
588 } else
589 clksrc |= MAX310X_CLKSRC_PLLBYP_BIT;
590
591 regmap_write(s->regmap, MAX310X_CLKSRC_REG, clksrc);
592
593
594 if (pllcfg && xtal)
595 msleep(10);
596
597 return (int)bestfreq;
598}
599
600static void max310x_handle_rx(struct uart_port *port, unsigned int rxlen)
601{
602 unsigned int sts, ch, flag;
603
604 if (unlikely(rxlen >= port->fifosize)) {
605 dev_warn_ratelimited(port->dev, "Possible RX FIFO overrun\n");
606 port->icount.buf_overrun++;
607
608 rxlen = port->fifosize;
609 }
610
611 while (rxlen--) {
612 ch = max310x_port_read(port, MAX310X_RHR_REG);
613 sts = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
614
615 sts &= MAX310X_LSR_RXPAR_BIT | MAX310X_LSR_FRERR_BIT |
616 MAX310X_LSR_RXOVR_BIT | MAX310X_LSR_RXBRK_BIT;
617
618 port->icount.rx++;
619 flag = TTY_NORMAL;
620
621 if (unlikely(sts)) {
622 if (sts & MAX310X_LSR_RXBRK_BIT) {
623 port->icount.brk++;
624 if (uart_handle_break(port))
625 continue;
626 } else if (sts & MAX310X_LSR_RXPAR_BIT)
627 port->icount.parity++;
628 else if (sts & MAX310X_LSR_FRERR_BIT)
629 port->icount.frame++;
630 else if (sts & MAX310X_LSR_RXOVR_BIT)
631 port->icount.overrun++;
632
633 sts &= port->read_status_mask;
634 if (sts & MAX310X_LSR_RXBRK_BIT)
635 flag = TTY_BREAK;
636 else if (sts & MAX310X_LSR_RXPAR_BIT)
637 flag = TTY_PARITY;
638 else if (sts & MAX310X_LSR_FRERR_BIT)
639 flag = TTY_FRAME;
640 else if (sts & MAX310X_LSR_RXOVR_BIT)
641 flag = TTY_OVERRUN;
642 }
643
644 if (uart_handle_sysrq_char(port, ch))
645 continue;
646
647 if (sts & port->ignore_status_mask)
648 continue;
649
650 uart_insert_char(port, sts, MAX310X_LSR_RXOVR_BIT, ch, flag);
651 }
652
653 tty_flip_buffer_push(&port->state->port);
654}
655
656static void max310x_handle_tx(struct uart_port *port)
657{
658 struct circ_buf *xmit = &port->state->xmit;
659 unsigned int txlen, to_send;
660
661 if (unlikely(port->x_char)) {
662 max310x_port_write(port, MAX310X_THR_REG, port->x_char);
663 port->icount.tx++;
664 port->x_char = 0;
665 return;
666 }
667
668 if (uart_circ_empty(xmit) || uart_tx_stopped(port))
669 return;
670
671
672 to_send = uart_circ_chars_pending(xmit);
673 if (likely(to_send)) {
674
675 txlen = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
676 txlen = port->fifosize - txlen;
677 to_send = (to_send > txlen) ? txlen : to_send;
678
679
680 port->icount.tx += to_send;
681 while (to_send--) {
682 max310x_port_write(port, MAX310X_THR_REG,
683 xmit->buf[xmit->tail]);
684 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
685 }
686 }
687
688 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
689 uart_write_wakeup(port);
690}
691
692static void max310x_port_irq(struct max310x_port *s, int portno)
693{
694 struct uart_port *port = &s->p[portno].port;
695
696 do {
697 unsigned int ists, lsr, rxlen;
698
699
700 ists = max310x_port_read(port, MAX310X_IRQSTS_REG);
701 rxlen = max310x_port_read(port, MAX310X_RXFIFOLVL_REG);
702 if (!ists && !rxlen)
703 break;
704
705 if (ists & MAX310X_IRQ_CTS_BIT) {
706 lsr = max310x_port_read(port, MAX310X_LSR_IRQSTS_REG);
707 uart_handle_cts_change(port,
708 !!(lsr & MAX310X_LSR_CTS_BIT));
709 }
710 if (rxlen)
711 max310x_handle_rx(port, rxlen);
712 if (ists & MAX310X_IRQ_TXEMPTY_BIT) {
713 mutex_lock(&s->mutex);
714 max310x_handle_tx(port);
715 mutex_unlock(&s->mutex);
716 }
717 } while (1);
718}
719
720static irqreturn_t max310x_ist(int irq, void *dev_id)
721{
722 struct max310x_port *s = (struct max310x_port *)dev_id;
723
724 if (s->devtype->nr > 1) {
725 do {
726 unsigned int val = ~0;
727
728 WARN_ON_ONCE(regmap_read(s->regmap,
729 MAX310X_GLOBALIRQ_REG, &val));
730 val = ((1 << s->devtype->nr) - 1) & ~val;
731 if (!val)
732 break;
733 max310x_port_irq(s, fls(val) - 1);
734 } while (1);
735 } else
736 max310x_port_irq(s, 0);
737
738 return IRQ_HANDLED;
739}
740
741static void max310x_wq_proc(struct work_struct *ws)
742{
743 struct max310x_one *one = container_of(ws, struct max310x_one, tx_work);
744 struct max310x_port *s = dev_get_drvdata(one->port.dev);
745
746 mutex_lock(&s->mutex);
747 max310x_handle_tx(&one->port);
748 mutex_unlock(&s->mutex);
749}
750
751static void max310x_start_tx(struct uart_port *port)
752{
753 struct max310x_one *one = container_of(port, struct max310x_one, port);
754
755 if (!work_pending(&one->tx_work))
756 schedule_work(&one->tx_work);
757}
758
759static unsigned int max310x_tx_empty(struct uart_port *port)
760{
761 unsigned int lvl, sts;
762
763 lvl = max310x_port_read(port, MAX310X_TXFIFOLVL_REG);
764 sts = max310x_port_read(port, MAX310X_IRQSTS_REG);
765
766 return ((sts & MAX310X_IRQ_TXEMPTY_BIT) && !lvl) ? TIOCSER_TEMT : 0;
767}
768
769static unsigned int max310x_get_mctrl(struct uart_port *port)
770{
771
772
773
774 return TIOCM_DSR | TIOCM_CAR;
775}
776
777static void max310x_md_proc(struct work_struct *ws)
778{
779 struct max310x_one *one = container_of(ws, struct max310x_one, md_work);
780
781 max310x_port_update(&one->port, MAX310X_MODE2_REG,
782 MAX310X_MODE2_LOOPBACK_BIT,
783 (one->port.mctrl & TIOCM_LOOP) ?
784 MAX310X_MODE2_LOOPBACK_BIT : 0);
785}
786
787static void max310x_set_mctrl(struct uart_port *port, unsigned int mctrl)
788{
789 struct max310x_one *one = container_of(port, struct max310x_one, port);
790
791 schedule_work(&one->md_work);
792}
793
794static void max310x_break_ctl(struct uart_port *port, int break_state)
795{
796 max310x_port_update(port, MAX310X_LCR_REG,
797 MAX310X_LCR_TXBREAK_BIT,
798 break_state ? MAX310X_LCR_TXBREAK_BIT : 0);
799}
800
801static void max310x_set_termios(struct uart_port *port,
802 struct ktermios *termios,
803 struct ktermios *old)
804{
805 unsigned int lcr = 0, flow = 0;
806 int baud;
807
808
809 termios->c_cflag &= ~CMSPAR;
810
811
812 switch (termios->c_cflag & CSIZE) {
813 case CS5:
814 break;
815 case CS6:
816 lcr = MAX310X_LCR_LENGTH0_BIT;
817 break;
818 case CS7:
819 lcr = MAX310X_LCR_LENGTH1_BIT;
820 break;
821 case CS8:
822 default:
823 lcr = MAX310X_LCR_LENGTH1_BIT | MAX310X_LCR_LENGTH0_BIT;
824 break;
825 }
826
827
828 if (termios->c_cflag & PARENB) {
829 lcr |= MAX310X_LCR_PARITY_BIT;
830 if (!(termios->c_cflag & PARODD))
831 lcr |= MAX310X_LCR_EVENPARITY_BIT;
832 }
833
834
835 if (termios->c_cflag & CSTOPB)
836 lcr |= MAX310X_LCR_STOPLEN_BIT;
837
838
839 max310x_port_write(port, MAX310X_LCR_REG, lcr);
840
841
842 port->read_status_mask = MAX310X_LSR_RXOVR_BIT;
843 if (termios->c_iflag & INPCK)
844 port->read_status_mask |= MAX310X_LSR_RXPAR_BIT |
845 MAX310X_LSR_FRERR_BIT;
846 if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
847 port->read_status_mask |= MAX310X_LSR_RXBRK_BIT;
848
849
850 port->ignore_status_mask = 0;
851 if (termios->c_iflag & IGNBRK)
852 port->ignore_status_mask |= MAX310X_LSR_RXBRK_BIT;
853 if (!(termios->c_cflag & CREAD))
854 port->ignore_status_mask |= MAX310X_LSR_RXPAR_BIT |
855 MAX310X_LSR_RXOVR_BIT |
856 MAX310X_LSR_FRERR_BIT |
857 MAX310X_LSR_RXBRK_BIT;
858
859
860 max310x_port_write(port, MAX310X_XON1_REG, termios->c_cc[VSTART]);
861 max310x_port_write(port, MAX310X_XOFF1_REG, termios->c_cc[VSTOP]);
862 if (termios->c_cflag & CRTSCTS)
863 flow |= MAX310X_FLOWCTRL_AUTOCTS_BIT |
864 MAX310X_FLOWCTRL_AUTORTS_BIT;
865 if (termios->c_iflag & IXON)
866 flow |= MAX310X_FLOWCTRL_SWFLOW3_BIT |
867 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
868 if (termios->c_iflag & IXOFF)
869 flow |= MAX310X_FLOWCTRL_SWFLOW1_BIT |
870 MAX310X_FLOWCTRL_SWFLOWEN_BIT;
871 max310x_port_write(port, MAX310X_FLOWCTRL_REG, flow);
872
873
874 baud = uart_get_baud_rate(port, termios, old,
875 port->uartclk / 16 / 0xffff,
876 port->uartclk / 4);
877
878
879 baud = max310x_set_baud(port, baud);
880
881
882 uart_update_timeout(port, termios->c_cflag, baud);
883}
884
885static void max310x_rs_proc(struct work_struct *ws)
886{
887 struct max310x_one *one = container_of(ws, struct max310x_one, rs_work);
888 unsigned int val;
889
890 val = (one->port.rs485.delay_rts_before_send << 4) |
891 one->port.rs485.delay_rts_after_send;
892 max310x_port_write(&one->port, MAX310X_HDPIXDELAY_REG, val);
893
894 if (one->port.rs485.flags & SER_RS485_ENABLED) {
895 max310x_port_update(&one->port, MAX310X_MODE1_REG,
896 MAX310X_MODE1_TRNSCVCTRL_BIT,
897 MAX310X_MODE1_TRNSCVCTRL_BIT);
898 max310x_port_update(&one->port, MAX310X_MODE2_REG,
899 MAX310X_MODE2_ECHOSUPR_BIT,
900 MAX310X_MODE2_ECHOSUPR_BIT);
901 } else {
902 max310x_port_update(&one->port, MAX310X_MODE1_REG,
903 MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
904 max310x_port_update(&one->port, MAX310X_MODE2_REG,
905 MAX310X_MODE2_ECHOSUPR_BIT, 0);
906 }
907}
908
909static int max310x_rs485_config(struct uart_port *port,
910 struct serial_rs485 *rs485)
911{
912 struct max310x_one *one = container_of(port, struct max310x_one, port);
913
914 if ((rs485->delay_rts_before_send > 0x0f) ||
915 (rs485->delay_rts_after_send > 0x0f))
916 return -ERANGE;
917
918 rs485->flags &= SER_RS485_RTS_ON_SEND | SER_RS485_ENABLED;
919 memset(rs485->padding, 0, sizeof(rs485->padding));
920 port->rs485 = *rs485;
921
922 schedule_work(&one->rs_work);
923
924 return 0;
925}
926
927static int max310x_startup(struct uart_port *port)
928{
929 struct max310x_port *s = dev_get_drvdata(port->dev);
930 unsigned int val;
931
932 s->devtype->power(port, 1);
933
934
935 max310x_port_update(port, MAX310X_MODE1_REG,
936 MAX310X_MODE1_TRNSCVCTRL_BIT, 0);
937
938
939 val = MAX310X_MODE2_RXEMPTINV_BIT | MAX310X_MODE2_FIFORST_BIT;
940 max310x_port_write(port, MAX310X_MODE2_REG, val);
941 max310x_port_update(port, MAX310X_MODE2_REG,
942 MAX310X_MODE2_FIFORST_BIT, 0);
943
944
945
946 max310x_port_write(port, MAX310X_FLOWLVL_REG,
947 MAX310X_FLOWLVL_RES(48) | MAX310X_FLOWLVL_HALT(96));
948
949
950 max310x_port_read(port, MAX310X_IRQSTS_REG);
951
952
953 val = MAX310X_IRQ_RXEMPTY_BIT | MAX310X_IRQ_TXEMPTY_BIT;
954 max310x_port_write(port, MAX310X_IRQEN_REG, val | MAX310X_IRQ_CTS_BIT);
955
956 return 0;
957}
958
959static void max310x_shutdown(struct uart_port *port)
960{
961 struct max310x_port *s = dev_get_drvdata(port->dev);
962
963
964 max310x_port_write(port, MAX310X_IRQEN_REG, 0);
965
966 s->devtype->power(port, 0);
967}
968
969static const char *max310x_type(struct uart_port *port)
970{
971 struct max310x_port *s = dev_get_drvdata(port->dev);
972
973 return (port->type == PORT_MAX310X) ? s->devtype->name : NULL;
974}
975
976static int max310x_request_port(struct uart_port *port)
977{
978
979 return 0;
980}
981
982static void max310x_config_port(struct uart_port *port, int flags)
983{
984 if (flags & UART_CONFIG_TYPE)
985 port->type = PORT_MAX310X;
986}
987
988static int max310x_verify_port(struct uart_port *port, struct serial_struct *s)
989{
990 if ((s->type != PORT_UNKNOWN) && (s->type != PORT_MAX310X))
991 return -EINVAL;
992 if (s->irq != port->irq)
993 return -EINVAL;
994
995 return 0;
996}
997
998static void max310x_null_void(struct uart_port *port)
999{
1000
1001}
1002
1003static const struct uart_ops max310x_ops = {
1004 .tx_empty = max310x_tx_empty,
1005 .set_mctrl = max310x_set_mctrl,
1006 .get_mctrl = max310x_get_mctrl,
1007 .stop_tx = max310x_null_void,
1008 .start_tx = max310x_start_tx,
1009 .stop_rx = max310x_null_void,
1010 .break_ctl = max310x_break_ctl,
1011 .startup = max310x_startup,
1012 .shutdown = max310x_shutdown,
1013 .set_termios = max310x_set_termios,
1014 .type = max310x_type,
1015 .request_port = max310x_request_port,
1016 .release_port = max310x_null_void,
1017 .config_port = max310x_config_port,
1018 .verify_port = max310x_verify_port,
1019};
1020
1021static int __maybe_unused max310x_suspend(struct device *dev)
1022{
1023 struct max310x_port *s = dev_get_drvdata(dev);
1024 int i;
1025
1026 for (i = 0; i < s->devtype->nr; i++) {
1027 uart_suspend_port(&max310x_uart, &s->p[i].port);
1028 s->devtype->power(&s->p[i].port, 0);
1029 }
1030
1031 return 0;
1032}
1033
1034static int __maybe_unused max310x_resume(struct device *dev)
1035{
1036 struct max310x_port *s = dev_get_drvdata(dev);
1037 int i;
1038
1039 for (i = 0; i < s->devtype->nr; i++) {
1040 s->devtype->power(&s->p[i].port, 1);
1041 uart_resume_port(&max310x_uart, &s->p[i].port);
1042 }
1043
1044 return 0;
1045}
1046
1047static SIMPLE_DEV_PM_OPS(max310x_pm_ops, max310x_suspend, max310x_resume);
1048
1049#ifdef CONFIG_GPIOLIB
1050static int max310x_gpio_get(struct gpio_chip *chip, unsigned offset)
1051{
1052 unsigned int val;
1053 struct max310x_port *s = gpiochip_get_data(chip);
1054 struct uart_port *port = &s->p[offset / 4].port;
1055
1056 val = max310x_port_read(port, MAX310X_GPIODATA_REG);
1057
1058 return !!((val >> 4) & (1 << (offset % 4)));
1059}
1060
1061static void max310x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1062{
1063 struct max310x_port *s = gpiochip_get_data(chip);
1064 struct uart_port *port = &s->p[offset / 4].port;
1065
1066 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1067 value ? 1 << (offset % 4) : 0);
1068}
1069
1070static int max310x_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
1071{
1072 struct max310x_port *s = gpiochip_get_data(chip);
1073 struct uart_port *port = &s->p[offset / 4].port;
1074
1075 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4), 0);
1076
1077 return 0;
1078}
1079
1080static int max310x_gpio_direction_output(struct gpio_chip *chip,
1081 unsigned offset, int value)
1082{
1083 struct max310x_port *s = gpiochip_get_data(chip);
1084 struct uart_port *port = &s->p[offset / 4].port;
1085
1086 max310x_port_update(port, MAX310X_GPIODATA_REG, 1 << (offset % 4),
1087 value ? 1 << (offset % 4) : 0);
1088 max310x_port_update(port, MAX310X_GPIOCFG_REG, 1 << (offset % 4),
1089 1 << (offset % 4));
1090
1091 return 0;
1092}
1093#endif
1094
1095static int max310x_probe(struct device *dev, struct max310x_devtype *devtype,
1096 struct regmap *regmap, int irq, unsigned long flags)
1097{
1098 int i, ret, fmin, fmax, freq, uartclk;
1099 struct clk *clk_osc, *clk_xtal;
1100 struct max310x_port *s;
1101 bool xtal = false;
1102
1103 if (IS_ERR(regmap))
1104 return PTR_ERR(regmap);
1105
1106
1107 s = devm_kzalloc(dev, sizeof(*s) +
1108 sizeof(struct max310x_one) * devtype->nr, GFP_KERNEL);
1109 if (!s) {
1110 dev_err(dev, "Error allocating port structure\n");
1111 return -ENOMEM;
1112 }
1113
1114 clk_osc = devm_clk_get(dev, "osc");
1115 clk_xtal = devm_clk_get(dev, "xtal");
1116 if (!IS_ERR(clk_osc)) {
1117 s->clk = clk_osc;
1118 fmin = 500000;
1119 fmax = 35000000;
1120 } else if (!IS_ERR(clk_xtal)) {
1121 s->clk = clk_xtal;
1122 fmin = 1000000;
1123 fmax = 4000000;
1124 xtal = true;
1125 } else if (PTR_ERR(clk_osc) == -EPROBE_DEFER ||
1126 PTR_ERR(clk_xtal) == -EPROBE_DEFER) {
1127 return -EPROBE_DEFER;
1128 } else {
1129 dev_err(dev, "Cannot get clock\n");
1130 return -EINVAL;
1131 }
1132
1133 ret = clk_prepare_enable(s->clk);
1134 if (ret)
1135 return ret;
1136
1137 freq = clk_get_rate(s->clk);
1138
1139 if (freq < fmin || freq > fmax) {
1140 ret = -ERANGE;
1141 goto out_clk;
1142 }
1143
1144 s->regmap = regmap;
1145 s->devtype = devtype;
1146 dev_set_drvdata(dev, s);
1147
1148
1149 ret = devtype->detect(dev);
1150 if (ret)
1151 goto out_clk;
1152
1153 for (i = 0; i < devtype->nr; i++) {
1154 unsigned int offs = i << 5;
1155
1156
1157 regmap_write(s->regmap, MAX310X_MODE2_REG + offs,
1158 MAX310X_MODE2_RST_BIT);
1159
1160 regmap_write(s->regmap, MAX310X_MODE2_REG + offs, 0);
1161
1162
1163 do {
1164 regmap_read(s->regmap,
1165 MAX310X_BRGDIVLSB_REG + offs, &ret);
1166 } while (ret != 0x01);
1167
1168 regmap_update_bits(s->regmap, MAX310X_MODE1_REG + offs,
1169 MAX310X_MODE1_AUTOSLEEP_BIT,
1170 MAX310X_MODE1_AUTOSLEEP_BIT);
1171 }
1172
1173 uartclk = max310x_set_ref_clk(s, freq, xtal);
1174 dev_dbg(dev, "Reference clock set to %i Hz\n", uartclk);
1175
1176#ifdef CONFIG_GPIOLIB
1177
1178 s->gpio.owner = THIS_MODULE;
1179 s->gpio.parent = dev;
1180 s->gpio.label = dev_name(dev);
1181 s->gpio.direction_input = max310x_gpio_direction_input;
1182 s->gpio.get = max310x_gpio_get;
1183 s->gpio.direction_output= max310x_gpio_direction_output;
1184 s->gpio.set = max310x_gpio_set;
1185 s->gpio.base = -1;
1186 s->gpio.ngpio = devtype->nr * 4;
1187 s->gpio.can_sleep = 1;
1188 ret = devm_gpiochip_add_data(dev, &s->gpio, s);
1189 if (ret)
1190 goto out_clk;
1191#endif
1192
1193 mutex_init(&s->mutex);
1194
1195 for (i = 0; i < devtype->nr; i++) {
1196 unsigned int line;
1197
1198 line = find_first_zero_bit(max310x_lines, MAX310X_UART_NRMAX);
1199 if (line == MAX310X_UART_NRMAX) {
1200 ret = -ERANGE;
1201 goto out_uart;
1202 }
1203
1204
1205 s->p[i].port.line = line;
1206 s->p[i].port.dev = dev;
1207 s->p[i].port.irq = irq;
1208 s->p[i].port.type = PORT_MAX310X;
1209 s->p[i].port.fifosize = MAX310X_FIFO_SIZE;
1210 s->p[i].port.flags = UPF_FIXED_TYPE | UPF_LOW_LATENCY;
1211 s->p[i].port.iotype = UPIO_PORT;
1212 s->p[i].port.iobase = i * 0x20;
1213 s->p[i].port.membase = (void __iomem *)~0;
1214 s->p[i].port.uartclk = uartclk;
1215 s->p[i].port.rs485_config = max310x_rs485_config;
1216 s->p[i].port.ops = &max310x_ops;
1217
1218 max310x_port_write(&s->p[i].port, MAX310X_IRQEN_REG, 0);
1219
1220 max310x_port_read(&s->p[i].port, MAX310X_IRQSTS_REG);
1221
1222 max310x_port_update(&s->p[i].port, MAX310X_MODE1_REG,
1223 MAX310X_MODE1_IRQSEL_BIT,
1224 MAX310X_MODE1_IRQSEL_BIT);
1225
1226 INIT_WORK(&s->p[i].tx_work, max310x_wq_proc);
1227
1228 INIT_WORK(&s->p[i].md_work, max310x_md_proc);
1229
1230 INIT_WORK(&s->p[i].rs_work, max310x_rs_proc);
1231
1232
1233 ret = uart_add_one_port(&max310x_uart, &s->p[i].port);
1234 if (ret) {
1235 s->p[i].port.dev = NULL;
1236 goto out_uart;
1237 }
1238 set_bit(line, max310x_lines);
1239
1240
1241 devtype->power(&s->p[i].port, 0);
1242 }
1243
1244
1245 ret = devm_request_threaded_irq(dev, irq, NULL, max310x_ist,
1246 IRQF_ONESHOT | flags, dev_name(dev), s);
1247 if (!ret)
1248 return 0;
1249
1250 dev_err(dev, "Unable to reguest IRQ %i\n", irq);
1251
1252out_uart:
1253 for (i = 0; i < devtype->nr; i++) {
1254 if (s->p[i].port.dev) {
1255 uart_remove_one_port(&max310x_uart, &s->p[i].port);
1256 clear_bit(s->p[i].port.line, max310x_lines);
1257 }
1258 }
1259
1260 mutex_destroy(&s->mutex);
1261
1262out_clk:
1263 clk_disable_unprepare(s->clk);
1264
1265 return ret;
1266}
1267
1268static int max310x_remove(struct device *dev)
1269{
1270 struct max310x_port *s = dev_get_drvdata(dev);
1271 int i;
1272
1273 for (i = 0; i < s->devtype->nr; i++) {
1274 cancel_work_sync(&s->p[i].tx_work);
1275 cancel_work_sync(&s->p[i].md_work);
1276 cancel_work_sync(&s->p[i].rs_work);
1277 uart_remove_one_port(&max310x_uart, &s->p[i].port);
1278 clear_bit(s->p[i].port.line, max310x_lines);
1279 s->devtype->power(&s->p[i].port, 0);
1280 }
1281
1282 mutex_destroy(&s->mutex);
1283 clk_disable_unprepare(s->clk);
1284
1285 return 0;
1286}
1287
1288static const struct of_device_id __maybe_unused max310x_dt_ids[] = {
1289 { .compatible = "maxim,max3107", .data = &max3107_devtype, },
1290 { .compatible = "maxim,max3108", .data = &max3108_devtype, },
1291 { .compatible = "maxim,max3109", .data = &max3109_devtype, },
1292 { .compatible = "maxim,max14830", .data = &max14830_devtype },
1293 { }
1294};
1295MODULE_DEVICE_TABLE(of, max310x_dt_ids);
1296
1297static struct regmap_config regcfg = {
1298 .reg_bits = 8,
1299 .val_bits = 8,
1300 .write_flag_mask = 0x80,
1301 .cache_type = REGCACHE_RBTREE,
1302 .writeable_reg = max310x_reg_writeable,
1303 .volatile_reg = max310x_reg_volatile,
1304 .precious_reg = max310x_reg_precious,
1305};
1306
1307#ifdef CONFIG_SPI_MASTER
1308static int max310x_spi_probe(struct spi_device *spi)
1309{
1310 struct max310x_devtype *devtype;
1311 unsigned long flags = 0;
1312 struct regmap *regmap;
1313 int ret;
1314
1315
1316 spi->bits_per_word = 8;
1317 spi->mode = spi->mode ? : SPI_MODE_0;
1318 spi->max_speed_hz = spi->max_speed_hz ? : 26000000;
1319 ret = spi_setup(spi);
1320 if (ret)
1321 return ret;
1322
1323 if (spi->dev.of_node) {
1324 const struct of_device_id *of_id =
1325 of_match_device(max310x_dt_ids, &spi->dev);
1326
1327 devtype = (struct max310x_devtype *)of_id->data;
1328 } else {
1329 const struct spi_device_id *id_entry = spi_get_device_id(spi);
1330
1331 devtype = (struct max310x_devtype *)id_entry->driver_data;
1332 }
1333
1334 flags = IRQF_TRIGGER_FALLING;
1335 regcfg.max_register = devtype->nr * 0x20 - 1;
1336 regmap = devm_regmap_init_spi(spi, ®cfg);
1337
1338 return max310x_probe(&spi->dev, devtype, regmap, spi->irq, flags);
1339}
1340
1341static int max310x_spi_remove(struct spi_device *spi)
1342{
1343 return max310x_remove(&spi->dev);
1344}
1345
1346static const struct spi_device_id max310x_id_table[] = {
1347 { "max3107", (kernel_ulong_t)&max3107_devtype, },
1348 { "max3108", (kernel_ulong_t)&max3108_devtype, },
1349 { "max3109", (kernel_ulong_t)&max3109_devtype, },
1350 { "max14830", (kernel_ulong_t)&max14830_devtype, },
1351 { }
1352};
1353MODULE_DEVICE_TABLE(spi, max310x_id_table);
1354
1355static struct spi_driver max310x_spi_driver = {
1356 .driver = {
1357 .name = MAX310X_NAME,
1358 .of_match_table = of_match_ptr(max310x_dt_ids),
1359 .pm = &max310x_pm_ops,
1360 },
1361 .probe = max310x_spi_probe,
1362 .remove = max310x_spi_remove,
1363 .id_table = max310x_id_table,
1364};
1365#endif
1366
1367static int __init max310x_uart_init(void)
1368{
1369 int ret;
1370
1371 bitmap_zero(max310x_lines, MAX310X_UART_NRMAX);
1372
1373 ret = uart_register_driver(&max310x_uart);
1374 if (ret)
1375 return ret;
1376
1377#ifdef CONFIG_SPI_MASTER
1378 spi_register_driver(&max310x_spi_driver);
1379#endif
1380
1381 return 0;
1382}
1383module_init(max310x_uart_init);
1384
1385static void __exit max310x_uart_exit(void)
1386{
1387#ifdef CONFIG_SPI_MASTER
1388 spi_unregister_driver(&max310x_spi_driver);
1389#endif
1390
1391 uart_unregister_driver(&max310x_uart);
1392}
1393module_exit(max310x_uart_exit);
1394
1395MODULE_LICENSE("GPL");
1396MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
1397MODULE_DESCRIPTION("MAX310X serial driver");
1398