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10
11#define pr_fmt(fmt) KBUILD_MODNAME ":" fmt
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/interrupt.h>
16#include <linux/serial_core.h>
17#include <linux/ioport.h>
18#include <linux/io.h>
19#include <linux/tty_flip.h>
20#include <linux/bitops.h>
21#include <linux/mcb.h>
22
23#define MEN_Z135_MAX_PORTS 12
24#define MEN_Z135_BASECLK 29491200
25#define MEN_Z135_FIFO_SIZE 1024
26#define MEN_Z135_FIFO_WATERMARK 1020
27
28#define MEN_Z135_STAT_REG 0x0
29#define MEN_Z135_RX_RAM 0x4
30#define MEN_Z135_TX_RAM 0x400
31#define MEN_Z135_RX_CTRL 0x800
32#define MEN_Z135_TX_CTRL 0x804
33#define MEN_Z135_CONF_REG 0x808
34#define MEN_Z135_UART_FREQ 0x80c
35#define MEN_Z135_BAUD_REG 0x810
36#define MEN_Z135_TIMEOUT 0x814
37
38#define IRQ_ID(x) ((x) & 0x1f)
39
40#define MEN_Z135_IER_RXCIEN BIT(0)
41#define MEN_Z135_IER_TXCIEN BIT(1)
42#define MEN_Z135_IER_RLSIEN BIT(2)
43#define MEN_Z135_IER_MSIEN BIT(3)
44#define MEN_Z135_ALL_IRQS (MEN_Z135_IER_RXCIEN \
45 | MEN_Z135_IER_RLSIEN \
46 | MEN_Z135_IER_MSIEN \
47 | MEN_Z135_IER_TXCIEN)
48
49#define MEN_Z135_MCR_DTR BIT(24)
50#define MEN_Z135_MCR_RTS BIT(25)
51#define MEN_Z135_MCR_OUT1 BIT(26)
52#define MEN_Z135_MCR_OUT2 BIT(27)
53#define MEN_Z135_MCR_LOOP BIT(28)
54#define MEN_Z135_MCR_RCFC BIT(29)
55
56#define MEN_Z135_MSR_DCTS BIT(0)
57#define MEN_Z135_MSR_DDSR BIT(1)
58#define MEN_Z135_MSR_DRI BIT(2)
59#define MEN_Z135_MSR_DDCD BIT(3)
60#define MEN_Z135_MSR_CTS BIT(4)
61#define MEN_Z135_MSR_DSR BIT(5)
62#define MEN_Z135_MSR_RI BIT(6)
63#define MEN_Z135_MSR_DCD BIT(7)
64
65#define MEN_Z135_LCR_SHIFT 8
66
67#define MEN_Z135_WL5 0
68#define MEN_Z135_WL6 1
69#define MEN_Z135_WL7 2
70#define MEN_Z135_WL8 3
71
72#define MEN_Z135_STB_SHIFT 2
73#define MEN_Z135_NSTB1 0
74#define MEN_Z135_NSTB2 1
75
76#define MEN_Z135_PEN_SHIFT 3
77#define MEN_Z135_PAR_DIS 0
78#define MEN_Z135_PAR_ENA 1
79
80#define MEN_Z135_PTY_SHIFT 4
81#define MEN_Z135_PTY_ODD 0
82#define MEN_Z135_PTY_EVN 1
83
84#define MEN_Z135_LSR_DR BIT(0)
85#define MEN_Z135_LSR_OE BIT(1)
86#define MEN_Z135_LSR_PE BIT(2)
87#define MEN_Z135_LSR_FE BIT(3)
88#define MEN_Z135_LSR_BI BIT(4)
89#define MEN_Z135_LSR_THEP BIT(5)
90#define MEN_Z135_LSR_TEXP BIT(6)
91#define MEN_Z135_LSR_RXFIFOERR BIT(7)
92
93#define MEN_Z135_IRQ_ID_RLS BIT(0)
94#define MEN_Z135_IRQ_ID_RDA BIT(1)
95#define MEN_Z135_IRQ_ID_CTI BIT(2)
96#define MEN_Z135_IRQ_ID_TSA BIT(3)
97#define MEN_Z135_IRQ_ID_MST BIT(4)
98
99#define LCR(x) (((x) >> MEN_Z135_LCR_SHIFT) & 0xff)
100
101#define BYTES_TO_ALIGN(x) ((x) & 0x3)
102
103static int line;
104
105static int txlvl = 5;
106module_param(txlvl, int, S_IRUGO);
107MODULE_PARM_DESC(txlvl, "TX IRQ trigger level 0-7, default 5 (128 byte)");
108
109static int rxlvl = 6;
110module_param(rxlvl, int, S_IRUGO);
111MODULE_PARM_DESC(rxlvl, "RX IRQ trigger level 0-7, default 6 (256 byte)");
112
113static int align;
114module_param(align, int, S_IRUGO);
115MODULE_PARM_DESC(align, "Keep hardware FIFO write pointer aligned, default 0");
116
117static uint rx_timeout;
118module_param(rx_timeout, uint, S_IRUGO);
119MODULE_PARM_DESC(rx_timeout, "RX timeout. "
120 "Timeout in seconds = (timeout_reg * baud_reg * 4) / freq_reg");
121
122struct men_z135_port {
123 struct uart_port port;
124 struct mcb_device *mdev;
125 struct resource *mem;
126 unsigned char *rxbuf;
127 u32 stat_reg;
128 spinlock_t lock;
129 bool automode;
130};
131#define to_men_z135(port) container_of((port), struct men_z135_port, port)
132
133
134
135
136
137
138
139static inline void men_z135_reg_set(struct men_z135_port *uart,
140 u32 addr, u32 val)
141{
142 struct uart_port *port = &uart->port;
143 unsigned long flags;
144 u32 reg;
145
146 spin_lock_irqsave(&uart->lock, flags);
147
148 reg = ioread32(port->membase + addr);
149 reg |= val;
150 iowrite32(reg, port->membase + addr);
151
152 spin_unlock_irqrestore(&uart->lock, flags);
153}
154
155
156
157
158
159
160
161static void men_z135_reg_clr(struct men_z135_port *uart,
162 u32 addr, u32 val)
163{
164 struct uart_port *port = &uart->port;
165 unsigned long flags;
166 u32 reg;
167
168 spin_lock_irqsave(&uart->lock, flags);
169
170 reg = ioread32(port->membase + addr);
171 reg &= ~val;
172 iowrite32(reg, port->membase + addr);
173
174 spin_unlock_irqrestore(&uart->lock, flags);
175}
176
177
178
179
180
181
182
183
184static void men_z135_handle_modem_status(struct men_z135_port *uart)
185{
186 u8 msr;
187
188 msr = (uart->stat_reg >> 8) & 0xff;
189
190 if (msr & MEN_Z135_MSR_DDCD)
191 uart_handle_dcd_change(&uart->port,
192 msr & MEN_Z135_MSR_DCD);
193 if (msr & MEN_Z135_MSR_DCTS)
194 uart_handle_cts_change(&uart->port,
195 msr & MEN_Z135_MSR_CTS);
196}
197
198static void men_z135_handle_lsr(struct men_z135_port *uart)
199{
200 struct uart_port *port = &uart->port;
201 u8 lsr;
202
203 lsr = (uart->stat_reg >> 16) & 0xff;
204
205 if (lsr & MEN_Z135_LSR_OE)
206 port->icount.overrun++;
207 if (lsr & MEN_Z135_LSR_PE)
208 port->icount.parity++;
209 if (lsr & MEN_Z135_LSR_FE)
210 port->icount.frame++;
211 if (lsr & MEN_Z135_LSR_BI) {
212 port->icount.brk++;
213 uart_handle_break(port);
214 }
215}
216
217
218
219
220
221
222
223static u16 get_rx_fifo_content(struct men_z135_port *uart)
224{
225 struct uart_port *port = &uart->port;
226 u32 stat_reg;
227 u16 rxc;
228 u8 rxc_lo;
229 u8 rxc_hi;
230
231 stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG);
232 rxc_lo = stat_reg >> 24;
233 rxc_hi = (stat_reg & 0xC0) >> 6;
234
235 rxc = rxc_lo | (rxc_hi << 8);
236
237 return rxc;
238}
239
240
241
242
243
244
245
246static void men_z135_handle_rx(struct men_z135_port *uart)
247{
248 struct uart_port *port = &uart->port;
249 struct tty_port *tport = &port->state->port;
250 int copied;
251 u16 size;
252 int room;
253
254 size = get_rx_fifo_content(uart);
255
256 if (size == 0)
257 return;
258
259
260
261
262 if (size > MEN_Z135_FIFO_WATERMARK)
263 size = MEN_Z135_FIFO_WATERMARK;
264
265 room = tty_buffer_request_room(tport, size);
266 if (room != size)
267 dev_warn(&uart->mdev->dev,
268 "Not enough room in flip buffer, truncating to %d\n",
269 room);
270
271 if (room == 0)
272 return;
273
274 memcpy_fromio(uart->rxbuf, port->membase + MEN_Z135_RX_RAM, room);
275
276 mb();
277 iowrite32(room, port->membase + MEN_Z135_RX_CTRL);
278
279 copied = tty_insert_flip_string(tport, uart->rxbuf, room);
280 if (copied != room)
281 dev_warn(&uart->mdev->dev,
282 "Only copied %d instead of %d bytes\n",
283 copied, room);
284
285 port->icount.rx += copied;
286
287 tty_flip_buffer_push(tport);
288
289}
290
291
292
293
294
295
296static void men_z135_handle_tx(struct men_z135_port *uart)
297{
298 struct uart_port *port = &uart->port;
299 struct circ_buf *xmit = &port->state->xmit;
300 u32 txc;
301 u32 wptr;
302 int qlen;
303 int n;
304 int txfree;
305 int head;
306 int tail;
307 int s;
308
309 if (uart_circ_empty(xmit))
310 goto out;
311
312 if (uart_tx_stopped(port))
313 goto out;
314
315 if (port->x_char)
316 goto out;
317
318
319 qlen = uart_circ_chars_pending(xmit);
320 if (qlen <= 0)
321 goto out;
322
323 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL);
324 txc = (wptr >> 16) & 0x3ff;
325 wptr &= 0x3ff;
326
327 if (txc > MEN_Z135_FIFO_WATERMARK)
328 txc = MEN_Z135_FIFO_WATERMARK;
329
330 txfree = MEN_Z135_FIFO_WATERMARK - txc;
331 if (txfree <= 0) {
332 dev_err(&uart->mdev->dev,
333 "Not enough room in TX FIFO have %d, need %d\n",
334 txfree, qlen);
335 goto irq_en;
336 }
337
338
339
340
341 if (align && qlen >= 3 && BYTES_TO_ALIGN(wptr))
342 n = 4 - BYTES_TO_ALIGN(wptr);
343 else if (qlen > txfree)
344 n = txfree;
345 else
346 n = qlen;
347
348 if (n <= 0)
349 goto irq_en;
350
351 head = xmit->head & (UART_XMIT_SIZE - 1);
352 tail = xmit->tail & (UART_XMIT_SIZE - 1);
353
354 s = ((head >= tail) ? head : UART_XMIT_SIZE) - tail;
355 n = min(n, s);
356
357 memcpy_toio(port->membase + MEN_Z135_TX_RAM, &xmit->buf[xmit->tail], n);
358 xmit->tail = (xmit->tail + n) & (UART_XMIT_SIZE - 1);
359 mmiowb();
360
361 iowrite32(n & 0x3ff, port->membase + MEN_Z135_TX_CTRL);
362
363 port->icount.tx += n;
364
365 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
366 uart_write_wakeup(port);
367
368irq_en:
369 if (!uart_circ_empty(xmit))
370 men_z135_reg_set(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN);
371 else
372 men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN);
373
374out:
375 return;
376
377}
378
379
380
381
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383
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385
386
387
388
389static irqreturn_t men_z135_intr(int irq, void *data)
390{
391 struct men_z135_port *uart = (struct men_z135_port *)data;
392 struct uart_port *port = &uart->port;
393 bool handled = false;
394 int irq_id;
395
396 uart->stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG);
397 irq_id = IRQ_ID(uart->stat_reg);
398
399 if (!irq_id)
400 goto out;
401
402 spin_lock(&port->lock);
403
404 iowrite8(irq_id, port->membase + MEN_Z135_STAT_REG);
405
406 if (irq_id & MEN_Z135_IRQ_ID_RLS) {
407 men_z135_handle_lsr(uart);
408 handled = true;
409 }
410
411 if (irq_id & (MEN_Z135_IRQ_ID_RDA | MEN_Z135_IRQ_ID_CTI)) {
412 if (irq_id & MEN_Z135_IRQ_ID_CTI)
413 dev_dbg(&uart->mdev->dev, "Character Timeout Indication\n");
414 men_z135_handle_rx(uart);
415 handled = true;
416 }
417
418 if (irq_id & MEN_Z135_IRQ_ID_TSA) {
419 men_z135_handle_tx(uart);
420 handled = true;
421 }
422
423 if (irq_id & MEN_Z135_IRQ_ID_MST) {
424 men_z135_handle_modem_status(uart);
425 handled = true;
426 }
427
428 spin_unlock(&port->lock);
429out:
430 return IRQ_RETVAL(handled);
431}
432
433
434
435
436
437
438
439
440static int men_z135_request_irq(struct men_z135_port *uart)
441{
442 struct device *dev = &uart->mdev->dev;
443 struct uart_port *port = &uart->port;
444 int err = 0;
445
446 err = request_irq(port->irq, men_z135_intr, IRQF_SHARED,
447 "men_z135_intr", uart);
448 if (err)
449 dev_err(dev, "Error %d getting interrupt\n", err);
450
451 return err;
452}
453
454
455
456
457
458
459
460
461static unsigned int men_z135_tx_empty(struct uart_port *port)
462{
463 u32 wptr;
464 u16 txc;
465
466 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL);
467 txc = (wptr >> 16) & 0x3ff;
468
469 if (txc == 0)
470 return TIOCSER_TEMT;
471 else
472 return 0;
473}
474
475
476
477
478
479
480
481
482
483static void men_z135_set_mctrl(struct uart_port *port, unsigned int mctrl)
484{
485 u32 old;
486 u32 conf_reg;
487
488 conf_reg = old = ioread32(port->membase + MEN_Z135_CONF_REG);
489 if (mctrl & TIOCM_RTS)
490 conf_reg |= MEN_Z135_MCR_RTS;
491 else
492 conf_reg &= ~MEN_Z135_MCR_RTS;
493
494 if (mctrl & TIOCM_DTR)
495 conf_reg |= MEN_Z135_MCR_DTR;
496 else
497 conf_reg &= ~MEN_Z135_MCR_DTR;
498
499 if (mctrl & TIOCM_OUT1)
500 conf_reg |= MEN_Z135_MCR_OUT1;
501 else
502 conf_reg &= ~MEN_Z135_MCR_OUT1;
503
504 if (mctrl & TIOCM_OUT2)
505 conf_reg |= MEN_Z135_MCR_OUT2;
506 else
507 conf_reg &= ~MEN_Z135_MCR_OUT2;
508
509 if (mctrl & TIOCM_LOOP)
510 conf_reg |= MEN_Z135_MCR_LOOP;
511 else
512 conf_reg &= ~MEN_Z135_MCR_LOOP;
513
514 if (conf_reg != old)
515 iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG);
516}
517
518
519
520
521
522
523
524static unsigned int men_z135_get_mctrl(struct uart_port *port)
525{
526 unsigned int mctrl = 0;
527 u8 msr;
528
529 msr = ioread8(port->membase + MEN_Z135_STAT_REG + 1);
530
531 if (msr & MEN_Z135_MSR_CTS)
532 mctrl |= TIOCM_CTS;
533 if (msr & MEN_Z135_MSR_DSR)
534 mctrl |= TIOCM_DSR;
535 if (msr & MEN_Z135_MSR_RI)
536 mctrl |= TIOCM_RI;
537 if (msr & MEN_Z135_MSR_DCD)
538 mctrl |= TIOCM_CAR;
539
540 return mctrl;
541}
542
543
544
545
546
547
548
549
550
551static void men_z135_stop_tx(struct uart_port *port)
552{
553 struct men_z135_port *uart = to_men_z135(port);
554
555 men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN);
556}
557
558
559
560
561
562
563
564static void men_z135_disable_ms(struct uart_port *port)
565{
566 struct men_z135_port *uart = to_men_z135(port);
567
568 men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_MSIEN);
569}
570
571
572
573
574
575
576
577
578static void men_z135_start_tx(struct uart_port *port)
579{
580 struct men_z135_port *uart = to_men_z135(port);
581
582 if (uart->automode)
583 men_z135_disable_ms(port);
584
585 men_z135_handle_tx(uart);
586}
587
588
589
590
591
592
593
594static void men_z135_stop_rx(struct uart_port *port)
595{
596 struct men_z135_port *uart = to_men_z135(port);
597
598 men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_RXCIEN);
599}
600
601
602
603
604
605
606
607static void men_z135_enable_ms(struct uart_port *port)
608{
609 struct men_z135_port *uart = to_men_z135(port);
610
611 men_z135_reg_set(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_MSIEN);
612}
613
614static int men_z135_startup(struct uart_port *port)
615{
616 struct men_z135_port *uart = to_men_z135(port);
617 int err;
618 u32 conf_reg = 0;
619
620 err = men_z135_request_irq(uart);
621 if (err)
622 return -ENODEV;
623
624 conf_reg = ioread32(port->membase + MEN_Z135_CONF_REG);
625
626
627 conf_reg |= MEN_Z135_ALL_IRQS & ~MEN_Z135_IER_TXCIEN;
628 conf_reg &= ~(0xff << 16);
629 conf_reg |= (txlvl << 16);
630 conf_reg |= (rxlvl << 20);
631
632 iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG);
633
634 if (rx_timeout)
635 iowrite32(rx_timeout, port->membase + MEN_Z135_TIMEOUT);
636
637 return 0;
638}
639
640static void men_z135_shutdown(struct uart_port *port)
641{
642 struct men_z135_port *uart = to_men_z135(port);
643 u32 conf_reg = 0;
644
645 conf_reg |= MEN_Z135_ALL_IRQS;
646
647 men_z135_reg_clr(uart, MEN_Z135_CONF_REG, conf_reg);
648
649 free_irq(uart->port.irq, uart);
650}
651
652static void men_z135_set_termios(struct uart_port *port,
653 struct ktermios *termios,
654 struct ktermios *old)
655{
656 struct men_z135_port *uart = to_men_z135(port);
657 unsigned int baud;
658 u32 conf_reg;
659 u32 bd_reg;
660 u32 uart_freq;
661 u8 lcr;
662
663 conf_reg = ioread32(port->membase + MEN_Z135_CONF_REG);
664 lcr = LCR(conf_reg);
665
666
667 switch (termios->c_cflag & CSIZE) {
668 case CS5:
669 lcr |= MEN_Z135_WL5;
670 break;
671 case CS6:
672 lcr |= MEN_Z135_WL6;
673 break;
674 case CS7:
675 lcr |= MEN_Z135_WL7;
676 break;
677 case CS8:
678 lcr |= MEN_Z135_WL8;
679 break;
680 }
681
682
683 if (termios->c_cflag & CSTOPB)
684 lcr |= MEN_Z135_NSTB2 << MEN_Z135_STB_SHIFT;
685
686
687 if (termios->c_cflag & PARENB) {
688 lcr |= MEN_Z135_PAR_ENA << MEN_Z135_PEN_SHIFT;
689
690 if (termios->c_cflag & PARODD)
691 lcr |= MEN_Z135_PTY_ODD << MEN_Z135_PTY_SHIFT;
692 else
693 lcr |= MEN_Z135_PTY_EVN << MEN_Z135_PTY_SHIFT;
694 } else
695 lcr |= MEN_Z135_PAR_DIS << MEN_Z135_PEN_SHIFT;
696
697 conf_reg |= MEN_Z135_IER_MSIEN;
698 if (termios->c_cflag & CRTSCTS) {
699 conf_reg |= MEN_Z135_MCR_RCFC;
700 uart->automode = true;
701 termios->c_cflag &= ~CLOCAL;
702 } else {
703 conf_reg &= ~MEN_Z135_MCR_RCFC;
704 uart->automode = false;
705 }
706
707 termios->c_cflag &= ~CMSPAR;
708
709 conf_reg |= lcr << MEN_Z135_LCR_SHIFT;
710 iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG);
711
712 uart_freq = ioread32(port->membase + MEN_Z135_UART_FREQ);
713 if (uart_freq == 0)
714 uart_freq = MEN_Z135_BASECLK;
715
716 baud = uart_get_baud_rate(port, termios, old, 0, uart_freq / 16);
717
718 spin_lock_irq(&port->lock);
719 if (tty_termios_baud_rate(termios))
720 tty_termios_encode_baud_rate(termios, baud, baud);
721
722 bd_reg = uart_freq / (4 * baud);
723 iowrite32(bd_reg, port->membase + MEN_Z135_BAUD_REG);
724
725 uart_update_timeout(port, termios->c_cflag, baud);
726 spin_unlock_irq(&port->lock);
727}
728
729static const char *men_z135_type(struct uart_port *port)
730{
731 return KBUILD_MODNAME;
732}
733
734static void men_z135_release_port(struct uart_port *port)
735{
736 struct men_z135_port *uart = to_men_z135(port);
737
738 iounmap(port->membase);
739 port->membase = NULL;
740
741 mcb_release_mem(uart->mem);
742}
743
744static int men_z135_request_port(struct uart_port *port)
745{
746 struct men_z135_port *uart = to_men_z135(port);
747 struct mcb_device *mdev = uart->mdev;
748 struct resource *mem;
749
750 mem = mcb_request_mem(uart->mdev, dev_name(&mdev->dev));
751 if (IS_ERR(mem))
752 return PTR_ERR(mem);
753
754 port->mapbase = mem->start;
755 uart->mem = mem;
756
757 port->membase = ioremap(mem->start, resource_size(mem));
758 if (port->membase == NULL) {
759 mcb_release_mem(mem);
760 return -ENOMEM;
761 }
762
763 return 0;
764}
765
766static void men_z135_config_port(struct uart_port *port, int type)
767{
768 port->type = PORT_MEN_Z135;
769 men_z135_request_port(port);
770}
771
772static int men_z135_verify_port(struct uart_port *port,
773 struct serial_struct *serinfo)
774{
775 return -EINVAL;
776}
777
778static const struct uart_ops men_z135_ops = {
779 .tx_empty = men_z135_tx_empty,
780 .set_mctrl = men_z135_set_mctrl,
781 .get_mctrl = men_z135_get_mctrl,
782 .stop_tx = men_z135_stop_tx,
783 .start_tx = men_z135_start_tx,
784 .stop_rx = men_z135_stop_rx,
785 .enable_ms = men_z135_enable_ms,
786 .startup = men_z135_startup,
787 .shutdown = men_z135_shutdown,
788 .set_termios = men_z135_set_termios,
789 .type = men_z135_type,
790 .release_port = men_z135_release_port,
791 .request_port = men_z135_request_port,
792 .config_port = men_z135_config_port,
793 .verify_port = men_z135_verify_port,
794};
795
796static struct uart_driver men_z135_driver = {
797 .owner = THIS_MODULE,
798 .driver_name = KBUILD_MODNAME,
799 .dev_name = "ttyHSU",
800 .major = 0,
801 .minor = 0,
802 .nr = MEN_Z135_MAX_PORTS,
803};
804
805
806
807
808
809
810
811
812
813static int men_z135_probe(struct mcb_device *mdev,
814 const struct mcb_device_id *id)
815{
816 struct men_z135_port *uart;
817 struct resource *mem;
818 struct device *dev;
819 int err;
820
821 dev = &mdev->dev;
822
823 uart = devm_kzalloc(dev, sizeof(struct men_z135_port), GFP_KERNEL);
824 if (!uart)
825 return -ENOMEM;
826
827 uart->rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
828 if (!uart->rxbuf)
829 return -ENOMEM;
830
831 mem = &mdev->mem;
832
833 mcb_set_drvdata(mdev, uart);
834
835 uart->port.uartclk = MEN_Z135_BASECLK * 16;
836 uart->port.fifosize = MEN_Z135_FIFO_SIZE;
837 uart->port.iotype = UPIO_MEM;
838 uart->port.ops = &men_z135_ops;
839 uart->port.irq = mcb_get_irq(mdev);
840 uart->port.iotype = UPIO_MEM;
841 uart->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
842 uart->port.line = line++;
843 uart->port.dev = dev;
844 uart->port.type = PORT_MEN_Z135;
845 uart->port.mapbase = mem->start;
846 uart->port.membase = NULL;
847 uart->mdev = mdev;
848
849 spin_lock_init(&uart->lock);
850
851 err = uart_add_one_port(&men_z135_driver, &uart->port);
852 if (err)
853 goto err;
854
855 return 0;
856
857err:
858 free_page((unsigned long) uart->rxbuf);
859 dev_err(dev, "Failed to add UART: %d\n", err);
860
861 return err;
862}
863
864
865
866
867
868
869static void men_z135_remove(struct mcb_device *mdev)
870{
871 struct men_z135_port *uart = mcb_get_drvdata(mdev);
872
873 line--;
874 uart_remove_one_port(&men_z135_driver, &uart->port);
875 free_page((unsigned long) uart->rxbuf);
876}
877
878static const struct mcb_device_id men_z135_ids[] = {
879 { .device = 0x87 },
880 { }
881};
882MODULE_DEVICE_TABLE(mcb, men_z135_ids);
883
884static struct mcb_driver mcb_driver = {
885 .driver = {
886 .name = "z135-uart",
887 .owner = THIS_MODULE,
888 },
889 .probe = men_z135_probe,
890 .remove = men_z135_remove,
891 .id_table = men_z135_ids,
892};
893
894
895
896
897
898
899
900static int __init men_z135_init(void)
901{
902 int err;
903
904 err = uart_register_driver(&men_z135_driver);
905 if (err) {
906 pr_err("Failed to register UART: %d\n", err);
907 return err;
908 }
909
910 err = mcb_register_driver(&mcb_driver);
911 if (err) {
912 pr_err("Failed to register MCB driver: %d\n", err);
913 uart_unregister_driver(&men_z135_driver);
914 return err;
915 }
916
917 return 0;
918}
919module_init(men_z135_init);
920
921
922
923
924
925
926static void __exit men_z135_exit(void)
927{
928 mcb_unregister_driver(&mcb_driver);
929 uart_unregister_driver(&men_z135_driver);
930}
931module_exit(men_z135_exit);
932
933MODULE_AUTHOR("Johannes Thumshirn <johannes.thumshirn@men.de>");
934MODULE_LICENSE("GPL v2");
935MODULE_DESCRIPTION("MEN 16z135 High Speed UART");
936MODULE_ALIAS("mcb:16z135");
937