linux/drivers/tty/serial/pmac_zilog.h
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   1#ifndef __PMAC_ZILOG_H__
   2#define __PMAC_ZILOG_H__
   3
   4/*
   5 * At most 2 ESCCs with 2 ports each
   6 */
   7#define MAX_ZS_PORTS    4
   8
   9/* 
  10 * We wrap our port structure around the generic uart_port.
  11 */
  12#define NUM_ZSREGS    17
  13
  14struct uart_pmac_port {
  15        struct uart_port                port;
  16        struct uart_pmac_port           *mate;
  17
  18#ifdef CONFIG_PPC_PMAC
  19        /* macio_dev for the escc holding this port (maybe be null on
  20         * early inited port)
  21         */
  22        struct macio_dev                *dev;
  23        /* device node to this port, this points to one of 2 childs
  24         * of "escc" node (ie. ch-a or ch-b)
  25         */
  26        struct device_node              *node;
  27#else
  28        struct platform_device          *pdev;
  29#endif
  30
  31        /* Port type as obtained from device tree (IRDA, modem, ...) */
  32        int                             port_type;
  33        u8                              curregs[NUM_ZSREGS];
  34
  35        unsigned int                    flags;
  36#define PMACZILOG_FLAG_IS_CONS          0x00000001
  37#define PMACZILOG_FLAG_IS_KGDB          0x00000002
  38#define PMACZILOG_FLAG_MODEM_STATUS     0x00000004
  39#define PMACZILOG_FLAG_IS_CHANNEL_A     0x00000008
  40#define PMACZILOG_FLAG_REGS_HELD        0x00000010
  41#define PMACZILOG_FLAG_TX_STOPPED       0x00000020
  42#define PMACZILOG_FLAG_TX_ACTIVE        0x00000040
  43#define PMACZILOG_FLAG_IS_IRDA          0x00000100
  44#define PMACZILOG_FLAG_IS_INTMODEM      0x00000200
  45#define PMACZILOG_FLAG_HAS_DMA          0x00000400
  46#define PMACZILOG_FLAG_RSRC_REQUESTED   0x00000800
  47#define PMACZILOG_FLAG_IS_OPEN          0x00002000
  48#define PMACZILOG_FLAG_IS_EXTCLK        0x00008000
  49#define PMACZILOG_FLAG_BREAK            0x00010000
  50
  51        unsigned char                   parity_mask;
  52        unsigned char                   prev_status;
  53
  54        volatile u8                     __iomem *control_reg;
  55        volatile u8                     __iomem *data_reg;
  56
  57#ifdef CONFIG_PPC_PMAC
  58        unsigned int                    tx_dma_irq;
  59        unsigned int                    rx_dma_irq;
  60        volatile struct dbdma_regs      __iomem *tx_dma_regs;
  61        volatile struct dbdma_regs      __iomem *rx_dma_regs;
  62#endif
  63
  64        unsigned char                   irq_name[8];
  65
  66        struct ktermios                 termios_cache;
  67};
  68
  69#define to_pmz(p) ((struct uart_pmac_port *)(p))
  70
  71static inline struct uart_pmac_port *pmz_get_port_A(struct uart_pmac_port *uap)
  72{
  73        if (uap->flags & PMACZILOG_FLAG_IS_CHANNEL_A)
  74                return uap;
  75        return uap->mate;
  76}
  77
  78/*
  79 * Register accessors. Note that we don't need to enforce a recovery
  80 * delay on PCI PowerMac hardware, it's dealt in HW by the MacIO chip,
  81 * though if we try to use this driver on older machines, we might have
  82 * to add it back
  83 */
  84static inline u8 read_zsreg(struct uart_pmac_port *port, u8 reg)
  85{
  86        if (reg != 0)
  87                writeb(reg, port->control_reg);
  88        return readb(port->control_reg);
  89}
  90
  91static inline void write_zsreg(struct uart_pmac_port *port, u8 reg, u8 value)
  92{
  93        if (reg != 0)
  94                writeb(reg, port->control_reg);
  95        writeb(value, port->control_reg);
  96}
  97
  98static inline u8 read_zsdata(struct uart_pmac_port *port)
  99{
 100        return readb(port->data_reg);
 101}
 102
 103static inline void write_zsdata(struct uart_pmac_port *port, u8 data)
 104{
 105        writeb(data, port->data_reg);
 106}
 107
 108static inline void zssync(struct uart_pmac_port *port)
 109{
 110        (void)readb(port->control_reg);
 111}
 112
 113/* Conversion routines to/from brg time constants from/to bits
 114 * per second.
 115 */
 116#define BRG_TO_BPS(brg, freq) ((freq) / 2 / ((brg) + 2))
 117#define BPS_TO_BRG(bps, freq) ((((freq) + (bps)) / (2 * (bps))) - 2)
 118
 119#define ZS_CLOCK         3686400        /* Z8530 RTxC input clock rate */
 120
 121/* The Zilog register set */
 122
 123#define FLAG    0x7e
 124
 125/* Write Register 0 */
 126#define R0      0               /* Register selects */
 127#define R1      1
 128#define R2      2
 129#define R3      3
 130#define R4      4
 131#define R5      5
 132#define R6      6
 133#define R7      7
 134#define R8      8
 135#define R9      9
 136#define R10     10
 137#define R11     11
 138#define R12     12
 139#define R13     13
 140#define R14     14
 141#define R15     15
 142#define R7P     16
 143
 144#define NULLCODE        0       /* Null Code */
 145#define POINT_HIGH      0x8     /* Select upper half of registers */
 146#define RES_EXT_INT     0x10    /* Reset Ext. Status Interrupts */
 147#define SEND_ABORT      0x18    /* HDLC Abort */
 148#define RES_RxINT_FC    0x20    /* Reset RxINT on First Character */
 149#define RES_Tx_P        0x28    /* Reset TxINT Pending */
 150#define ERR_RES         0x30    /* Error Reset */
 151#define RES_H_IUS       0x38    /* Reset highest IUS */
 152
 153#define RES_Rx_CRC      0x40    /* Reset Rx CRC Checker */
 154#define RES_Tx_CRC      0x80    /* Reset Tx CRC Checker */
 155#define RES_EOM_L       0xC0    /* Reset EOM latch */
 156
 157/* Write Register 1 */
 158
 159#define EXT_INT_ENAB    0x1     /* Ext Int Enable */
 160#define TxINT_ENAB      0x2     /* Tx Int Enable */
 161#define PAR_SPEC        0x4     /* Parity is special condition */
 162
 163#define RxINT_DISAB     0       /* Rx Int Disable */
 164#define RxINT_FCERR     0x8     /* Rx Int on First Character Only or Error */
 165#define INT_ALL_Rx      0x10    /* Int on all Rx Characters or error */
 166#define INT_ERR_Rx      0x18    /* Int on error only */
 167#define RxINT_MASK      0x18
 168
 169#define WT_RDY_RT       0x20    /* W/Req reflects recv if 1, xmit if 0 */
 170#define WT_FN_RDYFN     0x40    /* W/Req pin is DMA request if 1, wait if 0 */
 171#define WT_RDY_ENAB     0x80    /* Enable W/Req pin */
 172
 173/* Write Register #2 (Interrupt Vector) */
 174
 175/* Write Register 3 */
 176
 177#define RxENABLE        0x1     /* Rx Enable */
 178#define SYNC_L_INH      0x2     /* Sync Character Load Inhibit */
 179#define ADD_SM          0x4     /* Address Search Mode (SDLC) */
 180#define RxCRC_ENAB      0x8     /* Rx CRC Enable */
 181#define ENT_HM          0x10    /* Enter Hunt Mode */
 182#define AUTO_ENAB       0x20    /* Auto Enables */
 183#define Rx5             0x0     /* Rx 5 Bits/Character */
 184#define Rx7             0x40    /* Rx 7 Bits/Character */
 185#define Rx6             0x80    /* Rx 6 Bits/Character */
 186#define Rx8             0xc0    /* Rx 8 Bits/Character */
 187#define RxN_MASK        0xc0
 188
 189/* Write Register 4 */
 190
 191#define PAR_ENAB        0x1     /* Parity Enable */
 192#define PAR_EVEN        0x2     /* Parity Even/Odd* */
 193
 194#define SYNC_ENAB       0       /* Sync Modes Enable */
 195#define SB1             0x4     /* 1 stop bit/char */
 196#define SB15            0x8     /* 1.5 stop bits/char */
 197#define SB2             0xc     /* 2 stop bits/char */
 198#define SB_MASK         0xc
 199
 200#define MONSYNC         0       /* 8 Bit Sync character */
 201#define BISYNC          0x10    /* 16 bit sync character */
 202#define SDLC            0x20    /* SDLC Mode (01111110 Sync Flag) */
 203#define EXTSYNC         0x30    /* External Sync Mode */
 204
 205#define X1CLK           0x0     /* x1 clock mode */
 206#define X16CLK          0x40    /* x16 clock mode */
 207#define X32CLK          0x80    /* x32 clock mode */
 208#define X64CLK          0xC0    /* x64 clock mode */
 209#define XCLK_MASK       0xC0
 210
 211/* Write Register 5 */
 212
 213#define TxCRC_ENAB      0x1     /* Tx CRC Enable */
 214#define RTS             0x2     /* RTS */
 215#define SDLC_CRC        0x4     /* SDLC/CRC-16 */
 216#define TxENABLE        0x8     /* Tx Enable */
 217#define SND_BRK         0x10    /* Send Break */
 218#define Tx5             0x0     /* Tx 5 bits (or less)/character */
 219#define Tx7             0x20    /* Tx 7 bits/character */
 220#define Tx6             0x40    /* Tx 6 bits/character */
 221#define Tx8             0x60    /* Tx 8 bits/character */
 222#define TxN_MASK        0x60
 223#define DTR             0x80    /* DTR */
 224
 225/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
 226
 227/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
 228
 229/* Write Register 7' (Some enhanced feature control) */
 230#define ENEXREAD        0x40    /* Enable read of some write registers */
 231
 232/* Write Register 8 (transmit buffer) */
 233
 234/* Write Register 9 (Master interrupt control) */
 235#define VIS     1       /* Vector Includes Status */
 236#define NV      2       /* No Vector */
 237#define DLC     4       /* Disable Lower Chain */
 238#define MIE     8       /* Master Interrupt Enable */
 239#define STATHI  0x10    /* Status high */
 240#define NORESET 0       /* No reset on write to R9 */
 241#define CHRB    0x40    /* Reset channel B */
 242#define CHRA    0x80    /* Reset channel A */
 243#define FHWRES  0xc0    /* Force hardware reset */
 244
 245/* Write Register 10 (misc control bits) */
 246#define BIT6    1       /* 6 bit/8bit sync */
 247#define LOOPMODE 2      /* SDLC Loop mode */
 248#define ABUNDER 4       /* Abort/flag on SDLC xmit underrun */
 249#define MARKIDLE 8      /* Mark/flag on idle */
 250#define GAOP    0x10    /* Go active on poll */
 251#define NRZ     0       /* NRZ mode */
 252#define NRZI    0x20    /* NRZI mode */
 253#define FM1     0x40    /* FM1 (transition = 1) */
 254#define FM0     0x60    /* FM0 (transition = 0) */
 255#define CRCPS   0x80    /* CRC Preset I/O */
 256
 257/* Write Register 11 (Clock Mode control) */
 258#define TRxCXT  0       /* TRxC = Xtal output */
 259#define TRxCTC  1       /* TRxC = Transmit clock */
 260#define TRxCBR  2       /* TRxC = BR Generator Output */
 261#define TRxCDP  3       /* TRxC = DPLL output */
 262#define TRxCOI  4       /* TRxC O/I */
 263#define TCRTxCP 0       /* Transmit clock = RTxC pin */
 264#define TCTRxCP 8       /* Transmit clock = TRxC pin */
 265#define TCBR    0x10    /* Transmit clock = BR Generator output */
 266#define TCDPLL  0x18    /* Transmit clock = DPLL output */
 267#define RCRTxCP 0       /* Receive clock = RTxC pin */
 268#define RCTRxCP 0x20    /* Receive clock = TRxC pin */
 269#define RCBR    0x40    /* Receive clock = BR Generator output */
 270#define RCDPLL  0x60    /* Receive clock = DPLL output */
 271#define RTxCX   0x80    /* RTxC Xtal/No Xtal */
 272
 273/* Write Register 12 (lower byte of baud rate generator time constant) */
 274
 275/* Write Register 13 (upper byte of baud rate generator time constant) */
 276
 277/* Write Register 14 (Misc control bits) */
 278#define BRENAB  1       /* Baud rate generator enable */
 279#define BRSRC   2       /* Baud rate generator source */
 280#define DTRREQ  4       /* DTR/Request function */
 281#define AUTOECHO 8      /* Auto Echo */
 282#define LOOPBAK 0x10    /* Local loopback */
 283#define SEARCH  0x20    /* Enter search mode */
 284#define RMC     0x40    /* Reset missing clock */
 285#define DISDPLL 0x60    /* Disable DPLL */
 286#define SSBR    0x80    /* Set DPLL source = BR generator */
 287#define SSRTxC  0xa0    /* Set DPLL source = RTxC */
 288#define SFMM    0xc0    /* Set FM mode */
 289#define SNRZI   0xe0    /* Set NRZI mode */
 290
 291/* Write Register 15 (external/status interrupt control) */
 292#define EN85C30 1       /* Enable some 85c30-enhanced registers */
 293#define ZCIE    2       /* Zero count IE */
 294#define ENSTFIFO 4      /* Enable status FIFO (SDLC) */
 295#define DCDIE   8       /* DCD IE */
 296#define SYNCIE  0x10    /* Sync/hunt IE */
 297#define CTSIE   0x20    /* CTS IE */
 298#define TxUIE   0x40    /* Tx Underrun/EOM IE */
 299#define BRKIE   0x80    /* Break/Abort IE */
 300
 301
 302/* Read Register 0 */
 303#define Rx_CH_AV        0x1     /* Rx Character Available */
 304#define ZCOUNT          0x2     /* Zero count */
 305#define Tx_BUF_EMP      0x4     /* Tx Buffer empty */
 306#define DCD             0x8     /* DCD */
 307#define SYNC_HUNT       0x10    /* Sync/hunt */
 308#define CTS             0x20    /* CTS */
 309#define TxEOM           0x40    /* Tx underrun */
 310#define BRK_ABRT        0x80    /* Break/Abort */
 311
 312/* Read Register 1 */
 313#define ALL_SNT         0x1     /* All sent */
 314/* Residue Data for 8 Rx bits/char programmed */
 315#define RES3            0x8     /* 0/3 */
 316#define RES4            0x4     /* 0/4 */
 317#define RES5            0xc     /* 0/5 */
 318#define RES6            0x2     /* 0/6 */
 319#define RES7            0xa     /* 0/7 */
 320#define RES8            0x6     /* 0/8 */
 321#define RES18           0xe     /* 1/8 */
 322#define RES28           0x0     /* 2/8 */
 323/* Special Rx Condition Interrupts */
 324#define PAR_ERR         0x10    /* Parity error */
 325#define Rx_OVR          0x20    /* Rx Overrun Error */
 326#define CRC_ERR         0x40    /* CRC/Framing Error */
 327#define END_FR          0x80    /* End of Frame (SDLC) */
 328
 329/* Read Register 2 (channel b only) - Interrupt vector */
 330#define CHB_Tx_EMPTY    0x00
 331#define CHB_EXT_STAT    0x02
 332#define CHB_Rx_AVAIL    0x04
 333#define CHB_SPECIAL     0x06
 334#define CHA_Tx_EMPTY    0x08
 335#define CHA_EXT_STAT    0x0a
 336#define CHA_Rx_AVAIL    0x0c
 337#define CHA_SPECIAL     0x0e
 338#define STATUS_MASK     0x06
 339
 340/* Read Register 3 (interrupt pending register) ch a only */
 341#define CHBEXT  0x1             /* Channel B Ext/Stat IP */
 342#define CHBTxIP 0x2             /* Channel B Tx IP */
 343#define CHBRxIP 0x4             /* Channel B Rx IP */
 344#define CHAEXT  0x8             /* Channel A Ext/Stat IP */
 345#define CHATxIP 0x10            /* Channel A Tx IP */
 346#define CHARxIP 0x20            /* Channel A Rx IP */
 347
 348/* Read Register 8 (receive data register) */
 349
 350/* Read Register 10  (misc status bits) */
 351#define ONLOOP  2               /* On loop */
 352#define LOOPSEND 0x10           /* Loop sending */
 353#define CLK2MIS 0x40            /* Two clocks missing */
 354#define CLK1MIS 0x80            /* One clock missing */
 355
 356/* Read Register 12 (lower byte of baud rate generator constant) */
 357
 358/* Read Register 13 (upper byte of baud rate generator constant) */
 359
 360/* Read Register 15 (value of WR 15) */
 361
 362/* Misc macros */
 363#define ZS_CLEARERR(port)    (write_zsreg(port, 0, ERR_RES))
 364#define ZS_CLEARFIFO(port)   do { volatile unsigned char garbage; \
 365                                     garbage = read_zsdata(port); \
 366                                     garbage = read_zsdata(port); \
 367                                     garbage = read_zsdata(port); \
 368                                } while(0)
 369
 370#define ZS_IS_CONS(UP)                  ((UP)->flags & PMACZILOG_FLAG_IS_CONS)
 371#define ZS_IS_KGDB(UP)                  ((UP)->flags & PMACZILOG_FLAG_IS_KGDB)
 372#define ZS_IS_CHANNEL_A(UP)             ((UP)->flags & PMACZILOG_FLAG_IS_CHANNEL_A)
 373#define ZS_REGS_HELD(UP)                ((UP)->flags & PMACZILOG_FLAG_REGS_HELD)
 374#define ZS_TX_STOPPED(UP)               ((UP)->flags & PMACZILOG_FLAG_TX_STOPPED)
 375#define ZS_TX_ACTIVE(UP)                ((UP)->flags & PMACZILOG_FLAG_TX_ACTIVE)
 376#define ZS_WANTS_MODEM_STATUS(UP)       ((UP)->flags & PMACZILOG_FLAG_MODEM_STATUS)
 377#define ZS_IS_IRDA(UP)                  ((UP)->flags & PMACZILOG_FLAG_IS_IRDA)
 378#define ZS_IS_INTMODEM(UP)              ((UP)->flags & PMACZILOG_FLAG_IS_INTMODEM)
 379#define ZS_HAS_DMA(UP)                  ((UP)->flags & PMACZILOG_FLAG_HAS_DMA)
 380#define ZS_IS_OPEN(UP)                  ((UP)->flags & PMACZILOG_FLAG_IS_OPEN)
 381#define ZS_IS_EXTCLK(UP)                ((UP)->flags & PMACZILOG_FLAG_IS_EXTCLK)
 382
 383#endif /* __PMAC_ZILOG_H__ */
 384
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