LXR linux/drivers/tty/serial/stm32-usart.h

   1/*
   2 * Copyright (C) Maxime Coquelin 2015
   3 * Authors:  Maxime Coquelin <mcoquelin.stm32@gmail.com>
   4 *           Gerald Baeza <gerald_baeza@yahoo.fr>
   5 * License terms:  GNU General Public License (GPL), version 2
   6 */
   7
   8#define DRIVER_NAME "stm32-usart"
   9
  10struct stm32_usart_offsets {
  11        u8 cr1;
  12        u8 cr2;
  13        u8 cr3;
  14        u8 brr;
  15        u8 gtpr;
  16        u8 rtor;
  17        u8 rqr;
  18        u8 isr;
  19        u8 icr;
  20        u8 rdr;
  21        u8 tdr;
  22};
  23
  24struct stm32_usart_config {
  25        u8 uart_enable_bit; /* USART_CR1_UE */
  26        bool has_7bits_data;
  27};
  28
  29struct stm32_usart_info {
  30        struct stm32_usart_offsets ofs;
  31        struct stm32_usart_config cfg;
  32};
  33
  34#define UNDEF_REG 0xff
  35
  36/* Register offsets */
  37struct stm32_usart_info stm32f4_info = {
  38        .ofs = {
  39                .isr    = 0x00,
  40                .rdr    = 0x04,
  41                .tdr    = 0x04,
  42                .brr    = 0x08,
  43                .cr1    = 0x0c,
  44                .cr2    = 0x10,
  45                .cr3    = 0x14,
  46                .gtpr   = 0x18,
  47                .rtor   = UNDEF_REG,
  48                .rqr    = UNDEF_REG,
  49                .icr    = UNDEF_REG,
  50        },
  51        .cfg = {
  52                .uart_enable_bit = 13,
  53                .has_7bits_data = false,
  54        }
  55};
  56
  57struct stm32_usart_info stm32f7_info = {
  58        .ofs = {
  59                .cr1    = 0x00,
  60                .cr2    = 0x04,
  61                .cr3    = 0x08,
  62                .brr    = 0x0c,
  63                .gtpr   = 0x10,
  64                .rtor   = 0x14,
  65                .rqr    = 0x18,
  66                .isr    = 0x1c,
  67                .icr    = 0x20,
  68                .rdr    = 0x24,
  69                .tdr    = 0x28,
  70        },
  71        .cfg = {
  72                .uart_enable_bit = 0,
  73                .has_7bits_data = true,
  74        }
  75};
  76
  77/* USART_SR (F4) / USART_ISR (F7) */
  78#define USART_SR_PE             BIT(0)
  79#define USART_SR_FE             BIT(1)
  80#define USART_SR_NF             BIT(2)
  81#define USART_SR_ORE            BIT(3)
  82#define USART_SR_IDLE           BIT(4)
  83#define USART_SR_RXNE           BIT(5)
  84#define USART_SR_TC             BIT(6)
  85#define USART_SR_TXE            BIT(7)
  86#define USART_SR_LBD            BIT(8)
  87#define USART_SR_CTSIF          BIT(9)
  88#define USART_SR_CTS            BIT(10)         /* F7 */
  89#define USART_SR_RTOF           BIT(11)         /* F7 */
  90#define USART_SR_EOBF           BIT(12)         /* F7 */
  91#define USART_SR_ABRE           BIT(14)         /* F7 */
  92#define USART_SR_ABRF           BIT(15)         /* F7 */
  93#define USART_SR_BUSY           BIT(16)         /* F7 */
  94#define USART_SR_CMF            BIT(17)         /* F7 */
  95#define USART_SR_SBKF           BIT(18)         /* F7 */
  96#define USART_SR_TEACK          BIT(21)         /* F7 */
  97#define USART_SR_ERR_MASK       (USART_SR_LBD | USART_SR_ORE | \
  98                                 USART_SR_FE | USART_SR_PE)
  99/* Dummy bits */
 100#define USART_SR_DUMMY_RX       BIT(16)
 101
 102/* USART_ICR (F7) */
 103#define USART_CR_TC             BIT(6)
 104
 105/* USART_DR */
 106#define USART_DR_MASK           GENMASK(8, 0)
 107
 108/* USART_BRR */
 109#define USART_BRR_DIV_F_MASK    GENMASK(3, 0)
 110#define USART_BRR_DIV_M_MASK    GENMASK(15, 4)
 111#define USART_BRR_DIV_M_SHIFT   4
 112
 113/* USART_CR1 */
 114#define USART_CR1_SBK           BIT(0)
 115#define USART_CR1_RWU           BIT(1)          /* F4 */
 116#define USART_CR1_RE            BIT(2)
 117#define USART_CR1_TE            BIT(3)
 118#define USART_CR1_IDLEIE        BIT(4)
 119#define USART_CR1_RXNEIE        BIT(5)
 120#define USART_CR1_TCIE          BIT(6)
 121#define USART_CR1_TXEIE         BIT(7)
 122#define USART_CR1_PEIE          BIT(8)
 123#define USART_CR1_PS            BIT(9)
 124#define USART_CR1_PCE           BIT(10)
 125#define USART_CR1_WAKE          BIT(11)
 126#define USART_CR1_M             BIT(12)
 127#define USART_CR1_M0            BIT(12)         /* F7 */
 128#define USART_CR1_MME           BIT(13)         /* F7 */
 129#define USART_CR1_CMIE          BIT(14)         /* F7 */
 130#define USART_CR1_OVER8         BIT(15)
 131#define USART_CR1_DEDT_MASK     GENMASK(20, 16) /* F7 */
 132#define USART_CR1_DEAT_MASK     GENMASK(25, 21) /* F7 */
 133#define USART_CR1_RTOIE         BIT(26)         /* F7 */
 134#define USART_CR1_EOBIE         BIT(27)         /* F7 */
 135#define USART_CR1_M1            BIT(28)         /* F7 */
 136#define USART_CR1_IE_MASK       (GENMASK(8, 4) | BIT(14) | BIT(26) | BIT(27))
 137
 138/* USART_CR2 */
 139#define USART_CR2_ADD_MASK      GENMASK(3, 0)   /* F4 */
 140#define USART_CR2_ADDM7         BIT(4)          /* F7 */
 141#define USART_CR2_LBDL          BIT(5)
 142#define USART_CR2_LBDIE         BIT(6)
 143#define USART_CR2_LBCL          BIT(8)
 144#define USART_CR2_CPHA          BIT(9)
 145#define USART_CR2_CPOL          BIT(10)
 146#define USART_CR2_CLKEN         BIT(11)
 147#define USART_CR2_STOP_2B       BIT(13)
 148#define USART_CR2_STOP_MASK     GENMASK(13, 12)
 149#define USART_CR2_LINEN         BIT(14)
 150#define USART_CR2_SWAP          BIT(15)         /* F7 */
 151#define USART_CR2_RXINV         BIT(16)         /* F7 */
 152#define USART_CR2_TXINV         BIT(17)         /* F7 */
 153#define USART_CR2_DATAINV       BIT(18)         /* F7 */
 154#define USART_CR2_MSBFIRST      BIT(19)         /* F7 */
 155#define USART_CR2_ABREN         BIT(20)         /* F7 */
 156#define USART_CR2_ABRMOD_MASK   GENMASK(22, 21) /* F7 */
 157#define USART_CR2_RTOEN         BIT(23)         /* F7 */
 158#define USART_CR2_ADD_F7_MASK   GENMASK(31, 24) /* F7 */
 159
 160/* USART_CR3 */
 161#define USART_CR3_EIE           BIT(0)
 162#define USART_CR3_IREN          BIT(1)
 163#define USART_CR3_IRLP          BIT(2)
 164#define USART_CR3_HDSEL         BIT(3)
 165#define USART_CR3_NACK          BIT(4)
 166#define USART_CR3_SCEN          BIT(5)
 167#define USART_CR3_DMAR          BIT(6)
 168#define USART_CR3_DMAT          BIT(7)
 169#define USART_CR3_RTSE          BIT(8)
 170#define USART_CR3_CTSE          BIT(9)
 171#define USART_CR3_CTSIE         BIT(10)
 172#define USART_CR3_ONEBIT        BIT(11)
 173#define USART_CR3_OVRDIS        BIT(12)         /* F7 */
 174#define USART_CR3_DDRE          BIT(13)         /* F7 */
 175#define USART_CR3_DEM           BIT(14)         /* F7 */
 176#define USART_CR3_DEP           BIT(15)         /* F7 */
 177#define USART_CR3_SCARCNT_MASK  GENMASK(19, 17) /* F7 */
 178
 179/* USART_GTPR */
 180#define USART_GTPR_PSC_MASK     GENMASK(7, 0)
 181#define USART_GTPR_GT_MASK      GENMASK(15, 8)
 182
 183/* USART_RTOR */
 184#define USART_RTOR_RTO_MASK     GENMASK(23, 0)  /* F7 */
 185#define USART_RTOR_BLEN_MASK    GENMASK(31, 24) /* F7 */
 186
 187/* USART_RQR */
 188#define USART_RQR_ABRRQ         BIT(0)          /* F7 */
 189#define USART_RQR_SBKRQ         BIT(1)          /* F7 */
 190#define USART_RQR_MMRQ          BIT(2)          /* F7 */
 191#define USART_RQR_RXFRQ         BIT(3)          /* F7 */
 192#define USART_RQR_TXFRQ         BIT(4)          /* F7 */
 193
 194/* USART_ICR */
 195#define USART_ICR_PECF          BIT(0)          /* F7 */
 196#define USART_ICR_FFECF         BIT(1)          /* F7 */
 197#define USART_ICR_NCF           BIT(2)          /* F7 */
 198#define USART_ICR_ORECF         BIT(3)          /* F7 */
 199#define USART_ICR_IDLECF        BIT(4)          /* F7 */
 200#define USART_ICR_TCCF          BIT(6)          /* F7 */
 201#define USART_ICR_LBDCF         BIT(8)          /* F7 */
 202#define USART_ICR_CTSCF         BIT(9)          /* F7 */
 203#define USART_ICR_RTOCF         BIT(11)         /* F7 */
 204#define USART_ICR_EOBCF         BIT(12)         /* F7 */
 205#define USART_ICR_CMCF          BIT(17)         /* F7 */
 206
 207#define STM32_SERIAL_NAME "ttyS"
 208#define STM32_MAX_PORTS 6
 209
 210#define RX_BUF_L 200             /* dma rx buffer length     */
 211#define RX_BUF_P RX_BUF_L        /* dma rx buffer period     */
 212#define TX_BUF_L 200             /* dma tx buffer length     */
 213
 214struct stm32_port {
 215        struct uart_port port;
 216        struct clk *clk;
 217        struct stm32_usart_info *info;
 218        struct dma_chan *rx_ch;  /* dma rx channel            */
 219        dma_addr_t rx_dma_buf;   /* dma rx buffer bus address */
 220        unsigned char *rx_buf;   /* dma rx buffer cpu address */
 221        struct dma_chan *tx_ch;  /* dma tx channel            */
 222        dma_addr_t tx_dma_buf;   /* dma tx buffer bus address */
 223        unsigned char *tx_buf;   /* dma tx buffer cpu address */
 224        bool tx_dma_busy;        /* dma tx busy               */
 225        bool hw_flow_control;
 226};
 227
 228static struct stm32_port stm32_ports[STM32_MAX_PORTS];
 229static struct uart_driver stm32_usart_driver;
 230