1
2
3
4
5
6
7
8
9
10
11#include <linux/types.h>
12#include <linux/kernel.h>
13#include <linux/pci.h>
14#include <linux/delay.h>
15#include <linux/export.h>
16#include <linux/acpi.h>
17#include <linux/dmi.h>
18#include "pci-quirks.h"
19#include "xhci-ext-caps.h"
20
21
22#define UHCI_USBLEGSUP 0xc0
23#define UHCI_USBCMD 0
24#define UHCI_USBINTR 4
25#define UHCI_USBLEGSUP_RWC 0x8f00
26#define UHCI_USBLEGSUP_RO 0x5040
27#define UHCI_USBCMD_RUN 0x0001
28#define UHCI_USBCMD_HCRESET 0x0002
29#define UHCI_USBCMD_EGSM 0x0008
30#define UHCI_USBCMD_CONFIGURE 0x0040
31#define UHCI_USBINTR_RESUME 0x0002
32
33#define OHCI_CONTROL 0x04
34#define OHCI_CMDSTATUS 0x08
35#define OHCI_INTRSTATUS 0x0c
36#define OHCI_INTRENABLE 0x10
37#define OHCI_INTRDISABLE 0x14
38#define OHCI_FMINTERVAL 0x34
39#define OHCI_HCFS (3 << 6)
40#define OHCI_HCR (1 << 0)
41#define OHCI_OCR (1 << 3)
42#define OHCI_CTRL_RWC (1 << 9)
43#define OHCI_CTRL_IR (1 << 8)
44#define OHCI_INTR_OC (1 << 30)
45
46#define EHCI_HCC_PARAMS 0x08
47#define EHCI_USBCMD 0
48#define EHCI_USBCMD_RUN (1 << 0)
49#define EHCI_USBSTS 4
50#define EHCI_USBSTS_HALTED (1 << 12)
51#define EHCI_USBINTR 8
52#define EHCI_CONFIGFLAG 0x40
53#define EHCI_USBLEGSUP 0
54#define EHCI_USBLEGSUP_BIOS (1 << 16)
55#define EHCI_USBLEGSUP_OS (1 << 24)
56#define EHCI_USBLEGCTLSTS 4
57#define EHCI_USBLEGCTLSTS_SOOE (1 << 13)
58
59
60#define AB_REG_BAR_LOW 0xe0
61#define AB_REG_BAR_HIGH 0xe1
62#define AB_REG_BAR_SB700 0xf0
63#define AB_INDX(addr) ((addr) + 0x00)
64#define AB_DATA(addr) ((addr) + 0x04)
65#define AX_INDXC 0x30
66#define AX_DATAC 0x34
67
68#define NB_PCIE_INDX_ADDR 0xe0
69#define NB_PCIE_INDX_DATA 0xe4
70#define PCIE_P_CNTL 0x10040
71#define BIF_NB 0x10002
72#define NB_PIF0_PWRDOWN_0 0x01100012
73#define NB_PIF0_PWRDOWN_1 0x01100013
74
75#define USB_INTEL_XUSB2PR 0xD0
76#define USB_INTEL_USB2PRM 0xD4
77#define USB_INTEL_USB3_PSSEN 0xD8
78#define USB_INTEL_USB3PRM 0xDC
79
80
81#define ASMT_DATA_WRITE0_REG 0xF8
82#define ASMT_DATA_WRITE1_REG 0xFC
83#define ASMT_CONTROL_REG 0xE0
84#define ASMT_CONTROL_WRITE_BIT 0x02
85#define ASMT_WRITEREG_CMD 0x10423
86#define ASMT_FLOWCTL_ADDR 0xFA30
87#define ASMT_FLOWCTL_DATA 0xBA
88#define ASMT_PSEUDO_DATA 0
89
90
91
92
93enum amd_chipset_gen {
94 NOT_AMD_CHIPSET = 0,
95 AMD_CHIPSET_SB600,
96 AMD_CHIPSET_SB700,
97 AMD_CHIPSET_SB800,
98 AMD_CHIPSET_HUDSON2,
99 AMD_CHIPSET_BOLTON,
100 AMD_CHIPSET_YANGTZE,
101 AMD_CHIPSET_TAISHAN,
102 AMD_CHIPSET_UNKNOWN,
103};
104
105struct amd_chipset_type {
106 enum amd_chipset_gen gen;
107 u8 rev;
108};
109
110static struct amd_chipset_info {
111 struct pci_dev *nb_dev;
112 struct pci_dev *smbus_dev;
113 int nb_type;
114 struct amd_chipset_type sb_type;
115 int isoc_reqs;
116 int probe_count;
117 int probe_result;
118} amd_chipset;
119
120static DEFINE_SPINLOCK(amd_lock);
121
122
123
124
125
126
127
128
129
130static int amd_chipset_sb_type_init(struct amd_chipset_info *pinfo)
131{
132 u8 rev = 0;
133 pinfo->sb_type.gen = AMD_CHIPSET_UNKNOWN;
134
135 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_ATI,
136 PCI_DEVICE_ID_ATI_SBX00_SMBUS, NULL);
137 if (pinfo->smbus_dev) {
138 rev = pinfo->smbus_dev->revision;
139 if (rev >= 0x10 && rev <= 0x1f)
140 pinfo->sb_type.gen = AMD_CHIPSET_SB600;
141 else if (rev >= 0x30 && rev <= 0x3f)
142 pinfo->sb_type.gen = AMD_CHIPSET_SB700;
143 else if (rev >= 0x40 && rev <= 0x4f)
144 pinfo->sb_type.gen = AMD_CHIPSET_SB800;
145 }
146 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
147 0x145c, NULL);
148 if (pinfo->smbus_dev) {
149 pinfo->sb_type.gen = AMD_CHIPSET_TAISHAN;
150 } else {
151 pinfo->smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD,
152 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL);
153
154 if (!pinfo->smbus_dev) {
155 pinfo->sb_type.gen = NOT_AMD_CHIPSET;
156 return 0;
157 }
158
159 rev = pinfo->smbus_dev->revision;
160 if (rev >= 0x11 && rev <= 0x14)
161 pinfo->sb_type.gen = AMD_CHIPSET_HUDSON2;
162 else if (rev >= 0x15 && rev <= 0x18)
163 pinfo->sb_type.gen = AMD_CHIPSET_BOLTON;
164 else if (rev >= 0x39 && rev <= 0x3a)
165 pinfo->sb_type.gen = AMD_CHIPSET_YANGTZE;
166 }
167
168 pinfo->sb_type.rev = rev;
169 return 1;
170}
171
172void sb800_prefetch(struct device *dev, int on)
173{
174 u16 misc;
175 struct pci_dev *pdev = to_pci_dev(dev);
176
177 pci_read_config_word(pdev, 0x50, &misc);
178 if (on == 0)
179 pci_write_config_word(pdev, 0x50, misc & 0xfcff);
180 else
181 pci_write_config_word(pdev, 0x50, misc | 0x0300);
182}
183EXPORT_SYMBOL_GPL(sb800_prefetch);
184
185int usb_amd_find_chipset_info(void)
186{
187 unsigned long flags;
188 struct amd_chipset_info info;
189 int ret;
190
191 spin_lock_irqsave(&amd_lock, flags);
192
193
194 if (amd_chipset.probe_count > 0) {
195 amd_chipset.probe_count++;
196 spin_unlock_irqrestore(&amd_lock, flags);
197 return amd_chipset.probe_result;
198 }
199 memset(&info, 0, sizeof(info));
200 spin_unlock_irqrestore(&amd_lock, flags);
201
202 if (!amd_chipset_sb_type_init(&info)) {
203 ret = 0;
204 goto commit;
205 }
206
207
208 if (info.sb_type.gen == AMD_CHIPSET_UNKNOWN ||
209 info.sb_type.gen == AMD_CHIPSET_SB600 ||
210 info.sb_type.gen == AMD_CHIPSET_YANGTZE ||
211 (info.sb_type.gen == AMD_CHIPSET_SB700 &&
212 info.sb_type.rev > 0x3b)) {
213 if (info.smbus_dev) {
214 pci_dev_put(info.smbus_dev);
215 info.smbus_dev = NULL;
216 }
217 ret = 0;
218 goto commit;
219 }
220
221 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x9601, NULL);
222 if (info.nb_dev) {
223 info.nb_type = 1;
224 } else {
225 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD, 0x1510, NULL);
226 if (info.nb_dev) {
227 info.nb_type = 2;
228 } else {
229 info.nb_dev = pci_get_device(PCI_VENDOR_ID_AMD,
230 0x9600, NULL);
231 if (info.nb_dev)
232 info.nb_type = 3;
233 }
234 }
235
236 ret = info.probe_result = 1;
237 printk(KERN_DEBUG "QUIRK: Enable AMD PLL fix\n");
238
239commit:
240
241 spin_lock_irqsave(&amd_lock, flags);
242 if (amd_chipset.probe_count > 0) {
243
244
245
246 amd_chipset.probe_count++;
247 ret = amd_chipset.probe_result;
248
249 spin_unlock_irqrestore(&amd_lock, flags);
250
251 pci_dev_put(info.nb_dev);
252 pci_dev_put(info.smbus_dev);
253
254 } else {
255
256 info.probe_count++;
257 amd_chipset = info;
258 spin_unlock_irqrestore(&amd_lock, flags);
259 }
260
261 return ret;
262}
263EXPORT_SYMBOL_GPL(usb_amd_find_chipset_info);
264
265int usb_hcd_amd_remote_wakeup_quirk(struct pci_dev *pdev)
266{
267
268 usb_amd_find_chipset_info();
269 if (amd_chipset.sb_type.gen == AMD_CHIPSET_YANGTZE ||
270 amd_chipset.sb_type.gen == AMD_CHIPSET_TAISHAN) {
271 dev_dbg(&pdev->dev, "QUIRK: Enable AMD remote wakeup fix\n");
272 return 1;
273 }
274 return 0;
275}
276EXPORT_SYMBOL_GPL(usb_hcd_amd_remote_wakeup_quirk);
277
278bool usb_amd_hang_symptom_quirk(void)
279{
280 u8 rev;
281
282 usb_amd_find_chipset_info();
283 rev = amd_chipset.sb_type.rev;
284
285 return amd_chipset.sb_type.gen == AMD_CHIPSET_SB600 ||
286 (amd_chipset.sb_type.gen == AMD_CHIPSET_SB700 &&
287 rev >= 0x3a && rev <= 0x3b);
288}
289EXPORT_SYMBOL_GPL(usb_amd_hang_symptom_quirk);
290
291bool usb_amd_prefetch_quirk(void)
292{
293 usb_amd_find_chipset_info();
294
295 return amd_chipset.sb_type.gen == AMD_CHIPSET_SB800;
296}
297EXPORT_SYMBOL_GPL(usb_amd_prefetch_quirk);
298
299
300
301
302
303
304
305
306
307
308
309static void usb_amd_quirk_pll(int disable)
310{
311 u32 addr, addr_low, addr_high, val;
312 u32 bit = disable ? 0 : 1;
313 unsigned long flags;
314
315 spin_lock_irqsave(&amd_lock, flags);
316
317 if (disable) {
318 amd_chipset.isoc_reqs++;
319 if (amd_chipset.isoc_reqs > 1) {
320 spin_unlock_irqrestore(&amd_lock, flags);
321 return;
322 }
323 } else {
324 amd_chipset.isoc_reqs--;
325 if (amd_chipset.isoc_reqs > 0) {
326 spin_unlock_irqrestore(&amd_lock, flags);
327 return;
328 }
329 }
330
331 if (amd_chipset.sb_type.gen == AMD_CHIPSET_SB800 ||
332 amd_chipset.sb_type.gen == AMD_CHIPSET_HUDSON2 ||
333 amd_chipset.sb_type.gen == AMD_CHIPSET_BOLTON) {
334 outb_p(AB_REG_BAR_LOW, 0xcd6);
335 addr_low = inb_p(0xcd7);
336 outb_p(AB_REG_BAR_HIGH, 0xcd6);
337 addr_high = inb_p(0xcd7);
338 addr = addr_high << 8 | addr_low;
339
340 outl_p(0x30, AB_INDX(addr));
341 outl_p(0x40, AB_DATA(addr));
342 outl_p(0x34, AB_INDX(addr));
343 val = inl_p(AB_DATA(addr));
344 } else if (amd_chipset.sb_type.gen == AMD_CHIPSET_SB700 &&
345 amd_chipset.sb_type.rev <= 0x3b) {
346 pci_read_config_dword(amd_chipset.smbus_dev,
347 AB_REG_BAR_SB700, &addr);
348 outl(AX_INDXC, AB_INDX(addr));
349 outl(0x40, AB_DATA(addr));
350 outl(AX_DATAC, AB_INDX(addr));
351 val = inl(AB_DATA(addr));
352 } else {
353 spin_unlock_irqrestore(&amd_lock, flags);
354 return;
355 }
356
357 if (disable) {
358 val &= ~0x08;
359 val |= (1 << 4) | (1 << 9);
360 } else {
361 val |= 0x08;
362 val &= ~((1 << 4) | (1 << 9));
363 }
364 outl_p(val, AB_DATA(addr));
365
366 if (!amd_chipset.nb_dev) {
367 spin_unlock_irqrestore(&amd_lock, flags);
368 return;
369 }
370
371 if (amd_chipset.nb_type == 1 || amd_chipset.nb_type == 3) {
372 addr = PCIE_P_CNTL;
373 pci_write_config_dword(amd_chipset.nb_dev,
374 NB_PCIE_INDX_ADDR, addr);
375 pci_read_config_dword(amd_chipset.nb_dev,
376 NB_PCIE_INDX_DATA, &val);
377
378 val &= ~(1 | (1 << 3) | (1 << 4) | (1 << 9) | (1 << 12));
379 val |= bit | (bit << 3) | (bit << 12);
380 val |= ((!bit) << 4) | ((!bit) << 9);
381 pci_write_config_dword(amd_chipset.nb_dev,
382 NB_PCIE_INDX_DATA, val);
383
384 addr = BIF_NB;
385 pci_write_config_dword(amd_chipset.nb_dev,
386 NB_PCIE_INDX_ADDR, addr);
387 pci_read_config_dword(amd_chipset.nb_dev,
388 NB_PCIE_INDX_DATA, &val);
389 val &= ~(1 << 8);
390 val |= bit << 8;
391
392 pci_write_config_dword(amd_chipset.nb_dev,
393 NB_PCIE_INDX_DATA, val);
394 } else if (amd_chipset.nb_type == 2) {
395 addr = NB_PIF0_PWRDOWN_0;
396 pci_write_config_dword(amd_chipset.nb_dev,
397 NB_PCIE_INDX_ADDR, addr);
398 pci_read_config_dword(amd_chipset.nb_dev,
399 NB_PCIE_INDX_DATA, &val);
400 if (disable)
401 val &= ~(0x3f << 7);
402 else
403 val |= 0x3f << 7;
404
405 pci_write_config_dword(amd_chipset.nb_dev,
406 NB_PCIE_INDX_DATA, val);
407
408 addr = NB_PIF0_PWRDOWN_1;
409 pci_write_config_dword(amd_chipset.nb_dev,
410 NB_PCIE_INDX_ADDR, addr);
411 pci_read_config_dword(amd_chipset.nb_dev,
412 NB_PCIE_INDX_DATA, &val);
413 if (disable)
414 val &= ~(0x3f << 7);
415 else
416 val |= 0x3f << 7;
417
418 pci_write_config_dword(amd_chipset.nb_dev,
419 NB_PCIE_INDX_DATA, val);
420 }
421
422 spin_unlock_irqrestore(&amd_lock, flags);
423 return;
424}
425
426void usb_amd_quirk_pll_disable(void)
427{
428 usb_amd_quirk_pll(1);
429}
430EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_disable);
431
432static int usb_asmedia_wait_write(struct pci_dev *pdev)
433{
434 unsigned long retry_count;
435 unsigned char value;
436
437 for (retry_count = 1000; retry_count > 0; --retry_count) {
438
439 pci_read_config_byte(pdev, ASMT_CONTROL_REG, &value);
440
441 if (value == 0xff) {
442 dev_err(&pdev->dev, "%s: check_ready ERROR", __func__);
443 return -EIO;
444 }
445
446 if ((value & ASMT_CONTROL_WRITE_BIT) == 0)
447 return 0;
448
449 usleep_range(40, 60);
450 }
451
452 dev_warn(&pdev->dev, "%s: check_write_ready timeout", __func__);
453 return -ETIMEDOUT;
454}
455
456void usb_asmedia_modifyflowcontrol(struct pci_dev *pdev)
457{
458 if (usb_asmedia_wait_write(pdev) != 0)
459 return;
460
461
462 pci_write_config_dword(pdev, ASMT_DATA_WRITE0_REG, ASMT_WRITEREG_CMD);
463 pci_write_config_dword(pdev, ASMT_DATA_WRITE1_REG, ASMT_FLOWCTL_ADDR);
464 pci_write_config_byte(pdev, ASMT_CONTROL_REG, ASMT_CONTROL_WRITE_BIT);
465
466 if (usb_asmedia_wait_write(pdev) != 0)
467 return;
468
469
470 pci_write_config_dword(pdev, ASMT_DATA_WRITE0_REG, ASMT_FLOWCTL_DATA);
471 pci_write_config_dword(pdev, ASMT_DATA_WRITE1_REG, ASMT_PSEUDO_DATA);
472 pci_write_config_byte(pdev, ASMT_CONTROL_REG, ASMT_CONTROL_WRITE_BIT);
473}
474EXPORT_SYMBOL_GPL(usb_asmedia_modifyflowcontrol);
475
476void usb_amd_quirk_pll_enable(void)
477{
478 usb_amd_quirk_pll(0);
479}
480EXPORT_SYMBOL_GPL(usb_amd_quirk_pll_enable);
481
482void usb_amd_dev_put(void)
483{
484 struct pci_dev *nb, *smbus;
485 unsigned long flags;
486
487 spin_lock_irqsave(&amd_lock, flags);
488
489 amd_chipset.probe_count--;
490 if (amd_chipset.probe_count > 0) {
491 spin_unlock_irqrestore(&amd_lock, flags);
492 return;
493 }
494
495
496 nb = amd_chipset.nb_dev;
497 smbus = amd_chipset.smbus_dev;
498
499 amd_chipset.nb_dev = NULL;
500 amd_chipset.smbus_dev = NULL;
501 amd_chipset.nb_type = 0;
502 memset(&amd_chipset.sb_type, 0, sizeof(amd_chipset.sb_type));
503 amd_chipset.isoc_reqs = 0;
504 amd_chipset.probe_result = 0;
505
506 spin_unlock_irqrestore(&amd_lock, flags);
507
508 pci_dev_put(nb);
509 pci_dev_put(smbus);
510}
511EXPORT_SYMBOL_GPL(usb_amd_dev_put);
512
513
514
515
516
517void uhci_reset_hc(struct pci_dev *pdev, unsigned long base)
518{
519
520
521
522 pci_write_config_word(pdev, UHCI_USBLEGSUP, UHCI_USBLEGSUP_RWC);
523
524
525
526
527
528
529 outw(UHCI_USBCMD_HCRESET, base + UHCI_USBCMD);
530 mb();
531 udelay(5);
532 if (inw(base + UHCI_USBCMD) & UHCI_USBCMD_HCRESET)
533 dev_warn(&pdev->dev, "HCRESET not completed yet!\n");
534
535
536
537
538 outw(0, base + UHCI_USBINTR);
539 outw(0, base + UHCI_USBCMD);
540}
541EXPORT_SYMBOL_GPL(uhci_reset_hc);
542
543
544
545
546
547
548
549int uhci_check_and_reset_hc(struct pci_dev *pdev, unsigned long base)
550{
551 u16 legsup;
552 unsigned int cmd, intr;
553
554
555
556
557
558
559
560
561
562
563
564 pci_read_config_word(pdev, UHCI_USBLEGSUP, &legsup);
565 if (legsup & ~(UHCI_USBLEGSUP_RO | UHCI_USBLEGSUP_RWC)) {
566 dev_dbg(&pdev->dev, "%s: legsup = 0x%04x\n",
567 __func__, legsup);
568 goto reset_needed;
569 }
570
571 cmd = inw(base + UHCI_USBCMD);
572 if ((cmd & UHCI_USBCMD_RUN) || !(cmd & UHCI_USBCMD_CONFIGURE) ||
573 !(cmd & UHCI_USBCMD_EGSM)) {
574 dev_dbg(&pdev->dev, "%s: cmd = 0x%04x\n",
575 __func__, cmd);
576 goto reset_needed;
577 }
578
579 intr = inw(base + UHCI_USBINTR);
580 if (intr & (~UHCI_USBINTR_RESUME)) {
581 dev_dbg(&pdev->dev, "%s: intr = 0x%04x\n",
582 __func__, intr);
583 goto reset_needed;
584 }
585 return 0;
586
587reset_needed:
588 dev_dbg(&pdev->dev, "Performing full reset\n");
589 uhci_reset_hc(pdev, base);
590 return 1;
591}
592EXPORT_SYMBOL_GPL(uhci_check_and_reset_hc);
593
594static inline int io_type_enabled(struct pci_dev *pdev, unsigned int mask)
595{
596 u16 cmd;
597 return !pci_read_config_word(pdev, PCI_COMMAND, &cmd) && (cmd & mask);
598}
599
600#define pio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_IO)
601#define mmio_enabled(dev) io_type_enabled(dev, PCI_COMMAND_MEMORY)
602
603static void quirk_usb_handoff_uhci(struct pci_dev *pdev)
604{
605 unsigned long base = 0;
606 int i;
607
608 if (!pio_enabled(pdev))
609 return;
610
611 for (i = 0; i < PCI_ROM_RESOURCE; i++)
612 if ((pci_resource_flags(pdev, i) & IORESOURCE_IO)) {
613 base = pci_resource_start(pdev, i);
614 break;
615 }
616
617 if (base)
618 uhci_check_and_reset_hc(pdev, base);
619}
620
621static int mmio_resource_enabled(struct pci_dev *pdev, int idx)
622{
623 return pci_resource_start(pdev, idx) && mmio_enabled(pdev);
624}
625
626static void quirk_usb_handoff_ohci(struct pci_dev *pdev)
627{
628 void __iomem *base;
629 u32 control;
630 u32 fminterval = 0;
631 bool no_fminterval = false;
632 int cnt;
633
634 if (!mmio_resource_enabled(pdev, 0))
635 return;
636
637 base = pci_ioremap_bar(pdev, 0);
638 if (base == NULL)
639 return;
640
641
642
643
644
645 if (pdev->vendor == PCI_VENDOR_ID_AL && pdev->device == 0x5237)
646 no_fminterval = true;
647
648 control = readl(base + OHCI_CONTROL);
649
650
651#ifdef __hppa__
652#define OHCI_CTRL_MASK (OHCI_CTRL_RWC | OHCI_CTRL_IR)
653#else
654#define OHCI_CTRL_MASK OHCI_CTRL_RWC
655
656 if (control & OHCI_CTRL_IR) {
657 int wait_time = 500;
658 writel(OHCI_INTR_OC, base + OHCI_INTRENABLE);
659 writel(OHCI_OCR, base + OHCI_CMDSTATUS);
660 while (wait_time > 0 &&
661 readl(base + OHCI_CONTROL) & OHCI_CTRL_IR) {
662 wait_time -= 10;
663 msleep(10);
664 }
665 if (wait_time <= 0)
666 dev_warn(&pdev->dev,
667 "OHCI: BIOS handoff failed (BIOS bug?) %08x\n",
668 readl(base + OHCI_CONTROL));
669 }
670#endif
671
672
673 writel((u32) ~0, base + OHCI_INTRDISABLE);
674
675
676 if (control & OHCI_HCFS) {
677
678 writel(control & OHCI_CTRL_MASK, base + OHCI_CONTROL);
679 readl(base + OHCI_CONTROL);
680
681
682 msleep(50);
683 }
684
685
686 if (!no_fminterval)
687 fminterval = readl(base + OHCI_FMINTERVAL);
688
689 writel(OHCI_HCR, base + OHCI_CMDSTATUS);
690
691
692 for (cnt = 30; cnt > 0; --cnt) {
693 if ((readl(base + OHCI_CMDSTATUS) & OHCI_HCR) == 0)
694 break;
695 udelay(1);
696 }
697
698 if (!no_fminterval)
699 writel(fminterval, base + OHCI_FMINTERVAL);
700
701
702 iounmap(base);
703}
704
705static const struct dmi_system_id ehci_dmi_nohandoff_table[] = {
706 {
707
708 .matches = {
709 DMI_MATCH(DMI_BOARD_NAME, "EXOPG06411"),
710 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-CE-133"),
711 },
712 },
713 {
714
715 .matches = {
716 DMI_MATCH(DMI_BOARD_NAME, "M11JB"),
717 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"),
718 },
719 },
720 {
721
722 .matches = {
723 DMI_MATCH(DMI_BOARD_NAME, "Ordissimo"),
724 DMI_MATCH(DMI_BIOS_VERSION, "Lucid-"),
725 },
726 },
727 {
728
729 .matches = {
730 DMI_MATCH(DMI_BOARD_VENDOR, "HASEE"),
731 DMI_MATCH(DMI_BOARD_NAME, "E210"),
732 DMI_MATCH(DMI_BIOS_VERSION, "6.00"),
733 },
734 },
735 { }
736};
737
738static void ehci_bios_handoff(struct pci_dev *pdev,
739 void __iomem *op_reg_base,
740 u32 cap, u8 offset)
741{
742 int try_handoff = 1, tried_handoff = 0;
743
744
745
746
747
748
749
750 if (pdev->vendor == 0x8086 && (pdev->device == 0x283a ||
751 pdev->device == 0x27cc)) {
752 if (dmi_check_system(ehci_dmi_nohandoff_table))
753 try_handoff = 0;
754 }
755
756 if (try_handoff && (cap & EHCI_USBLEGSUP_BIOS)) {
757 dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n");
758
759#if 0
760
761
762
763
764
765
766
767
768 pci_read_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, &val);
769 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS,
770 val | EHCI_USBLEGCTLSTS_SOOE);
771#endif
772
773
774
775
776
777 pci_write_config_byte(pdev, offset + 3, 1);
778 }
779
780
781 if (try_handoff) {
782 int msec = 1000;
783 while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
784 tried_handoff = 1;
785 msleep(10);
786 msec -= 10;
787 pci_read_config_dword(pdev, offset, &cap);
788 }
789 }
790
791 if (cap & EHCI_USBLEGSUP_BIOS) {
792
793
794
795 if (try_handoff)
796 dev_warn(&pdev->dev,
797 "EHCI: BIOS handoff failed (BIOS bug?) %08x\n",
798 cap);
799 pci_write_config_byte(pdev, offset + 2, 0);
800 }
801
802
803 pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 0);
804
805
806
807
808 if (tried_handoff)
809 writel(0, op_reg_base + EHCI_CONFIGFLAG);
810}
811
812static void quirk_usb_disable_ehci(struct pci_dev *pdev)
813{
814 void __iomem *base, *op_reg_base;
815 u32 hcc_params, cap, val;
816 u8 offset, cap_length;
817 int wait_time, count = 256/4;
818
819 if (!mmio_resource_enabled(pdev, 0))
820 return;
821
822 base = pci_ioremap_bar(pdev, 0);
823 if (base == NULL)
824 return;
825
826 cap_length = readb(base);
827 op_reg_base = base + cap_length;
828
829
830
831
832
833 hcc_params = readl(base + EHCI_HCC_PARAMS);
834 offset = (hcc_params >> 8) & 0xff;
835 while (offset && --count) {
836 pci_read_config_dword(pdev, offset, &cap);
837
838 switch (cap & 0xff) {
839 case 1:
840 ehci_bios_handoff(pdev, op_reg_base, cap, offset);
841 break;
842 case 0:
843 cap = 0;
844 default:
845 dev_warn(&pdev->dev,
846 "EHCI: unrecognized capability %02x\n",
847 cap & 0xff);
848 }
849 offset = (cap >> 8) & 0xff;
850 }
851 if (!count)
852 dev_printk(KERN_DEBUG, &pdev->dev, "EHCI: capability loop?\n");
853
854
855
856
857 val = readl(op_reg_base + EHCI_USBSTS);
858 if ((val & EHCI_USBSTS_HALTED) == 0) {
859 val = readl(op_reg_base + EHCI_USBCMD);
860 val &= ~EHCI_USBCMD_RUN;
861 writel(val, op_reg_base + EHCI_USBCMD);
862
863 wait_time = 2000;
864 do {
865 writel(0x3f, op_reg_base + EHCI_USBSTS);
866 udelay(100);
867 wait_time -= 100;
868 val = readl(op_reg_base + EHCI_USBSTS);
869 if ((val == ~(u32)0) || (val & EHCI_USBSTS_HALTED)) {
870 break;
871 }
872 } while (wait_time > 0);
873 }
874 writel(0, op_reg_base + EHCI_USBINTR);
875 writel(0x3f, op_reg_base + EHCI_USBSTS);
876
877 iounmap(base);
878}
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893static int handshake(void __iomem *ptr, u32 mask, u32 done,
894 int wait_usec, int delay_usec)
895{
896 u32 result;
897
898 do {
899 result = readl(ptr);
900 result &= mask;
901 if (result == done)
902 return 0;
903 udelay(delay_usec);
904 wait_usec -= delay_usec;
905 } while (wait_usec > 0);
906 return -ETIMEDOUT;
907}
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927void usb_enable_intel_xhci_ports(struct pci_dev *xhci_pdev)
928{
929 u32 ports_available;
930 bool ehci_found = false;
931 struct pci_dev *companion = NULL;
932
933
934
935
936 if (xhci_pdev->subsystem_vendor == PCI_VENDOR_ID_SONY &&
937 xhci_pdev->subsystem_device == 0x90a8)
938 return;
939
940
941 for_each_pci_dev(companion) {
942 if (companion->class == PCI_CLASS_SERIAL_USB_EHCI &&
943 companion->vendor == PCI_VENDOR_ID_INTEL) {
944 ehci_found = true;
945 break;
946 }
947 }
948
949 if (!ehci_found)
950 return;
951
952
953
954
955
956 if (!IS_ENABLED(CONFIG_USB_XHCI_HCD)) {
957 dev_warn(&xhci_pdev->dev,
958 "CONFIG_USB_XHCI_HCD is turned off, defaulting to EHCI.\n");
959 dev_warn(&xhci_pdev->dev,
960 "USB 3.0 devices will work at USB 2.0 speeds.\n");
961 usb_disable_xhci_ports(xhci_pdev);
962 return;
963 }
964
965
966
967
968 pci_read_config_dword(xhci_pdev, USB_INTEL_USB3PRM,
969 &ports_available);
970
971 dev_dbg(&xhci_pdev->dev, "Configurable ports to enable SuperSpeed: 0x%x\n",
972 ports_available);
973
974
975
976
977
978 pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
979 ports_available);
980
981 pci_read_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN,
982 &ports_available);
983 dev_dbg(&xhci_pdev->dev,
984 "USB 3.0 ports that are now enabled under xHCI: 0x%x\n",
985 ports_available);
986
987
988
989
990
991 pci_read_config_dword(xhci_pdev, USB_INTEL_USB2PRM,
992 &ports_available);
993
994 dev_dbg(&xhci_pdev->dev, "Configurable USB 2.0 ports to hand over to xCHI: 0x%x\n",
995 ports_available);
996
997
998
999
1000
1001 pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
1002 ports_available);
1003
1004 pci_read_config_dword(xhci_pdev, USB_INTEL_XUSB2PR,
1005 &ports_available);
1006 dev_dbg(&xhci_pdev->dev,
1007 "USB 2.0 ports that are now switched over to xHCI: 0x%x\n",
1008 ports_available);
1009}
1010EXPORT_SYMBOL_GPL(usb_enable_intel_xhci_ports);
1011
1012void usb_disable_xhci_ports(struct pci_dev *xhci_pdev)
1013{
1014 pci_write_config_dword(xhci_pdev, USB_INTEL_USB3_PSSEN, 0x0);
1015 pci_write_config_dword(xhci_pdev, USB_INTEL_XUSB2PR, 0x0);
1016}
1017EXPORT_SYMBOL_GPL(usb_disable_xhci_ports);
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027static void quirk_usb_handoff_xhci(struct pci_dev *pdev)
1028{
1029 void __iomem *base;
1030 int ext_cap_offset;
1031 void __iomem *op_reg_base;
1032 u32 val;
1033 int timeout;
1034 int len = pci_resource_len(pdev, 0);
1035
1036 if (!mmio_resource_enabled(pdev, 0))
1037 return;
1038
1039 base = ioremap_nocache(pci_resource_start(pdev, 0), len);
1040 if (base == NULL)
1041 return;
1042
1043
1044
1045
1046
1047 ext_cap_offset = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_LEGACY);
1048
1049 if (!ext_cap_offset)
1050 goto hc_init;
1051
1052 if ((ext_cap_offset + sizeof(val)) > len) {
1053
1054 dev_warn(&pdev->dev, "xHCI controller failing to respond");
1055 goto iounmap;
1056 }
1057 val = readl(base + ext_cap_offset);
1058
1059
1060 if ((pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241) ||
1061 (pdev->vendor == PCI_VENDOR_ID_RENESAS
1062 && pdev->device == 0x0014)) {
1063 val = (val | XHCI_HC_OS_OWNED) & ~XHCI_HC_BIOS_OWNED;
1064 writel(val, base + ext_cap_offset);
1065 }
1066
1067
1068 if (val & XHCI_HC_BIOS_OWNED) {
1069 writel(val | XHCI_HC_OS_OWNED, base + ext_cap_offset);
1070
1071
1072 timeout = handshake(base + ext_cap_offset, XHCI_HC_BIOS_OWNED,
1073 0, 5000, 10);
1074
1075
1076 if (timeout) {
1077 dev_warn(&pdev->dev,
1078 "xHCI BIOS handoff failed (BIOS bug ?) %08x\n",
1079 val);
1080 writel(val & ~XHCI_HC_BIOS_OWNED, base + ext_cap_offset);
1081 }
1082 }
1083
1084 val = readl(base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
1085
1086 val &= XHCI_LEGACY_DISABLE_SMI;
1087
1088 val |= XHCI_LEGACY_SMI_EVENTS;
1089
1090 writel(val, base + ext_cap_offset + XHCI_LEGACY_CONTROL_OFFSET);
1091
1092hc_init:
1093 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
1094 usb_enable_intel_xhci_ports(pdev);
1095
1096 op_reg_base = base + XHCI_HC_LENGTH(readl(base));
1097
1098
1099
1100
1101 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_CNR, 0,
1102 5000, 10);
1103
1104 if (timeout) {
1105 val = readl(op_reg_base + XHCI_STS_OFFSET);
1106 dev_warn(&pdev->dev,
1107 "xHCI HW not ready after 5 sec (HC bug?) status = 0x%x\n",
1108 val);
1109 }
1110
1111
1112 val = readl(op_reg_base + XHCI_CMD_OFFSET);
1113 val &= ~(XHCI_CMD_RUN | XHCI_IRQS);
1114 writel(val, op_reg_base + XHCI_CMD_OFFSET);
1115
1116
1117 timeout = handshake(op_reg_base + XHCI_STS_OFFSET, XHCI_STS_HALT, 1,
1118 XHCI_MAX_HALT_USEC, 125);
1119 if (timeout) {
1120 val = readl(op_reg_base + XHCI_STS_OFFSET);
1121 dev_warn(&pdev->dev,
1122 "xHCI HW did not halt within %d usec status = 0x%x\n",
1123 XHCI_MAX_HALT_USEC, val);
1124 }
1125
1126iounmap:
1127 iounmap(base);
1128}
1129
1130static void quirk_usb_early_handoff(struct pci_dev *pdev)
1131{
1132
1133
1134
1135 if (pdev->vendor == 0x184e)
1136 return;
1137 if (pdev->class != PCI_CLASS_SERIAL_USB_UHCI &&
1138 pdev->class != PCI_CLASS_SERIAL_USB_OHCI &&
1139 pdev->class != PCI_CLASS_SERIAL_USB_EHCI &&
1140 pdev->class != PCI_CLASS_SERIAL_USB_XHCI)
1141 return;
1142
1143 if (pci_enable_device(pdev) < 0) {
1144 dev_warn(&pdev->dev,
1145 "Can't enable PCI device, BIOS handoff failed.\n");
1146 return;
1147 }
1148 if (pdev->class == PCI_CLASS_SERIAL_USB_UHCI)
1149 quirk_usb_handoff_uhci(pdev);
1150 else if (pdev->class == PCI_CLASS_SERIAL_USB_OHCI)
1151 quirk_usb_handoff_ohci(pdev);
1152 else if (pdev->class == PCI_CLASS_SERIAL_USB_EHCI)
1153 quirk_usb_disable_ehci(pdev);
1154 else if (pdev->class == PCI_CLASS_SERIAL_USB_XHCI)
1155 quirk_usb_handoff_xhci(pdev);
1156 pci_disable_device(pdev);
1157}
1158DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
1159 PCI_CLASS_SERIAL_USB, 8, quirk_usb_early_handoff);
1160
1161bool usb_xhci_needs_pci_reset(struct pci_dev *pdev)
1162{
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
1174 (pdev->device == 0x0014 || pdev->device == 0x0015))
1175 return true;
1176
1177 return false;
1178}
1179EXPORT_SYMBOL_GPL(usb_xhci_needs_pci_reset);
1180