LXR linux/drivers/usb/musb/cppi

   1/* Copyright (C) 2005-2006 by Texas Instruments */
   2
   3#ifndef _CPPI_DMA_H_
   4#define _CPPI_DMA_H_
   5
   6#include <linux/slab.h>
   7#include <linux/list.h>
   8#include <linux/errno.h>
   9#include <linux/dmapool.h>
  10#include <linux/dmaengine.h>
  11
  12#include "musb_core.h"
  13#include "musb_dma.h"
  14
  15/* CPPI RX/TX state RAM */
  16
  17struct cppi_tx_stateram {
  18        u32 tx_head;                    /* "DMA packet" head descriptor */
  19        u32 tx_buf;
  20        u32 tx_current;                 /* current descriptor */
  21        u32 tx_buf_current;
  22        u32 tx_info;                    /* flags, remaining buflen */
  23        u32 tx_rem_len;
  24        u32 tx_dummy;                   /* unused */
  25        u32 tx_complete;
  26};
  27
  28struct cppi_rx_stateram {
  29        u32 rx_skipbytes;
  30        u32 rx_head;
  31        u32 rx_sop;                     /* "DMA packet" head descriptor */
  32        u32 rx_current;                 /* current descriptor */
  33        u32 rx_buf_current;
  34        u32 rx_len_len;
  35        u32 rx_cnt_cnt;
  36        u32 rx_complete;
  37};
  38
  39/* hw_options bits in CPPI buffer descriptors */
  40#define CPPI_SOP_SET    ((u32)(1 << 31))
  41#define CPPI_EOP_SET    ((u32)(1 << 30))
  42#define CPPI_OWN_SET    ((u32)(1 << 29))        /* owned by cppi */
  43#define CPPI_EOQ_MASK   ((u32)(1 << 28))
  44#define CPPI_ZERO_SET   ((u32)(1 << 23))        /* rx saw zlp; tx issues one */
  45#define CPPI_RXABT_MASK ((u32)(1 << 19))        /* need more rx buffers */
  46
  47#define CPPI_RECV_PKTLEN_MASK 0xFFFF
  48#define CPPI_BUFFER_LEN_MASK 0xFFFF
  49
  50#define CPPI_TEAR_READY ((u32)(1 << 31))
  51
  52/* CPPI data structure definitions */
  53
  54#define CPPI_DESCRIPTOR_ALIGN   16      /* bytes; 5-dec docs say 4-byte align */
  55
  56struct cppi_descriptor {
  57        /* hardware overlay */
  58        u32             hw_next;        /* next buffer descriptor Pointer */
  59        u32             hw_bufp;        /* i/o buffer pointer */
  60        u32             hw_off_len;     /* buffer_offset16, buffer_length16 */
  61        u32             hw_options;     /* flags:  SOP, EOP etc*/
  62
  63        struct cppi_descriptor *next;
  64        dma_addr_t      dma;            /* address of this descriptor */
  65        u32             buflen;         /* for RX: original buffer length */
  66} __attribute__ ((aligned(CPPI_DESCRIPTOR_ALIGN)));
  67
  68
  69struct cppi;
  70
  71/* CPPI  Channel Control structure */
  72struct cppi_channel {
  73        struct dma_channel      channel;
  74
  75        /* back pointer to the DMA controller structure */
  76        struct cppi             *controller;
  77
  78        /* which direction of which endpoint? */
  79        struct musb_hw_ep       *hw_ep;
  80        bool                    transmit;
  81        u8                      index;
  82
  83        /* DMA modes:  RNDIS or "transparent" */
  84        u8                      is_rndis;
  85
  86        /* book keeping for current transfer request */
  87        dma_addr_t              buf_dma;
  88        u32                     buf_len;
  89        u32                     maxpacket;
  90        u32                     offset;         /* dma requested */
  91
  92        void __iomem            *state_ram;     /* CPPI state */
  93
  94        struct cppi_descriptor  *freelist;
  95
  96        /* BD management fields */
  97        struct cppi_descriptor  *head;
  98        struct cppi_descriptor  *tail;
  99        struct cppi_descriptor  *last_processed;
 100
 101        /* use tx_complete in host role to track endpoints waiting for
 102         * FIFONOTEMPTY to clear.
 103         */
 104        struct list_head        tx_complete;
 105};
 106
 107/* CPPI DMA controller object */
 108struct cppi {
 109        struct dma_controller           controller;
 110        void __iomem                    *mregs;         /* Mentor regs */
 111        void __iomem                    *tibase;        /* TI/CPPI regs */
 112
 113        int                             irq;
 114
 115        struct cppi_channel             tx[4];
 116        struct cppi_channel             rx[4];
 117
 118        struct dma_pool                 *pool;
 119
 120        struct list_head                tx_complete;
 121};
 122
 123/* CPPI IRQ handler */
 124extern irqreturn_t cppi_interrupt(int, void *);
 125
 126struct cppi41_dma_channel {
 127        struct dma_channel channel;
 128        struct cppi41_dma_controller *controller;
 129        struct musb_hw_ep *hw_ep;
 130        struct dma_chan *dc;
 131        dma_cookie_t cookie;
 132        u8 port_num;
 133        u8 is_tx;
 134        u8 is_allocated;
 135        u8 usb_toggle;
 136
 137        dma_addr_t buf_addr;
 138        u32 total_len;
 139        u32 prog_len;
 140        u32 transferred;
 141        u32 packet_sz;
 142        struct list_head tx_check;
 143        int tx_zlp;
 144};
 145
 146#endif                          /* end of ifndef _CPPI_DMA_H_ */
 147