LXR linux/drivers/usb/musb/musbhsdma.c

   1/*
   2 * MUSB OTG driver - support for Mentor's DMA controller
   3 *
   4 * Copyright 2005 Mentor Graphics Corporation
   5 * Copyright (C) 2005-2007 by Texas Instruments
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public License
   9 * version 2 as published by the Free Software Foundation.
  10 *
  11 * This program is distributed in the hope that it will be useful, but
  12 * WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU General Public License
  17 * along with this program; if not, write to the Free Software
  18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  19 * 02110-1301 USA
  20 *
  21 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
  22 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  23 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  24 * NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  27 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  28 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  31 *
  32 */
  33#include <linux/device.h>
  34#include <linux/interrupt.h>
  35#include <linux/platform_device.h>
  36#include <linux/slab.h>
  37#include "musb_core.h"
  38#include "musbhsdma.h"
  39
  40static void dma_channel_release(struct dma_channel *channel);
  41
  42static void dma_controller_stop(struct musb_dma_controller *controller)
  43{
  44        struct musb *musb = controller->private_data;
  45        struct dma_channel *channel;
  46        u8 bit;
  47
  48        if (controller->used_channels != 0) {
  49                dev_err(musb->controller,
  50                        "Stopping DMA controller while channel active\n");
  51
  52                for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
  53                        if (controller->used_channels & (1 << bit)) {
  54                                channel = &controller->channel[bit].channel;
  55                                dma_channel_release(channel);
  56
  57                                if (!controller->used_channels)
  58                                        break;
  59                        }
  60                }
  61        }
  62}
  63
  64static struct dma_channel *dma_channel_allocate(struct dma_controller *c,
  65                                struct musb_hw_ep *hw_ep, u8 transmit)
  66{
  67        struct musb_dma_controller *controller = container_of(c,
  68                        struct musb_dma_controller, controller);
  69        struct musb_dma_channel *musb_channel = NULL;
  70        struct dma_channel *channel = NULL;
  71        u8 bit;
  72
  73        for (bit = 0; bit < MUSB_HSDMA_CHANNELS; bit++) {
  74                if (!(controller->used_channels & (1 << bit))) {
  75                        controller->used_channels |= (1 << bit);
  76                        musb_channel = &(controller->channel[bit]);
  77                        musb_channel->controller = controller;
  78                        musb_channel->idx = bit;
  79                        musb_channel->epnum = hw_ep->epnum;
  80                        musb_channel->transmit = transmit;
  81                        channel = &(musb_channel->channel);
  82                        channel->private_data = musb_channel;
  83                        channel->status = MUSB_DMA_STATUS_FREE;
  84                        channel->max_len = 0x100000;
  85                        /* Tx => mode 1; Rx => mode 0 */
  86                        channel->desired_mode = transmit;
  87                        channel->actual_len = 0;
  88                        break;
  89                }
  90        }
  91
  92        return channel;
  93}
  94
  95static void dma_channel_release(struct dma_channel *channel)
  96{
  97        struct musb_dma_channel *musb_channel = channel->private_data;
  98
  99        channel->actual_len = 0;
 100        musb_channel->start_addr = 0;
 101        musb_channel->len = 0;
 102
 103        musb_channel->controller->used_channels &=
 104                ~(1 << musb_channel->idx);
 105
 106        channel->status = MUSB_DMA_STATUS_UNKNOWN;
 107}
 108
 109static void configure_channel(struct dma_channel *channel,
 110                                u16 packet_sz, u8 mode,
 111                                dma_addr_t dma_addr, u32 len)
 112{
 113        struct musb_dma_channel *musb_channel = channel->private_data;
 114        struct musb_dma_controller *controller = musb_channel->controller;
 115        struct musb *musb = controller->private_data;
 116        void __iomem *mbase = controller->base;
 117        u8 bchannel = musb_channel->idx;
 118        u16 csr = 0;
 119
 120        musb_dbg(musb, "%p, pkt_sz %d, addr %pad, len %d, mode %d",
 121                        channel, packet_sz, &dma_addr, len, mode);
 122
 123        if (mode) {
 124                csr |= 1 << MUSB_HSDMA_MODE1_SHIFT;
 125                BUG_ON(len < packet_sz);
 126        }
 127        csr |= MUSB_HSDMA_BURSTMODE_INCR16
 128                                << MUSB_HSDMA_BURSTMODE_SHIFT;
 129
 130        csr |= (musb_channel->epnum << MUSB_HSDMA_ENDPOINT_SHIFT)
 131                | (1 << MUSB_HSDMA_ENABLE_SHIFT)
 132                | (1 << MUSB_HSDMA_IRQENABLE_SHIFT)
 133                | (musb_channel->transmit
 134                                ? (1 << MUSB_HSDMA_TRANSMIT_SHIFT)
 135                                : 0);
 136
 137        /* address/count */
 138        musb_write_hsdma_addr(mbase, bchannel, dma_addr);
 139        musb_write_hsdma_count(mbase, bchannel, len);
 140
 141        /* control (this should start things) */
 142        musb_writew(mbase,
 143                MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
 144                csr);
 145}
 146
 147static int dma_channel_program(struct dma_channel *channel,
 148                                u16 packet_sz, u8 mode,
 149                                dma_addr_t dma_addr, u32 len)
 150{
 151        struct musb_dma_channel *musb_channel = channel->private_data;
 152        struct musb_dma_controller *controller = musb_channel->controller;
 153        struct musb *musb = controller->private_data;
 154
 155        musb_dbg(musb, "ep%d-%s pkt_sz %d, dma_addr %pad length %d, mode %d",
 156                musb_channel->epnum,
 157                musb_channel->transmit ? "Tx" : "Rx",
 158                packet_sz, &dma_addr, len, mode);
 159
 160        BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
 161                channel->status == MUSB_DMA_STATUS_BUSY);
 162
 163        /* Let targets check/tweak the arguments */
 164        if (musb->ops->adjust_channel_params) {
 165                int ret = musb->ops->adjust_channel_params(channel,
 166                        packet_sz, &mode, &dma_addr, &len);
 167                if (ret)
 168                        return ret;
 169        }
 170
 171        /*
 172         * The DMA engine in RTL1.8 and above cannot handle
 173         * DMA addresses that are not aligned to a 4 byte boundary.
 174         * It ends up masking the last two bits of the address
 175         * programmed in DMA_ADDR.
 176         *
 177         * Fail such DMA transfers, so that the backup PIO mode
 178         * can carry out the transfer
 179         */
 180        if ((musb->hwvers >= MUSB_HWVERS_1800) && (dma_addr % 4))
 181                return false;
 182
 183        channel->actual_len = 0;
 184        musb_channel->start_addr = dma_addr;
 185        musb_channel->len = len;
 186        musb_channel->max_packet_sz = packet_sz;
 187        channel->status = MUSB_DMA_STATUS_BUSY;
 188
 189        configure_channel(channel, packet_sz, mode, dma_addr, len);
 190
 191        return true;
 192}
 193
 194static int dma_channel_abort(struct dma_channel *channel)
 195{
 196        struct musb_dma_channel *musb_channel = channel->private_data;
 197        void __iomem *mbase = musb_channel->controller->base;
 198        struct musb *musb = musb_channel->controller->private_data;
 199
 200        u8 bchannel = musb_channel->idx;
 201        int offset;
 202        u16 csr;
 203
 204        if (channel->status == MUSB_DMA_STATUS_BUSY) {
 205                if (musb_channel->transmit) {
 206                        offset = musb->io.ep_offset(musb_channel->epnum,
 207                                                MUSB_TXCSR);
 208
 209                        /*
 210                         * The programming guide says that we must clear
 211                         * the DMAENAB bit before the DMAMODE bit...
 212                         */
 213                        csr = musb_readw(mbase, offset);
 214                        csr &= ~(MUSB_TXCSR_AUTOSET | MUSB_TXCSR_DMAENAB);
 215                        musb_writew(mbase, offset, csr);
 216                        csr &= ~MUSB_TXCSR_DMAMODE;
 217                        musb_writew(mbase, offset, csr);
 218                } else {
 219                        offset = musb->io.ep_offset(musb_channel->epnum,
 220                                                MUSB_RXCSR);
 221
 222                        csr = musb_readw(mbase, offset);
 223                        csr &= ~(MUSB_RXCSR_AUTOCLEAR |
 224                                 MUSB_RXCSR_DMAENAB |
 225                                 MUSB_RXCSR_DMAMODE);
 226                        musb_writew(mbase, offset, csr);
 227                }
 228
 229                musb_writew(mbase,
 230                        MUSB_HSDMA_CHANNEL_OFFSET(bchannel, MUSB_HSDMA_CONTROL),
 231                        0);
 232                musb_write_hsdma_addr(mbase, bchannel, 0);
 233                musb_write_hsdma_count(mbase, bchannel, 0);
 234                channel->status = MUSB_DMA_STATUS_FREE;
 235        }
 236
 237        return 0;
 238}
 239
 240static irqreturn_t dma_controller_irq(int irq, void *private_data)
 241{
 242        struct musb_dma_controller *controller = private_data;
 243        struct musb *musb = controller->private_data;
 244        struct musb_dma_channel *musb_channel;
 245        struct dma_channel *channel;
 246
 247        void __iomem *mbase = controller->base;
 248
 249        irqreturn_t retval = IRQ_NONE;
 250
 251        unsigned long flags;
 252
 253        u8 bchannel;
 254        u8 int_hsdma;
 255
 256        u32 addr, count;
 257        u16 csr;
 258
 259        spin_lock_irqsave(&musb->lock, flags);
 260
 261        int_hsdma = musb_readb(mbase, MUSB_HSDMA_INTR);
 262
 263#ifdef CONFIG_BLACKFIN
 264        /* Clear DMA interrupt flags */
 265        musb_writeb(mbase, MUSB_HSDMA_INTR, int_hsdma);
 266#endif
 267
 268        if (!int_hsdma) {
 269                musb_dbg(musb, "spurious DMA irq");
 270
 271                for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
 272                        musb_channel = (struct musb_dma_channel *)
 273                                        &(controller->channel[bchannel]);
 274                        channel = &musb_channel->channel;
 275                        if (channel->status == MUSB_DMA_STATUS_BUSY) {
 276                                count = musb_read_hsdma_count(mbase, bchannel);
 277
 278                                if (count == 0)
 279                                        int_hsdma |= (1 << bchannel);
 280                        }
 281                }
 282
 283                musb_dbg(musb, "int_hsdma = 0x%x", int_hsdma);
 284
 285                if (!int_hsdma)
 286                        goto done;
 287        }
 288
 289        for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
 290                if (int_hsdma & (1 << bchannel)) {
 291                        musb_channel = (struct musb_dma_channel *)
 292                                        &(controller->channel[bchannel]);
 293                        channel = &musb_channel->channel;
 294
 295                        csr = musb_readw(mbase,
 296                                        MUSB_HSDMA_CHANNEL_OFFSET(bchannel,
 297                                                        MUSB_HSDMA_CONTROL));
 298
 299                        if (csr & (1 << MUSB_HSDMA_BUSERROR_SHIFT)) {
 300                                musb_channel->channel.status =
 301                                        MUSB_DMA_STATUS_BUS_ABORT;
 302                        } else {
 303                                u8 devctl;
 304
 305                                addr = musb_read_hsdma_addr(mbase,
 306                                                bchannel);
 307                                channel->actual_len = addr
 308                                        - musb_channel->start_addr;
 309
 310                                musb_dbg(musb, "ch %p, 0x%x -> 0x%x (%zu / %d) %s",
 311                                        channel, musb_channel->start_addr,
 312                                        addr, channel->actual_len,
 313                                        musb_channel->len,
 314                                        (channel->actual_len
 315                                                < musb_channel->len) ?
 316                                        "=> reconfig 0" : "=> complete");
 317
 318                                devctl = musb_readb(mbase, MUSB_DEVCTL);
 319
 320                                channel->status = MUSB_DMA_STATUS_FREE;
 321
 322                                /* completed */
 323                                if ((devctl & MUSB_DEVCTL_HM)
 324                                        && (musb_channel->transmit)
 325                                        && ((channel->desired_mode == 0)
 326                                            || (channel->actual_len &
 327                                            (musb_channel->max_packet_sz - 1)))
 328                                    ) {
 329                                        u8  epnum  = musb_channel->epnum;
 330                                        int offset = musb->io.ep_offset(epnum,
 331                                                                    MUSB_TXCSR);
 332                                        u16 txcsr;
 333
 334                                        /*
 335                                         * The programming guide says that we
 336                                         * must clear DMAENAB before DMAMODE.
 337                                         */
 338                                        musb_ep_select(mbase, epnum);
 339                                        txcsr = musb_readw(mbase, offset);
 340                                        txcsr &= ~(MUSB_TXCSR_DMAENAB
 341                                                        | MUSB_TXCSR_AUTOSET);
 342                                        musb_writew(mbase, offset, txcsr);
 343                                        /* Send out the packet */
 344                                        txcsr &= ~MUSB_TXCSR_DMAMODE;
 345                                        txcsr |=  MUSB_TXCSR_TXPKTRDY;
 346                                        musb_writew(mbase, offset, txcsr);
 347                                }
 348                                musb_dma_completion(musb, musb_channel->epnum,
 349                                                    musb_channel->transmit);
 350                        }
 351                }
 352        }
 353
 354        retval = IRQ_HANDLED;
 355done:
 356        spin_unlock_irqrestore(&musb->lock, flags);
 357        return retval;
 358}
 359
 360void musbhs_dma_controller_destroy(struct dma_controller *c)
 361{
 362        struct musb_dma_controller *controller = container_of(c,
 363                        struct musb_dma_controller, controller);
 364
 365        dma_controller_stop(controller);
 366
 367        if (controller->irq)
 368                free_irq(controller->irq, c);
 369
 370        kfree(controller);
 371}
 372EXPORT_SYMBOL_GPL(musbhs_dma_controller_destroy);
 373
 374struct dma_controller *musbhs_dma_controller_create(struct musb *musb,
 375                                                    void __iomem *base)
 376{
 377        struct musb_dma_controller *controller;
 378        struct device *dev = musb->controller;
 379        struct platform_device *pdev = to_platform_device(dev);
 380        int irq = platform_get_irq_byname(pdev, "dma");
 381
 382        if (irq <= 0) {
 383                dev_err(dev, "No DMA interrupt line!\n");
 384                return NULL;
 385        }
 386
 387        controller = kzalloc(sizeof(*controller), GFP_KERNEL);
 388        if (!controller)
 389                return NULL;
 390
 391        controller->channel_count = MUSB_HSDMA_CHANNELS;
 392        controller->private_data = musb;
 393        controller->base = base;
 394
 395        controller->controller.channel_alloc = dma_channel_allocate;
 396        controller->controller.channel_release = dma_channel_release;
 397        controller->controller.channel_program = dma_channel_program;
 398        controller->controller.channel_abort = dma_channel_abort;
 399
 400        if (request_irq(irq, dma_controller_irq, 0,
 401                        dev_name(musb->controller), &controller->controller)) {
 402                dev_err(dev, "request_irq %d failed!\n", irq);
 403                musb_dma_controller_destroy(&controller->controller);
 404
 405                return NULL;
 406        }
 407
 408        controller->irq = irq;
 409
 410        return &controller->controller;
 411}
 412EXPORT_SYMBOL_GPL(musbhs_dma_controller_create);
 413