1/* 2 * Copyright (c) 2014 MundoReader S.L. 3 * Author: Heiko Stuebner <heiko@sntech.de> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H 17#define _DT_BINDINGS_CLK_ROCKCHIP_RK3188_COMMON_H 18 19/* core clocks from */ 20#define PLL_APLL 1 21#define PLL_DPLL 2 22#define PLL_CPLL 3 23#define PLL_GPLL 4 24#define CORE_PERI 5 25#define CORE_L2C 6 26#define ARMCLK 7 27 28/* sclk gates (special clocks) */ 29#define SCLK_UART0 64 30#define SCLK_UART1 65 31#define SCLK_UART2 66 32#define SCLK_UART3 67 33#define SCLK_MAC 68 34#define SCLK_SPI0 69 35#define SCLK_SPI1 70 36#define SCLK_SARADC 71 37#define SCLK_SDMMC 72 38#define SCLK_SDIO 73 39#define SCLK_EMMC 74 40#define SCLK_I2S0 75 41#define SCLK_I2S1 76 42#define SCLK_I2S2 77 43#define SCLK_SPDIF 78 44#define SCLK_CIF0 79 45#define SCLK_CIF1 80 46#define SCLK_OTGPHY0 81 47#define SCLK_OTGPHY1 82 48#define SCLK_HSADC 83 49#define SCLK_TIMER0 84 50#define SCLK_TIMER1 85 51#define SCLK_TIMER2 86 52#define SCLK_TIMER3 87 53#define SCLK_TIMER4 88 54#define SCLK_TIMER5 89 55#define SCLK_TIMER6 90 56#define SCLK_JTAG 91 57#define SCLK_SMC 92 58#define SCLK_TSADC 93 59 60#define DCLK_LCDC0 190 61#define DCLK_LCDC1 191 62 63/* aclk gates */ 64#define ACLK_DMA1 192 65#define ACLK_DMA2 193 66#define ACLK_GPS 194 67#define ACLK_LCDC0 195 68#define ACLK_LCDC1 196 69#define ACLK_GPU 197 70#define ACLK_SMC 198 71#define ACLK_CIF 199 72#define ACLK_IPP 200 73#define ACLK_RGA 201 74#define ACLK_CIF0 202 75#define ACLK_CPU 203 76#define ACLK_PERI 204 77 78/* pclk gates */ 79#define PCLK_GRF 320 80#define PCLK_PMU 321 81#define PCLK_TIMER0 322 82#define PCLK_TIMER1 323 83#define PCLK_TIMER2 324 84#define PCLK_TIMER3 325 85#define PCLK_PWM01 326 86#define PCLK_PWM23 327 87#define PCLK_SPI0 328 88#define PCLK_SPI1 329 89#define PCLK_SARADC 330 90#define PCLK_WDT 331 91#define PCLK_UART0 332 92#define PCLK_UART1 333 93#define PCLK_UART2 334 94#define PCLK_UART3 335 95#define PCLK_I2C0 336 96#define PCLK_I2C1 337 97#define PCLK_I2C2 338 98#define PCLK_I2C3 339 99#define PCLK_I2C4 340 100#define PCLK_GPIO0 341 101#define PCLK_GPIO1 342 102#define PCLK_GPIO2 343 103#define PCLK_GPIO3 344 104#define PCLK_GPIO4 345 105#define PCLK_GPIO6 346 106#define PCLK_EFUSE 347 107#define PCLK_TZPC 348 108#define PCLK_TSADC 349 109#define PCLK_CPU 350 110#define PCLK_PERI 351 111#define PCLK_DDRUPCTL 352 112#define PCLK_PUBL 353 113 114/* hclk gates */ 115#define HCLK_SDMMC 448 116#define HCLK_SDIO 449 117#define HCLK_EMMC 450 118#define HCLK_OTG0 451 119#define HCLK_EMAC 452 120#define HCLK_SPDIF 453 121#define HCLK_I2S0 454 122#define HCLK_I2S1 455 123#define HCLK_I2S2 456 124#define HCLK_OTG1 457 125#define HCLK_HSIC 458 126#define HCLK_HSADC 459 127#define HCLK_PIDF 460 128#define HCLK_LCDC0 461 129#define HCLK_LCDC1 462 130#define HCLK_ROM 463 131#define HCLK_CIF0 464 132#define HCLK_IPP 465 133#define HCLK_RGA 466 134#define HCLK_NANDC0 467 135#define HCLK_CPU 468 136#define HCLK_PERI 469 137 138#define CLK_NR_CLKS (HCLK_PERI + 1) 139 140/* soft-reset indices */ 141#define SRST_MCORE 2 142#define SRST_CORE0 3 143#define SRST_CORE1 4 144#define SRST_MCORE_DBG 7 145#define SRST_CORE0_DBG 8 146#define SRST_CORE1_DBG 9 147#define SRST_CORE0_WDT 12 148#define SRST_CORE1_WDT 13 149#define SRST_STRC_SYS 14 150#define SRST_L2C 15 151 152#define SRST_CPU_AHB 17 153#define SRST_AHB2APB 19 154#define SRST_DMA1 20 155#define SRST_INTMEM 21 156#define SRST_ROM 22 157#define SRST_SPDIF 26 158#define SRST_TIMER0 27 159#define SRST_TIMER1 28 160#define SRST_EFUSE 30 161 162#define SRST_GPIO0 32 163#define SRST_GPIO1 33 164#define SRST_GPIO2 34 165#define SRST_GPIO3 35 166 167#define SRST_UART0 39 168#define SRST_UART1 40 169#define SRST_UART2 41 170#define SRST_UART3 42 171#define SRST_I2C0 43 172#define SRST_I2C1 44 173#define SRST_I2C2 45 174#define SRST_I2C3 46 175#define SRST_I2C4 47 176 177#define SRST_PWM0 48 178#define SRST_PWM1 49 179#define SRST_DAP_PO 50 180#define SRST_DAP 51 181#define SRST_DAP_SYS 52 182#define SRST_TPIU_ATB 53 183#define SRST_PMU_APB 54 184#define SRST_GRF 55 185#define SRST_PMU 56 186#define SRST_PERI_AXI 57 187#define SRST_PERI_AHB 58 188#define SRST_PERI_APB 59 189#define SRST_PERI_NIU 60 190#define SRST_CPU_PERI 61 191#define SRST_EMEM_PERI 62 192#define SRST_USB_PERI 63 193 194#define SRST_DMA2 64 195#define SRST_SMC 65 196#define SRST_MAC 66 197#define SRST_NANC0 68 198#define SRST_USBOTG0 69 199#define SRST_USBPHY0 70 200#define SRST_OTGC0 71 201#define SRST_USBOTG1 72 202#define SRST_USBPHY1 73 203#define SRST_OTGC1 74 204#define SRST_HSADC 76 205#define SRST_PIDFILTER 77 206#define SRST_DDR_MSCH 79 207 208#define SRST_TZPC 80 209#define SRST_SDMMC 81 210#define SRST_SDIO 82 211#define SRST_EMMC 83 212#define SRST_SPI0 84 213#define SRST_SPI1 85 214#define SRST_WDT 86 215#define SRST_SARADC 87 216#define SRST_DDRPHY 88 217#define SRST_DDRPHY_APB 89 218#define SRST_DDRCTL 90 219#define SRST_DDRCTL_APB 91 220#define SRST_DDRPUB 93 221 222#define SRST_VIO0_AXI 98 223#define SRST_VIO0_AHB 99 224#define SRST_LCDC0_AXI 100 225#define SRST_LCDC0_AHB 101 226#define SRST_LCDC0_DCLK 102 227#define SRST_LCDC1_AXI 103 228#define SRST_LCDC1_AHB 104 229#define SRST_LCDC1_DCLK 105 230#define SRST_IPP_AXI 106 231#define SRST_IPP_AHB 107 232#define SRST_RGA_AXI 108 233#define SRST_RGA_AHB 109 234#define SRST_CIF0 110 235 236#define SRST_VCODEC_AXI 112 237#define SRST_VCODEC_AHB 113 238#define SRST_VIO1_AXI 114 239#define SRST_VCODEC_CPU 115 240#define SRST_VCODEC_NIU 116 241#define SRST_GPU 120 242#define SRST_GPU_NIU 122 243#define SRST_TFUN_ATB 125 244#define SRST_TFUN_APB 126 245#define SRST_CTI4_APB 127 246 247#define SRST_TPIU_APB 128 248#define SRST_TRACE 129 249#define SRST_CORE_DBG 130 250#define SRST_DBG_APB 131 251#define SRST_CTI0 132 252#define SRST_CTI0_APB 133 253#define SRST_CTI1 134 254#define SRST_CTI1_APB 135 255#define SRST_PTM_CORE0 136 256#define SRST_PTM_CORE1 137 257#define SRST_PTM0 138 258#define SRST_PTM0_ATB 139 259#define SRST_PTM1 140 260#define SRST_PTM1_ATB 141 261#define SRST_CTM 142 262#define SRST_TS 143 263 264#endif 265