1/* 2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License 14 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17#ifndef __LINUX_CLK_TEGRA_H_ 18#define __LINUX_CLK_TEGRA_H_ 19 20#include <linux/types.h> 21#include <linux/bug.h> 22 23/* 24 * Tegra CPU clock and reset control ops 25 * 26 * wait_for_reset: 27 * keep waiting until the CPU in reset state 28 * put_in_reset: 29 * put the CPU in reset state 30 * out_of_reset: 31 * release the CPU from reset state 32 * enable_clock: 33 * CPU clock un-gate 34 * disable_clock: 35 * CPU clock gate 36 * rail_off_ready: 37 * CPU is ready for rail off 38 * suspend: 39 * save the clock settings when CPU go into low-power state 40 * resume: 41 * restore the clock settings when CPU exit low-power state 42 */ 43struct tegra_cpu_car_ops { 44 void (*wait_for_reset)(u32 cpu); 45 void (*put_in_reset)(u32 cpu); 46 void (*out_of_reset)(u32 cpu); 47 void (*enable_clock)(u32 cpu); 48 void (*disable_clock)(u32 cpu); 49#ifdef CONFIG_PM_SLEEP 50 bool (*rail_off_ready)(void); 51 void (*suspend)(void); 52 void (*resume)(void); 53#endif 54}; 55 56extern struct tegra_cpu_car_ops *tegra_cpu_car_ops; 57 58static inline void tegra_wait_cpu_in_reset(u32 cpu) 59{ 60 if (WARN_ON(!tegra_cpu_car_ops->wait_for_reset)) 61 return; 62 63 tegra_cpu_car_ops->wait_for_reset(cpu); 64} 65 66static inline void tegra_put_cpu_in_reset(u32 cpu) 67{ 68 if (WARN_ON(!tegra_cpu_car_ops->put_in_reset)) 69 return; 70 71 tegra_cpu_car_ops->put_in_reset(cpu); 72} 73 74static inline void tegra_cpu_out_of_reset(u32 cpu) 75{ 76 if (WARN_ON(!tegra_cpu_car_ops->out_of_reset)) 77 return; 78 79 tegra_cpu_car_ops->out_of_reset(cpu); 80} 81 82static inline void tegra_enable_cpu_clock(u32 cpu) 83{ 84 if (WARN_ON(!tegra_cpu_car_ops->enable_clock)) 85 return; 86 87 tegra_cpu_car_ops->enable_clock(cpu); 88} 89 90static inline void tegra_disable_cpu_clock(u32 cpu) 91{ 92 if (WARN_ON(!tegra_cpu_car_ops->disable_clock)) 93 return; 94 95 tegra_cpu_car_ops->disable_clock(cpu); 96} 97 98#ifdef CONFIG_PM_SLEEP 99static inline bool tegra_cpu_rail_off_ready(void) 100{ 101 if (WARN_ON(!tegra_cpu_car_ops->rail_off_ready)) 102 return false; 103 104 return tegra_cpu_car_ops->rail_off_ready(); 105} 106 107static inline void tegra_cpu_clock_suspend(void) 108{ 109 if (WARN_ON(!tegra_cpu_car_ops->suspend)) 110 return; 111 112 tegra_cpu_car_ops->suspend(); 113} 114 115static inline void tegra_cpu_clock_resume(void) 116{ 117 if (WARN_ON(!tegra_cpu_car_ops->resume)) 118 return; 119 120 tegra_cpu_car_ops->resume(); 121} 122#endif 123 124extern void tegra210_xusb_pll_hw_control_enable(void); 125extern void tegra210_xusb_pll_hw_sequence_start(void); 126extern void tegra210_sata_pll_hw_control_enable(void); 127extern void tegra210_sata_pll_hw_sequence_start(void); 128extern void tegra210_set_sata_pll_seq_sw(bool state); 129extern void tegra210_put_utmipll_in_iddq(void); 130extern void tegra210_put_utmipll_out_iddq(void); 131 132#endif /* __LINUX_CLK_TEGRA_H_ */ 133