1#ifndef _LINUX_IRQ_H
2#define _LINUX_IRQ_H
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12#include <linux/smp.h>
13#include <linux/linkage.h>
14#include <linux/cache.h>
15#include <linux/spinlock.h>
16#include <linux/cpumask.h>
17#include <linux/gfp.h>
18#include <linux/irqhandler.h>
19#include <linux/irqreturn.h>
20#include <linux/irqnr.h>
21#include <linux/errno.h>
22#include <linux/topology.h>
23#include <linux/wait.h>
24#include <linux/io.h>
25#include <linux/slab.h>
26
27#include <asm/irq.h>
28#include <asm/ptrace.h>
29#include <asm/irq_regs.h>
30
31struct seq_file;
32struct module;
33struct msi_msg;
34enum irqchip_irq_state;
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78enum {
79 IRQ_TYPE_NONE = 0x00000000,
80 IRQ_TYPE_EDGE_RISING = 0x00000001,
81 IRQ_TYPE_EDGE_FALLING = 0x00000002,
82 IRQ_TYPE_EDGE_BOTH = (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING),
83 IRQ_TYPE_LEVEL_HIGH = 0x00000004,
84 IRQ_TYPE_LEVEL_LOW = 0x00000008,
85 IRQ_TYPE_LEVEL_MASK = (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH),
86 IRQ_TYPE_SENSE_MASK = 0x0000000f,
87 IRQ_TYPE_DEFAULT = IRQ_TYPE_SENSE_MASK,
88
89 IRQ_TYPE_PROBE = 0x00000010,
90
91 IRQ_LEVEL = (1 << 8),
92 IRQ_PER_CPU = (1 << 9),
93 IRQ_NOPROBE = (1 << 10),
94 IRQ_NOREQUEST = (1 << 11),
95 IRQ_NOAUTOEN = (1 << 12),
96 IRQ_NO_BALANCING = (1 << 13),
97 IRQ_MOVE_PCNTXT = (1 << 14),
98 IRQ_NESTED_THREAD = (1 << 15),
99 IRQ_NOTHREAD = (1 << 16),
100 IRQ_PER_CPU_DEVID = (1 << 17),
101 IRQ_IS_POLLED = (1 << 18),
102 IRQ_DISABLE_UNLAZY = (1 << 19),
103};
104
105#define IRQF_MODIFY_MASK \
106 (IRQ_TYPE_SENSE_MASK | IRQ_NOPROBE | IRQ_NOREQUEST | \
107 IRQ_NOAUTOEN | IRQ_MOVE_PCNTXT | IRQ_LEVEL | IRQ_NO_BALANCING | \
108 IRQ_PER_CPU | IRQ_NESTED_THREAD | IRQ_NOTHREAD | IRQ_PER_CPU_DEVID | \
109 IRQ_IS_POLLED | IRQ_DISABLE_UNLAZY)
110
111#define IRQ_NO_BALANCING_MASK (IRQ_PER_CPU | IRQ_NO_BALANCING)
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121
122enum {
123 IRQ_SET_MASK_OK = 0,
124 IRQ_SET_MASK_OK_NOCOPY,
125 IRQ_SET_MASK_OK_DONE,
126};
127
128struct msi_desc;
129struct irq_domain;
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146struct irq_common_data {
147 unsigned int __private state_use_accessors;
148#ifdef CONFIG_NUMA
149 unsigned int node;
150#endif
151 void *handler_data;
152 struct msi_desc *msi_desc;
153 cpumask_var_t affinity;
154#ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
155 cpumask_var_t effective_affinity;
156#endif
157#ifdef CONFIG_GENERIC_IRQ_IPI
158 unsigned int ipi_offset;
159#endif
160};
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176struct irq_data {
177 u32 mask;
178 unsigned int irq;
179 unsigned long hwirq;
180 struct irq_common_data *common;
181 struct irq_chip *chip;
182 struct irq_domain *domain;
183#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
184 struct irq_data *parent_data;
185#endif
186 void *chip_data;
187};
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214enum {
215 IRQD_TRIGGER_MASK = 0xf,
216 IRQD_SETAFFINITY_PENDING = (1 << 8),
217 IRQD_ACTIVATED = (1 << 9),
218 IRQD_NO_BALANCING = (1 << 10),
219 IRQD_PER_CPU = (1 << 11),
220 IRQD_AFFINITY_SET = (1 << 12),
221 IRQD_LEVEL = (1 << 13),
222 IRQD_WAKEUP_STATE = (1 << 14),
223 IRQD_MOVE_PCNTXT = (1 << 15),
224 IRQD_IRQ_DISABLED = (1 << 16),
225 IRQD_IRQ_MASKED = (1 << 17),
226 IRQD_IRQ_INPROGRESS = (1 << 18),
227 IRQD_WAKEUP_ARMED = (1 << 19),
228 IRQD_FORWARDED_TO_VCPU = (1 << 20),
229 IRQD_AFFINITY_MANAGED = (1 << 21),
230 IRQD_IRQ_STARTED = (1 << 22),
231 IRQD_MANAGED_SHUTDOWN = (1 << 23),
232 IRQD_SINGLE_TARGET = (1 << 24),
233};
234
235#define __irqd_to_state(d) ACCESS_PRIVATE((d)->common, state_use_accessors)
236
237static inline bool irqd_is_setaffinity_pending(struct irq_data *d)
238{
239 return __irqd_to_state(d) & IRQD_SETAFFINITY_PENDING;
240}
241
242static inline bool irqd_is_per_cpu(struct irq_data *d)
243{
244 return __irqd_to_state(d) & IRQD_PER_CPU;
245}
246
247static inline bool irqd_can_balance(struct irq_data *d)
248{
249 return !(__irqd_to_state(d) & (IRQD_PER_CPU | IRQD_NO_BALANCING));
250}
251
252static inline bool irqd_affinity_was_set(struct irq_data *d)
253{
254 return __irqd_to_state(d) & IRQD_AFFINITY_SET;
255}
256
257static inline void irqd_mark_affinity_was_set(struct irq_data *d)
258{
259 __irqd_to_state(d) |= IRQD_AFFINITY_SET;
260}
261
262static inline u32 irqd_get_trigger_type(struct irq_data *d)
263{
264 return __irqd_to_state(d) & IRQD_TRIGGER_MASK;
265}
266
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269
270static inline void irqd_set_trigger_type(struct irq_data *d, u32 type)
271{
272 __irqd_to_state(d) &= ~IRQD_TRIGGER_MASK;
273 __irqd_to_state(d) |= type & IRQD_TRIGGER_MASK;
274}
275
276static inline bool irqd_is_level_type(struct irq_data *d)
277{
278 return __irqd_to_state(d) & IRQD_LEVEL;
279}
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284
285static inline void irqd_set_single_target(struct irq_data *d)
286{
287 __irqd_to_state(d) |= IRQD_SINGLE_TARGET;
288}
289
290static inline bool irqd_is_single_target(struct irq_data *d)
291{
292 return __irqd_to_state(d) & IRQD_SINGLE_TARGET;
293}
294
295static inline bool irqd_is_wakeup_set(struct irq_data *d)
296{
297 return __irqd_to_state(d) & IRQD_WAKEUP_STATE;
298}
299
300static inline bool irqd_can_move_in_process_context(struct irq_data *d)
301{
302 return __irqd_to_state(d) & IRQD_MOVE_PCNTXT;
303}
304
305static inline bool irqd_irq_disabled(struct irq_data *d)
306{
307 return __irqd_to_state(d) & IRQD_IRQ_DISABLED;
308}
309
310static inline bool irqd_irq_masked(struct irq_data *d)
311{
312 return __irqd_to_state(d) & IRQD_IRQ_MASKED;
313}
314
315static inline bool irqd_irq_inprogress(struct irq_data *d)
316{
317 return __irqd_to_state(d) & IRQD_IRQ_INPROGRESS;
318}
319
320static inline bool irqd_is_wakeup_armed(struct irq_data *d)
321{
322 return __irqd_to_state(d) & IRQD_WAKEUP_ARMED;
323}
324
325static inline bool irqd_is_forwarded_to_vcpu(struct irq_data *d)
326{
327 return __irqd_to_state(d) & IRQD_FORWARDED_TO_VCPU;
328}
329
330static inline void irqd_set_forwarded_to_vcpu(struct irq_data *d)
331{
332 __irqd_to_state(d) |= IRQD_FORWARDED_TO_VCPU;
333}
334
335static inline void irqd_clr_forwarded_to_vcpu(struct irq_data *d)
336{
337 __irqd_to_state(d) &= ~IRQD_FORWARDED_TO_VCPU;
338}
339
340static inline bool irqd_affinity_is_managed(struct irq_data *d)
341{
342 return __irqd_to_state(d) & IRQD_AFFINITY_MANAGED;
343}
344
345static inline bool irqd_is_activated(struct irq_data *d)
346{
347 return __irqd_to_state(d) & IRQD_ACTIVATED;
348}
349
350static inline void irqd_set_activated(struct irq_data *d)
351{
352 __irqd_to_state(d) |= IRQD_ACTIVATED;
353}
354
355static inline void irqd_clr_activated(struct irq_data *d)
356{
357 __irqd_to_state(d) &= ~IRQD_ACTIVATED;
358}
359
360static inline bool irqd_is_started(struct irq_data *d)
361{
362 return __irqd_to_state(d) & IRQD_IRQ_STARTED;
363}
364
365static inline bool irqd_is_managed_and_shutdown(struct irq_data *d)
366{
367 return __irqd_to_state(d) & IRQD_MANAGED_SHUTDOWN;
368}
369
370#undef __irqd_to_state
371
372static inline irq_hw_number_t irqd_to_hwirq(struct irq_data *d)
373{
374 return d->hwirq;
375}
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424struct irq_chip {
425 struct device *parent_device;
426 const char *name;
427 unsigned int (*irq_startup)(struct irq_data *data);
428 void (*irq_shutdown)(struct irq_data *data);
429 void (*irq_enable)(struct irq_data *data);
430 void (*irq_disable)(struct irq_data *data);
431
432 void (*irq_ack)(struct irq_data *data);
433 void (*irq_mask)(struct irq_data *data);
434 void (*irq_mask_ack)(struct irq_data *data);
435 void (*irq_unmask)(struct irq_data *data);
436 void (*irq_eoi)(struct irq_data *data);
437
438 int (*irq_set_affinity)(struct irq_data *data, const struct cpumask *dest, bool force);
439 int (*irq_retrigger)(struct irq_data *data);
440 int (*irq_set_type)(struct irq_data *data, unsigned int flow_type);
441 int (*irq_set_wake)(struct irq_data *data, unsigned int on);
442
443 void (*irq_bus_lock)(struct irq_data *data);
444 void (*irq_bus_sync_unlock)(struct irq_data *data);
445
446 void (*irq_cpu_online)(struct irq_data *data);
447 void (*irq_cpu_offline)(struct irq_data *data);
448
449 void (*irq_suspend)(struct irq_data *data);
450 void (*irq_resume)(struct irq_data *data);
451 void (*irq_pm_shutdown)(struct irq_data *data);
452
453 void (*irq_calc_mask)(struct irq_data *data);
454
455 void (*irq_print_chip)(struct irq_data *data, struct seq_file *p);
456 int (*irq_request_resources)(struct irq_data *data);
457 void (*irq_release_resources)(struct irq_data *data);
458
459 void (*irq_compose_msi_msg)(struct irq_data *data, struct msi_msg *msg);
460 void (*irq_write_msi_msg)(struct irq_data *data, struct msi_msg *msg);
461
462 int (*irq_get_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool *state);
463 int (*irq_set_irqchip_state)(struct irq_data *data, enum irqchip_irq_state which, bool state);
464
465 int (*irq_set_vcpu_affinity)(struct irq_data *data, void *vcpu_info);
466
467 void (*ipi_send_single)(struct irq_data *data, unsigned int cpu);
468 void (*ipi_send_mask)(struct irq_data *data, const struct cpumask *dest);
469
470 unsigned long flags;
471};
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485enum {
486 IRQCHIP_SET_TYPE_MASKED = (1 << 0),
487 IRQCHIP_EOI_IF_HANDLED = (1 << 1),
488 IRQCHIP_MASK_ON_SUSPEND = (1 << 2),
489 IRQCHIP_ONOFFLINE_ENABLED = (1 << 3),
490 IRQCHIP_SKIP_SET_WAKE = (1 << 4),
491 IRQCHIP_ONESHOT_SAFE = (1 << 5),
492 IRQCHIP_EOI_THREADED = (1 << 6),
493};
494
495#include <linux/irqdesc.h>
496
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499
500#include <asm/hw_irq.h>
501
502#ifndef NR_IRQS_LEGACY
503# define NR_IRQS_LEGACY 0
504#endif
505
506#ifndef ARCH_IRQ_INIT_FLAGS
507# define ARCH_IRQ_INIT_FLAGS 0
508#endif
509
510#define IRQ_DEFAULT_INIT_FLAGS ARCH_IRQ_INIT_FLAGS
511
512struct irqaction;
513extern int setup_irq(unsigned int irq, struct irqaction *new);
514extern void remove_irq(unsigned int irq, struct irqaction *act);
515extern int setup_percpu_irq(unsigned int irq, struct irqaction *new);
516extern void remove_percpu_irq(unsigned int irq, struct irqaction *act);
517
518extern void irq_cpu_online(void);
519extern void irq_cpu_offline(void);
520extern int irq_set_affinity_locked(struct irq_data *data,
521 const struct cpumask *cpumask, bool force);
522extern int irq_set_vcpu_affinity(unsigned int irq, void *vcpu_info);
523
524#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_IRQ_MIGRATION)
525extern void irq_migrate_all_off_this_cpu(void);
526extern int irq_affinity_online_cpu(unsigned int cpu);
527#else
528# define irq_affinity_online_cpu NULL
529#endif
530
531#if defined(CONFIG_SMP) && defined(CONFIG_GENERIC_PENDING_IRQ)
532void irq_move_irq(struct irq_data *data);
533void irq_move_masked_irq(struct irq_data *data);
534void irq_force_complete_move(struct irq_desc *desc);
535#else
536static inline void irq_move_irq(struct irq_data *data) { }
537static inline void irq_move_masked_irq(struct irq_data *data) { }
538static inline void irq_force_complete_move(struct irq_desc *desc) { }
539#endif
540
541extern int no_irq_affinity;
542
543#ifdef CONFIG_HARDIRQS_SW_RESEND
544int irq_set_parent(int irq, int parent_irq);
545#else
546static inline int irq_set_parent(int irq, int parent_irq)
547{
548 return 0;
549}
550#endif
551
552
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554
555
556extern void handle_level_irq(struct irq_desc *desc);
557extern void handle_fasteoi_irq(struct irq_desc *desc);
558extern void handle_edge_irq(struct irq_desc *desc);
559extern void handle_edge_eoi_irq(struct irq_desc *desc);
560extern void handle_simple_irq(struct irq_desc *desc);
561extern void handle_untracked_irq(struct irq_desc *desc);
562extern void handle_percpu_irq(struct irq_desc *desc);
563extern void handle_percpu_devid_irq(struct irq_desc *desc);
564extern void handle_bad_irq(struct irq_desc *desc);
565extern void handle_nested_irq(unsigned int irq);
566
567extern int irq_chip_compose_msi_msg(struct irq_data *data, struct msi_msg *msg);
568extern int irq_chip_pm_get(struct irq_data *data);
569extern int irq_chip_pm_put(struct irq_data *data);
570#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY
571extern void irq_chip_enable_parent(struct irq_data *data);
572extern void irq_chip_disable_parent(struct irq_data *data);
573extern void irq_chip_ack_parent(struct irq_data *data);
574extern int irq_chip_retrigger_hierarchy(struct irq_data *data);
575extern void irq_chip_mask_parent(struct irq_data *data);
576extern void irq_chip_unmask_parent(struct irq_data *data);
577extern void irq_chip_eoi_parent(struct irq_data *data);
578extern int irq_chip_set_affinity_parent(struct irq_data *data,
579 const struct cpumask *dest,
580 bool force);
581extern int irq_chip_set_wake_parent(struct irq_data *data, unsigned int on);
582extern int irq_chip_set_vcpu_affinity_parent(struct irq_data *data,
583 void *vcpu_info);
584extern int irq_chip_set_type_parent(struct irq_data *data, unsigned int type);
585#endif
586
587
588extern void note_interrupt(struct irq_desc *desc, irqreturn_t action_ret);
589
590
591
592extern int noirqdebug_setup(char *str);
593
594
595extern int can_request_irq(unsigned int irq, unsigned long irqflags);
596
597
598extern struct irq_chip no_irq_chip;
599extern struct irq_chip dummy_irq_chip;
600
601extern void
602irq_set_chip_and_handler_name(unsigned int irq, struct irq_chip *chip,
603 irq_flow_handler_t handle, const char *name);
604
605static inline void irq_set_chip_and_handler(unsigned int irq, struct irq_chip *chip,
606 irq_flow_handler_t handle)
607{
608 irq_set_chip_and_handler_name(irq, chip, handle, NULL);
609}
610
611extern int irq_set_percpu_devid(unsigned int irq);
612extern int irq_set_percpu_devid_partition(unsigned int irq,
613 const struct cpumask *affinity);
614extern int irq_get_percpu_devid_partition(unsigned int irq,
615 struct cpumask *affinity);
616
617extern void
618__irq_set_handler(unsigned int irq, irq_flow_handler_t handle, int is_chained,
619 const char *name);
620
621static inline void
622irq_set_handler(unsigned int irq, irq_flow_handler_t handle)
623{
624 __irq_set_handler(irq, handle, 0, NULL);
625}
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631
632static inline void
633irq_set_chained_handler(unsigned int irq, irq_flow_handler_t handle)
634{
635 __irq_set_handler(irq, handle, 1, NULL);
636}
637
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642
643void
644irq_set_chained_handler_and_data(unsigned int irq, irq_flow_handler_t handle,
645 void *data);
646
647void irq_modify_status(unsigned int irq, unsigned long clr, unsigned long set);
648
649static inline void irq_set_status_flags(unsigned int irq, unsigned long set)
650{
651 irq_modify_status(irq, 0, set);
652}
653
654static inline void irq_clear_status_flags(unsigned int irq, unsigned long clr)
655{
656 irq_modify_status(irq, clr, 0);
657}
658
659static inline void irq_set_noprobe(unsigned int irq)
660{
661 irq_modify_status(irq, 0, IRQ_NOPROBE);
662}
663
664static inline void irq_set_probe(unsigned int irq)
665{
666 irq_modify_status(irq, IRQ_NOPROBE, 0);
667}
668
669static inline void irq_set_nothread(unsigned int irq)
670{
671 irq_modify_status(irq, 0, IRQ_NOTHREAD);
672}
673
674static inline void irq_set_thread(unsigned int irq)
675{
676 irq_modify_status(irq, IRQ_NOTHREAD, 0);
677}
678
679static inline void irq_set_nested_thread(unsigned int irq, bool nest)
680{
681 if (nest)
682 irq_set_status_flags(irq, IRQ_NESTED_THREAD);
683 else
684 irq_clear_status_flags(irq, IRQ_NESTED_THREAD);
685}
686
687static inline void irq_set_percpu_devid_flags(unsigned int irq)
688{
689 irq_set_status_flags(irq,
690 IRQ_NOAUTOEN | IRQ_PER_CPU | IRQ_NOTHREAD |
691 IRQ_NOPROBE | IRQ_PER_CPU_DEVID);
692}
693
694
695extern int irq_set_chip(unsigned int irq, struct irq_chip *chip);
696extern int irq_set_handler_data(unsigned int irq, void *data);
697extern int irq_set_chip_data(unsigned int irq, void *data);
698extern int irq_set_irq_type(unsigned int irq, unsigned int type);
699extern int irq_set_msi_desc(unsigned int irq, struct msi_desc *entry);
700extern int irq_set_msi_desc_off(unsigned int irq_base, unsigned int irq_offset,
701 struct msi_desc *entry);
702extern struct irq_data *irq_get_irq_data(unsigned int irq);
703
704static inline struct irq_chip *irq_get_chip(unsigned int irq)
705{
706 struct irq_data *d = irq_get_irq_data(irq);
707 return d ? d->chip : NULL;
708}
709
710static inline struct irq_chip *irq_data_get_irq_chip(struct irq_data *d)
711{
712 return d->chip;
713}
714
715static inline void *irq_get_chip_data(unsigned int irq)
716{
717 struct irq_data *d = irq_get_irq_data(irq);
718 return d ? d->chip_data : NULL;
719}
720
721static inline void *irq_data_get_irq_chip_data(struct irq_data *d)
722{
723 return d->chip_data;
724}
725
726static inline void *irq_get_handler_data(unsigned int irq)
727{
728 struct irq_data *d = irq_get_irq_data(irq);
729 return d ? d->common->handler_data : NULL;
730}
731
732static inline void *irq_data_get_irq_handler_data(struct irq_data *d)
733{
734 return d->common->handler_data;
735}
736
737static inline struct msi_desc *irq_get_msi_desc(unsigned int irq)
738{
739 struct irq_data *d = irq_get_irq_data(irq);
740 return d ? d->common->msi_desc : NULL;
741}
742
743static inline struct msi_desc *irq_data_get_msi_desc(struct irq_data *d)
744{
745 return d->common->msi_desc;
746}
747
748static inline u32 irq_get_trigger_type(unsigned int irq)
749{
750 struct irq_data *d = irq_get_irq_data(irq);
751 return d ? irqd_get_trigger_type(d) : 0;
752}
753
754static inline int irq_common_data_get_node(struct irq_common_data *d)
755{
756#ifdef CONFIG_NUMA
757 return d->node;
758#else
759 return 0;
760#endif
761}
762
763static inline int irq_data_get_node(struct irq_data *d)
764{
765 return irq_common_data_get_node(d->common);
766}
767
768static inline struct cpumask *irq_get_affinity_mask(int irq)
769{
770 struct irq_data *d = irq_get_irq_data(irq);
771
772 return d ? d->common->affinity : NULL;
773}
774
775static inline struct cpumask *irq_data_get_affinity_mask(struct irq_data *d)
776{
777 return d->common->affinity;
778}
779
780#ifdef CONFIG_GENERIC_IRQ_EFFECTIVE_AFF_MASK
781static inline
782struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
783{
784 return d->common->effective_affinity;
785}
786static inline void irq_data_update_effective_affinity(struct irq_data *d,
787 const struct cpumask *m)
788{
789 cpumask_copy(d->common->effective_affinity, m);
790}
791#else
792static inline void irq_data_update_effective_affinity(struct irq_data *d,
793 const struct cpumask *m)
794{
795}
796static inline
797struct cpumask *irq_data_get_effective_affinity_mask(struct irq_data *d)
798{
799 return d->common->affinity;
800}
801#endif
802
803unsigned int arch_dynirq_lower_bound(unsigned int from);
804
805int __irq_alloc_descs(int irq, unsigned int from, unsigned int cnt, int node,
806 struct module *owner, const struct cpumask *affinity);
807
808int __devm_irq_alloc_descs(struct device *dev, int irq, unsigned int from,
809 unsigned int cnt, int node, struct module *owner,
810 const struct cpumask *affinity);
811
812
813#define irq_alloc_descs(irq, from, cnt, node) \
814 __irq_alloc_descs(irq, from, cnt, node, THIS_MODULE, NULL)
815
816#define irq_alloc_desc(node) \
817 irq_alloc_descs(-1, 0, 1, node)
818
819#define irq_alloc_desc_at(at, node) \
820 irq_alloc_descs(at, at, 1, node)
821
822#define irq_alloc_desc_from(from, node) \
823 irq_alloc_descs(-1, from, 1, node)
824
825#define irq_alloc_descs_from(from, cnt, node) \
826 irq_alloc_descs(-1, from, cnt, node)
827
828#define devm_irq_alloc_descs(dev, irq, from, cnt, node) \
829 __devm_irq_alloc_descs(dev, irq, from, cnt, node, THIS_MODULE, NULL)
830
831#define devm_irq_alloc_desc(dev, node) \
832 devm_irq_alloc_descs(dev, -1, 0, 1, node)
833
834#define devm_irq_alloc_desc_at(dev, at, node) \
835 devm_irq_alloc_descs(dev, at, at, 1, node)
836
837#define devm_irq_alloc_desc_from(dev, from, node) \
838 devm_irq_alloc_descs(dev, -1, from, 1, node)
839
840#define devm_irq_alloc_descs_from(dev, from, cnt, node) \
841 devm_irq_alloc_descs(dev, -1, from, cnt, node)
842
843void irq_free_descs(unsigned int irq, unsigned int cnt);
844static inline void irq_free_desc(unsigned int irq)
845{
846 irq_free_descs(irq, 1);
847}
848
849#ifdef CONFIG_GENERIC_IRQ_LEGACY_ALLOC_HWIRQ
850unsigned int irq_alloc_hwirqs(int cnt, int node);
851static inline unsigned int irq_alloc_hwirq(int node)
852{
853 return irq_alloc_hwirqs(1, node);
854}
855void irq_free_hwirqs(unsigned int from, int cnt);
856static inline void irq_free_hwirq(unsigned int irq)
857{
858 return irq_free_hwirqs(irq, 1);
859}
860int arch_setup_hwirq(unsigned int irq, int node);
861void arch_teardown_hwirq(unsigned int irq);
862#endif
863
864#ifdef CONFIG_GENERIC_IRQ_LEGACY
865void irq_init_desc(unsigned int irq);
866#endif
867
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878struct irq_chip_regs {
879 unsigned long enable;
880 unsigned long disable;
881 unsigned long mask;
882 unsigned long ack;
883 unsigned long eoi;
884 unsigned long type;
885 unsigned long polarity;
886};
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900
901struct irq_chip_type {
902 struct irq_chip chip;
903 struct irq_chip_regs regs;
904 irq_flow_handler_t handler;
905 u32 type;
906 u32 mask_cache_priv;
907 u32 *mask_cache;
908};
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943struct irq_chip_generic {
944 raw_spinlock_t lock;
945 void __iomem *reg_base;
946 u32 (*reg_readl)(void __iomem *addr);
947 void (*reg_writel)(u32 val, void __iomem *addr);
948 void (*suspend)(struct irq_chip_generic *gc);
949 void (*resume)(struct irq_chip_generic *gc);
950 unsigned int irq_base;
951 unsigned int irq_cnt;
952 u32 mask_cache;
953 u32 type_cache;
954 u32 polarity_cache;
955 u32 wake_enabled;
956 u32 wake_active;
957 unsigned int num_ct;
958 void *private;
959 unsigned long installed;
960 unsigned long unused;
961 struct irq_domain *domain;
962 struct list_head list;
963 struct irq_chip_type chip_types[0];
964};
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976enum irq_gc_flags {
977 IRQ_GC_INIT_MASK_CACHE = 1 << 0,
978 IRQ_GC_INIT_NESTED_LOCK = 1 << 1,
979 IRQ_GC_MASK_CACHE_PER_TYPE = 1 << 2,
980 IRQ_GC_NO_MASK = 1 << 3,
981 IRQ_GC_BE_IO = 1 << 4,
982};
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992
993struct irq_domain_chip_generic {
994 unsigned int irqs_per_chip;
995 unsigned int num_chips;
996 unsigned int irq_flags_to_clear;
997 unsigned int irq_flags_to_set;
998 enum irq_gc_flags gc_flags;
999 struct irq_chip_generic *gc[0];
1000};
1001
1002
1003void irq_gc_noop(struct irq_data *d);
1004void irq_gc_mask_disable_reg(struct irq_data *d);
1005void irq_gc_mask_set_bit(struct irq_data *d);
1006void irq_gc_mask_clr_bit(struct irq_data *d);
1007void irq_gc_unmask_enable_reg(struct irq_data *d);
1008void irq_gc_ack_set_bit(struct irq_data *d);
1009void irq_gc_ack_clr_bit(struct irq_data *d);
1010void irq_gc_mask_disable_reg_and_ack(struct irq_data *d);
1011void irq_gc_eoi(struct irq_data *d);
1012int irq_gc_set_wake(struct irq_data *d, unsigned int on);
1013
1014
1015int irq_map_generic_chip(struct irq_domain *d, unsigned int virq,
1016 irq_hw_number_t hw_irq);
1017struct irq_chip_generic *
1018irq_alloc_generic_chip(const char *name, int nr_ct, unsigned int irq_base,
1019 void __iomem *reg_base, irq_flow_handler_t handler);
1020void irq_setup_generic_chip(struct irq_chip_generic *gc, u32 msk,
1021 enum irq_gc_flags flags, unsigned int clr,
1022 unsigned int set);
1023int irq_setup_alt_chip(struct irq_data *d, unsigned int type);
1024void irq_remove_generic_chip(struct irq_chip_generic *gc, u32 msk,
1025 unsigned int clr, unsigned int set);
1026
1027struct irq_chip_generic *
1028devm_irq_alloc_generic_chip(struct device *dev, const char *name, int num_ct,
1029 unsigned int irq_base, void __iomem *reg_base,
1030 irq_flow_handler_t handler);
1031int devm_irq_setup_generic_chip(struct device *dev, struct irq_chip_generic *gc,
1032 u32 msk, enum irq_gc_flags flags,
1033 unsigned int clr, unsigned int set);
1034
1035struct irq_chip_generic *irq_get_domain_generic_chip(struct irq_domain *d, unsigned int hw_irq);
1036
1037int __irq_alloc_domain_generic_chips(struct irq_domain *d, int irqs_per_chip,
1038 int num_ct, const char *name,
1039 irq_flow_handler_t handler,
1040 unsigned int clr, unsigned int set,
1041 enum irq_gc_flags flags);
1042
1043#define irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name, \
1044 handler, clr, set, flags) \
1045({ \
1046 MAYBE_BUILD_BUG_ON(irqs_per_chip > 32); \
1047 __irq_alloc_domain_generic_chips(d, irqs_per_chip, num_ct, name,\
1048 handler, clr, set, flags); \
1049})
1050
1051static inline void irq_free_generic_chip(struct irq_chip_generic *gc)
1052{
1053 kfree(gc);
1054}
1055
1056static inline void irq_destroy_generic_chip(struct irq_chip_generic *gc,
1057 u32 msk, unsigned int clr,
1058 unsigned int set)
1059{
1060 irq_remove_generic_chip(gc, msk, clr, set);
1061 irq_free_generic_chip(gc);
1062}
1063
1064static inline struct irq_chip_type *irq_data_get_chip_type(struct irq_data *d)
1065{
1066 return container_of(d->chip, struct irq_chip_type, chip);
1067}
1068
1069#define IRQ_MSK(n) (u32)((n) < 32 ? ((1 << (n)) - 1) : UINT_MAX)
1070
1071#ifdef CONFIG_SMP
1072static inline void irq_gc_lock(struct irq_chip_generic *gc)
1073{
1074 raw_spin_lock(&gc->lock);
1075}
1076
1077static inline void irq_gc_unlock(struct irq_chip_generic *gc)
1078{
1079 raw_spin_unlock(&gc->lock);
1080}
1081#else
1082static inline void irq_gc_lock(struct irq_chip_generic *gc) { }
1083static inline void irq_gc_unlock(struct irq_chip_generic *gc) { }
1084#endif
1085
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1090#define irq_gc_lock_irqsave(gc, flags) \
1091 raw_spin_lock_irqsave(&(gc)->lock, flags)
1092
1093#define irq_gc_unlock_irqrestore(gc, flags) \
1094 raw_spin_unlock_irqrestore(&(gc)->lock, flags)
1095
1096static inline void irq_reg_writel(struct irq_chip_generic *gc,
1097 u32 val, int reg_offset)
1098{
1099 if (gc->reg_writel)
1100 gc->reg_writel(val, gc->reg_base + reg_offset);
1101 else
1102 writel(val, gc->reg_base + reg_offset);
1103}
1104
1105static inline u32 irq_reg_readl(struct irq_chip_generic *gc,
1106 int reg_offset)
1107{
1108 if (gc->reg_readl)
1109 return gc->reg_readl(gc->reg_base + reg_offset);
1110 else
1111 return readl(gc->reg_base + reg_offset);
1112}
1113
1114
1115#define INVALID_HWIRQ (~0UL)
1116irq_hw_number_t ipi_get_hwirq(unsigned int irq, unsigned int cpu);
1117int __ipi_send_single(struct irq_desc *desc, unsigned int cpu);
1118int __ipi_send_mask(struct irq_desc *desc, const struct cpumask *dest);
1119int ipi_send_single(unsigned int virq, unsigned int cpu);
1120int ipi_send_mask(unsigned int virq, const struct cpumask *dest);
1121
1122#endif
1123