LXR linux/include/linux/mfd/tmio.h

   1#ifndef MFD_TMIO_H
   2#define MFD_TMIO_H
   3
   4#include <linux/device.h>
   5#include <linux/fb.h>
   6#include <linux/io.h>
   7#include <linux/jiffies.h>
   8#include <linux/mmc/card.h>
   9#include <linux/platform_device.h>
  10#include <linux/pm_runtime.h>
  11
  12#define tmio_ioread8(addr) readb(addr)
  13#define tmio_ioread16(addr) readw(addr)
  14#define tmio_ioread16_rep(r, b, l) readsw(r, b, l)
  15#define tmio_ioread32(addr) \
  16        (((u32)readw((addr))) | (((u32)readw((addr) + 2)) << 16))
  17
  18#define tmio_iowrite8(val, addr) writeb((val), (addr))
  19#define tmio_iowrite16(val, addr) writew((val), (addr))
  20#define tmio_iowrite16_rep(r, b, l) writesw(r, b, l)
  21#define tmio_iowrite32(val, addr) \
  22        do { \
  23                writew((val),       (addr)); \
  24                writew((val) >> 16, (addr) + 2); \
  25        } while (0)
  26
  27#define CNF_CMD     0x04
  28#define CNF_CTL_BASE   0x10
  29#define CNF_INT_PIN  0x3d
  30#define CNF_STOP_CLK_CTL 0x40
  31#define CNF_GCLK_CTL 0x41
  32#define CNF_SD_CLK_MODE 0x42
  33#define CNF_PIN_STATUS 0x44
  34#define CNF_PWR_CTL_1 0x48
  35#define CNF_PWR_CTL_2 0x49
  36#define CNF_PWR_CTL_3 0x4a
  37#define CNF_CARD_DETECT_MODE 0x4c
  38#define CNF_SD_SLOT 0x50
  39#define CNF_EXT_GCLK_CTL_1 0xf0
  40#define CNF_EXT_GCLK_CTL_2 0xf1
  41#define CNF_EXT_GCLK_CTL_3 0xf9
  42#define CNF_SD_LED_EN_1 0xfa
  43#define CNF_SD_LED_EN_2 0xfe
  44
  45#define   SDCREN 0x2   /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/
  46
  47#define sd_config_write8(base, shift, reg, val) \
  48        tmio_iowrite8((val), (base) + ((reg) << (shift)))
  49#define sd_config_write16(base, shift, reg, val) \
  50        tmio_iowrite16((val), (base) + ((reg) << (shift)))
  51#define sd_config_write32(base, shift, reg, val) \
  52        do { \
  53                tmio_iowrite16((val), (base) + ((reg) << (shift)));   \
  54                tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \
  55        } while (0)
  56
  57/* tmio MMC platform flags */
  58#define TMIO_MMC_WRPROTECT_DISABLE      BIT(0)
  59/*
  60 * Some controllers can support a 2-byte block size when the bus width
  61 * is configured in 4-bit mode.
  62 */
  63#define TMIO_MMC_BLKSZ_2BYTES           BIT(1)
  64/*
  65 * Some controllers can support SDIO IRQ signalling.
  66 */
  67#define TMIO_MMC_SDIO_IRQ               BIT(2)
  68
  69/* Some features are only available or tested on R-Car Gen2 or later */
  70#define TMIO_MMC_MIN_RCAR2              BIT(3)
  71
  72/*
  73 * Some controllers require waiting for the SD bus to become
  74 * idle before writing to some registers.
  75 */
  76#define TMIO_MMC_HAS_IDLE_WAIT          BIT(4)
  77/*
  78 * A GPIO is used for card hotplug detection. We need an extra flag for this,
  79 * because 0 is a valid GPIO number too, and requiring users to specify
  80 * cd_gpio < 0 to disable GPIO hotplug would break backwards compatibility.
  81 */
  82#define TMIO_MMC_USE_GPIO_CD            BIT(5)
  83
  84/*
  85 * Some controllers doesn't have over 0x100 register.
  86 * it is used to checking accessibility of
  87 * CTL_SD_CARD_CLK_CTL / CTL_CLK_AND_WAIT_CTL
  88 */
  89#define TMIO_MMC_HAVE_HIGH_REG          BIT(6)
  90
  91/*
  92 * Some controllers have CMD12 automatically
  93 * issue/non-issue register
  94 */
  95#define TMIO_MMC_HAVE_CMD12_CTRL        BIT(7)
  96
  97/* Controller has some SDIO status bits which must be 1 */
  98#define TMIO_MMC_SDIO_STATUS_SETBITS    BIT(8)
  99
 100/*
 101 * Some controllers have a 32-bit wide data port register
 102 */
 103#define TMIO_MMC_32BIT_DATA_PORT        BIT(9)
 104
 105/*
 106 * Some controllers allows to set SDx actual clock
 107 */
 108#define TMIO_MMC_CLK_ACTUAL             BIT(10)
 109
 110int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
 111int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
 112void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
 113void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);
 114
 115struct dma_chan;
 116
 117/*
 118 * data for the MMC controller
 119 */
 120struct tmio_mmc_data {
 121        void                            *chan_priv_tx;
 122        void                            *chan_priv_rx;
 123        unsigned int                    hclk;
 124        unsigned long                   capabilities;
 125        unsigned long                   capabilities2;
 126        unsigned long                   flags;
 127        u32                             ocr_mask;       /* available voltages */
 128        unsigned int                    cd_gpio;
 129        int                             alignment_shift;
 130        dma_addr_t                      dma_rx_offset;
 131        void (*set_pwr)(struct platform_device *host, int state);
 132        void (*set_clk_div)(struct platform_device *host, int state);
 133};
 134
 135/*
 136 * data for the NAND controller
 137 */
 138struct tmio_nand_data {
 139        struct nand_bbt_descr   *badblock_pattern;
 140        struct mtd_partition    *partition;
 141        unsigned int            num_partitions;
 142};
 143
 144#define FBIO_TMIO_ACC_WRITE     0x7C639300
 145#define FBIO_TMIO_ACC_SYNC      0x7C639301
 146
 147struct tmio_fb_data {
 148        int                     (*lcd_set_power)(struct platform_device *fb_dev,
 149                                                 bool on);
 150        int                     (*lcd_mode)(struct platform_device *fb_dev,
 151                                            const struct fb_videomode *mode);
 152        int                     num_modes;
 153        struct fb_videomode     *modes;
 154
 155        /* in mm: size of screen */
 156        int                     height;
 157        int                     width;
 158};
 159
 160#endif
 161