LXR linux/include/linux/mtd/spi-nor.h

   1/*
   2 * Copyright (C) 2014 Freescale Semiconductor, Inc.
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License as published by
   6 * the Free Software Foundation; either version 2 of the License, or
   7 * (at your option) any later version.
   8 */
   9
  10#ifndef __LINUX_MTD_SPI_NOR_H
  11#define __LINUX_MTD_SPI_NOR_H
  12
  13#include <linux/bitops.h>
  14#include <linux/mtd/cfi.h>
  15#include <linux/mtd/mtd.h>
  16
  17/*
  18 * Manufacturer IDs
  19 *
  20 * The first byte returned from the flash after sending opcode SPINOR_OP_RDID.
  21 * Sometimes these are the same as CFI IDs, but sometimes they aren't.
  22 */
  23#define SNOR_MFR_ATMEL          CFI_MFR_ATMEL
  24#define SNOR_MFR_GIGADEVICE     0xc8
  25#define SNOR_MFR_INTEL          CFI_MFR_INTEL
  26#define SNOR_MFR_MICRON         CFI_MFR_ST /* ST Micro <--> Micron */
  27#define SNOR_MFR_MACRONIX       CFI_MFR_MACRONIX
  28#define SNOR_MFR_SPANSION       CFI_MFR_AMD
  29#define SNOR_MFR_SST            CFI_MFR_SST
  30#define SNOR_MFR_WINBOND        0xef /* Also used by some Spansion */
  31
  32/*
  33 * Note on opcode nomenclature: some opcodes have a format like
  34 * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
  35 * of I/O lines used for the opcode, address, and data (respectively). The
  36 * FUNCTION has an optional suffix of '4', to represent an opcode which
  37 * requires a 4-byte (32-bit) address.
  38 */
  39
  40/* Flash opcodes. */
  41#define SPINOR_OP_WREN          0x06    /* Write enable */
  42#define SPINOR_OP_RDSR          0x05    /* Read status register */
  43#define SPINOR_OP_WRSR          0x01    /* Write status register 1 byte */
  44#define SPINOR_OP_READ          0x03    /* Read data bytes (low frequency) */
  45#define SPINOR_OP_READ_FAST     0x0b    /* Read data bytes (high frequency) */
  46#define SPINOR_OP_READ_1_1_2    0x3b    /* Read data bytes (Dual Output SPI) */
  47#define SPINOR_OP_READ_1_2_2    0xbb    /* Read data bytes (Dual I/O SPI) */
  48#define SPINOR_OP_READ_1_1_4    0x6b    /* Read data bytes (Quad Output SPI) */
  49#define SPINOR_OP_READ_1_4_4    0xeb    /* Read data bytes (Quad I/O SPI) */
  50#define SPINOR_OP_PP            0x02    /* Page program (up to 256 bytes) */
  51#define SPINOR_OP_PP_1_1_4      0x32    /* Quad page program */
  52#define SPINOR_OP_PP_1_4_4      0x38    /* Quad page program */
  53#define SPINOR_OP_BE_4K         0x20    /* Erase 4KiB block */
  54#define SPINOR_OP_BE_4K_PMC     0xd7    /* Erase 4KiB block on PMC chips */
  55#define SPINOR_OP_BE_32K        0x52    /* Erase 32KiB block */
  56#define SPINOR_OP_CHIP_ERASE    0xc7    /* Erase whole flash chip */
  57#define SPINOR_OP_SE            0xd8    /* Sector erase (usually 64KiB) */
  58#define SPINOR_OP_RDID          0x9f    /* Read JEDEC ID */
  59#define SPINOR_OP_RDCR          0x35    /* Read configuration register */
  60#define SPINOR_OP_RDFSR         0x70    /* Read flag status register */
  61
  62/* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
  63#define SPINOR_OP_READ_4B       0x13    /* Read data bytes (low frequency) */
  64#define SPINOR_OP_READ_FAST_4B  0x0c    /* Read data bytes (high frequency) */
  65#define SPINOR_OP_READ_1_1_2_4B 0x3c    /* Read data bytes (Dual Output SPI) */
  66#define SPINOR_OP_READ_1_2_2_4B 0xbc    /* Read data bytes (Dual I/O SPI) */
  67#define SPINOR_OP_READ_1_1_4_4B 0x6c    /* Read data bytes (Quad Output SPI) */
  68#define SPINOR_OP_READ_1_4_4_4B 0xec    /* Read data bytes (Quad I/O SPI) */
  69#define SPINOR_OP_PP_4B         0x12    /* Page program (up to 256 bytes) */
  70#define SPINOR_OP_PP_1_1_4_4B   0x34    /* Quad page program */
  71#define SPINOR_OP_PP_1_4_4_4B   0x3e    /* Quad page program */
  72#define SPINOR_OP_BE_4K_4B      0x21    /* Erase 4KiB block */
  73#define SPINOR_OP_BE_32K_4B     0x5c    /* Erase 32KiB block */
  74#define SPINOR_OP_SE_4B         0xdc    /* Sector erase (usually 64KiB) */
  75
  76/* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
  77#define SPINOR_OP_READ_1_1_1_DTR        0x0d
  78#define SPINOR_OP_READ_1_2_2_DTR        0xbd
  79#define SPINOR_OP_READ_1_4_4_DTR        0xed
  80
  81#define SPINOR_OP_READ_1_1_1_DTR_4B     0x0e
  82#define SPINOR_OP_READ_1_2_2_DTR_4B     0xbe
  83#define SPINOR_OP_READ_1_4_4_DTR_4B     0xee
  84
  85/* Used for SST flashes only. */
  86#define SPINOR_OP_BP            0x02    /* Byte program */
  87#define SPINOR_OP_WRDI          0x04    /* Write disable */
  88#define SPINOR_OP_AAI_WP        0xad    /* Auto address increment word program */
  89
  90/* Used for S3AN flashes only */
  91#define SPINOR_OP_XSE           0x50    /* Sector erase */
  92#define SPINOR_OP_XPP           0x82    /* Page program */
  93#define SPINOR_OP_XRDSR         0xd7    /* Read status register */
  94
  95#define XSR_PAGESIZE            BIT(0)  /* Page size in Po2 or Linear */
  96#define XSR_RDY                 BIT(7)  /* Ready */
  97
  98
  99/* Used for Macronix and Winbond flashes. */
 100#define SPINOR_OP_EN4B          0xb7    /* Enter 4-byte mode */
 101#define SPINOR_OP_EX4B          0xe9    /* Exit 4-byte mode */
 102
 103/* Used for Spansion flashes only. */
 104#define SPINOR_OP_BRWR          0x17    /* Bank register write */
 105
 106/* Used for Micron flashes only. */
 107#define SPINOR_OP_RD_EVCR      0x65    /* Read EVCR register */
 108#define SPINOR_OP_WD_EVCR      0x61    /* Write EVCR register */
 109
 110/* Status Register bits. */
 111#define SR_WIP                  BIT(0)  /* Write in progress */
 112#define SR_WEL                  BIT(1)  /* Write enable latch */
 113/* meaning of other SR_* bits may differ between vendors */
 114#define SR_BP0                  BIT(2)  /* Block protect 0 */
 115#define SR_BP1                  BIT(3)  /* Block protect 1 */
 116#define SR_BP2                  BIT(4)  /* Block protect 2 */
 117#define SR_TB                   BIT(5)  /* Top/Bottom protect */
 118#define SR_SRWD                 BIT(7)  /* SR write protect */
 119
 120#define SR_QUAD_EN_MX           BIT(6)  /* Macronix Quad I/O */
 121
 122/* Enhanced Volatile Configuration Register bits */
 123#define EVCR_QUAD_EN_MICRON     BIT(7)  /* Micron Quad I/O */
 124
 125/* Flag Status Register bits */
 126#define FSR_READY               BIT(7)
 127
 128/* Configuration Register bits. */
 129#define CR_QUAD_EN_SPAN         BIT(1)  /* Spansion Quad I/O */
 130
 131/* Supported SPI protocols */
 132#define SNOR_PROTO_INST_MASK    GENMASK(23, 16)
 133#define SNOR_PROTO_INST_SHIFT   16
 134#define SNOR_PROTO_INST(_nbits) \
 135        ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
 136         SNOR_PROTO_INST_MASK)
 137
 138#define SNOR_PROTO_ADDR_MASK    GENMASK(15, 8)
 139#define SNOR_PROTO_ADDR_SHIFT   8
 140#define SNOR_PROTO_ADDR(_nbits) \
 141        ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
 142         SNOR_PROTO_ADDR_MASK)
 143
 144#define SNOR_PROTO_DATA_MASK    GENMASK(7, 0)
 145#define SNOR_PROTO_DATA_SHIFT   0
 146#define SNOR_PROTO_DATA(_nbits) \
 147        ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
 148         SNOR_PROTO_DATA_MASK)
 149
 150#define SNOR_PROTO_IS_DTR       BIT(24) /* Double Transfer Rate */
 151
 152#define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits)   \
 153        (SNOR_PROTO_INST(_inst_nbits) |                         \
 154         SNOR_PROTO_ADDR(_addr_nbits) |                         \
 155         SNOR_PROTO_DATA(_data_nbits))
 156#define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits)   \
 157        (SNOR_PROTO_IS_DTR |                                    \
 158         SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
 159
 160enum spi_nor_protocol {
 161        SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
 162        SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
 163        SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
 164        SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
 165        SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
 166        SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
 167        SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
 168        SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
 169        SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
 170        SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
 171
 172        SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
 173        SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
 174        SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
 175        SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
 176};
 177
 178static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
 179{
 180        return !!(proto & SNOR_PROTO_IS_DTR);
 181}
 182
 183static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
 184{
 185        return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
 186                SNOR_PROTO_INST_SHIFT;
 187}
 188
 189static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
 190{
 191        return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
 192                SNOR_PROTO_ADDR_SHIFT;
 193}
 194
 195static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
 196{
 197        return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
 198                SNOR_PROTO_DATA_SHIFT;
 199}
 200
 201static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
 202{
 203        return spi_nor_get_protocol_data_nbits(proto);
 204}
 205
 206#define SPI_NOR_MAX_CMD_SIZE    8
 207enum spi_nor_ops {
 208        SPI_NOR_OPS_READ = 0,
 209        SPI_NOR_OPS_WRITE,
 210        SPI_NOR_OPS_ERASE,
 211        SPI_NOR_OPS_LOCK,
 212        SPI_NOR_OPS_UNLOCK,
 213};
 214
 215enum spi_nor_option_flags {
 216        SNOR_F_USE_FSR          = BIT(0),
 217        SNOR_F_HAS_SR_TB        = BIT(1),
 218        SNOR_F_NO_OP_CHIP_ERASE = BIT(2),
 219        SNOR_F_S3AN_ADDR_DEFAULT = BIT(3),
 220        SNOR_F_READY_XSR_RDY    = BIT(4),
 221};
 222
 223/**
 224 * struct spi_nor - Structure for defining a the SPI NOR layer
 225 * @mtd:                point to a mtd_info structure
 226 * @lock:               the lock for the read/write/erase/lock/unlock operations
 227 * @dev:                point to a spi device, or a spi nor controller device.
 228 * @page_size:          the page size of the SPI NOR
 229 * @addr_width:         number of address bytes
 230 * @erase_opcode:       the opcode for erasing a sector
 231 * @read_opcode:        the read opcode
 232 * @read_dummy:         the dummy needed by the read operation
 233 * @program_opcode:     the program opcode
 234 * @sst_write_second:   used by the SST write operation
 235 * @flags:              flag options for the current SPI-NOR (SNOR_F_*)
 236 * @read_proto:         the SPI protocol for read operations
 237 * @write_proto:        the SPI protocol for write operations
 238 * @reg_proto           the SPI protocol for read_reg/write_reg/erase operations
 239 * @cmd_buf:            used by the write_reg
 240 * @prepare:            [OPTIONAL] do some preparations for the
 241 *                      read/write/erase/lock/unlock operations
 242 * @unprepare:          [OPTIONAL] do some post work after the
 243 *                      read/write/erase/lock/unlock operations
 244 * @read_reg:           [DRIVER-SPECIFIC] read out the register
 245 * @write_reg:          [DRIVER-SPECIFIC] write data to the register
 246 * @read:               [DRIVER-SPECIFIC] read data from the SPI NOR
 247 * @write:              [DRIVER-SPECIFIC] write data to the SPI NOR
 248 * @erase:              [DRIVER-SPECIFIC] erase a sector of the SPI NOR
 249 *                      at the offset @offs; if not provided by the driver,
 250 *                      spi-nor will send the erase opcode via write_reg()
 251 * @flash_lock:         [FLASH-SPECIFIC] lock a region of the SPI NOR
 252 * @flash_unlock:       [FLASH-SPECIFIC] unlock a region of the SPI NOR
 253 * @flash_is_locked:    [FLASH-SPECIFIC] check if a region of the SPI NOR is
 254 *                      completely locked
 255 * @priv:               the private data
 256 */
 257struct spi_nor {
 258        struct mtd_info         mtd;
 259        struct mutex            lock;
 260        struct device           *dev;
 261        u32                     page_size;
 262        u8                      addr_width;
 263        u8                      erase_opcode;
 264        u8                      read_opcode;
 265        u8                      read_dummy;
 266        u8                      program_opcode;
 267        enum spi_nor_protocol   read_proto;
 268        enum spi_nor_protocol   write_proto;
 269        enum spi_nor_protocol   reg_proto;
 270        bool                    sst_write_second;
 271        u32                     flags;
 272        u8                      cmd_buf[SPI_NOR_MAX_CMD_SIZE];
 273
 274        int (*prepare)(struct spi_nor *nor, enum spi_nor_ops ops);
 275        void (*unprepare)(struct spi_nor *nor, enum spi_nor_ops ops);
 276        int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
 277        int (*write_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, int len);
 278
 279        ssize_t (*read)(struct spi_nor *nor, loff_t from,
 280                        size_t len, u_char *read_buf);
 281        ssize_t (*write)(struct spi_nor *nor, loff_t to,
 282                        size_t len, const u_char *write_buf);
 283        int (*erase)(struct spi_nor *nor, loff_t offs);
 284
 285        int (*flash_lock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
 286        int (*flash_unlock)(struct spi_nor *nor, loff_t ofs, uint64_t len);
 287        int (*flash_is_locked)(struct spi_nor *nor, loff_t ofs, uint64_t len);
 288
 289        void *priv;
 290};
 291
 292static inline void spi_nor_set_flash_node(struct spi_nor *nor,
 293                                          struct device_node *np)
 294{
 295        mtd_set_of_node(&nor->mtd, np);
 296}
 297
 298static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
 299{
 300        return mtd_get_of_node(&nor->mtd);
 301}
 302
 303/**
 304 * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
 305 * supported by the SPI controller (bus master).
 306 * @mask:               the bitmask listing all the supported hw capabilies
 307 */
 308struct spi_nor_hwcaps {
 309        u32     mask;
 310};
 311
 312/*
 313 *(Fast) Read capabilities.
 314 * MUST be ordered by priority: the higher bit position, the higher priority.
 315 * As a matter of performances, it is relevant to use Octo SPI protocols first,
 316 * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
 317 * (Slow) Read.
 318 */
 319#define SNOR_HWCAPS_READ_MASK           GENMASK(14, 0)
 320#define SNOR_HWCAPS_READ                BIT(0)
 321#define SNOR_HWCAPS_READ_FAST           BIT(1)
 322#define SNOR_HWCAPS_READ_1_1_1_DTR      BIT(2)
 323
 324#define SNOR_HWCAPS_READ_DUAL           GENMASK(6, 3)
 325#define SNOR_HWCAPS_READ_1_1_2          BIT(3)
 326#define SNOR_HWCAPS_READ_1_2_2          BIT(4)
 327#define SNOR_HWCAPS_READ_2_2_2          BIT(5)
 328#define SNOR_HWCAPS_READ_1_2_2_DTR      BIT(6)
 329
 330#define SNOR_HWCAPS_READ_QUAD           GENMASK(10, 7)
 331#define SNOR_HWCAPS_READ_1_1_4          BIT(7)
 332#define SNOR_HWCAPS_READ_1_4_4          BIT(8)
 333#define SNOR_HWCAPS_READ_4_4_4          BIT(9)
 334#define SNOR_HWCAPS_READ_1_4_4_DTR      BIT(10)
 335
 336#define SNOR_HWCPAS_READ_OCTO           GENMASK(14, 11)
 337#define SNOR_HWCAPS_READ_1_1_8          BIT(11)
 338#define SNOR_HWCAPS_READ_1_8_8          BIT(12)
 339#define SNOR_HWCAPS_READ_8_8_8          BIT(13)
 340#define SNOR_HWCAPS_READ_1_8_8_DTR      BIT(14)
 341
 342/*
 343 * Page Program capabilities.
 344 * MUST be ordered by priority: the higher bit position, the higher priority.
 345 * Like (Fast) Read capabilities, Octo/Quad SPI protocols are preferred to the
 346 * legacy SPI 1-1-1 protocol.
 347 * Note that Dual Page Programs are not supported because there is no existing
 348 * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
 349 * implements such commands.
 350 */
 351#define SNOR_HWCAPS_PP_MASK     GENMASK(22, 16)
 352#define SNOR_HWCAPS_PP          BIT(16)
 353
 354#define SNOR_HWCAPS_PP_QUAD     GENMASK(19, 17)
 355#define SNOR_HWCAPS_PP_1_1_4    BIT(17)
 356#define SNOR_HWCAPS_PP_1_4_4    BIT(18)
 357#define SNOR_HWCAPS_PP_4_4_4    BIT(19)
 358
 359#define SNOR_HWCAPS_PP_OCTO     GENMASK(22, 20)
 360#define SNOR_HWCAPS_PP_1_1_8    BIT(20)
 361#define SNOR_HWCAPS_PP_1_8_8    BIT(21)
 362#define SNOR_HWCAPS_PP_8_8_8    BIT(22)
 363
 364/**
 365 * spi_nor_scan() - scan the SPI NOR
 366 * @nor:        the spi_nor structure
 367 * @name:       the chip type name
 368 * @hwcaps:     the hardware capabilities supported by the controller driver
 369 *
 370 * The drivers can use this fuction to scan the SPI NOR.
 371 * In the scanning, it will try to get all the necessary information to
 372 * fill the mtd_info{} and the spi_nor{}.
 373 *
 374 * The chip type name can be provided through the @name parameter.
 375 *
 376 * Return: 0 for success, others for failure.
 377 */
 378int spi_nor_scan(struct spi_nor *nor, const char *name,
 379                 const struct spi_nor_hwcaps *hwcaps);
 380
 381#endif
 382