LXR linux/include/linux/qcom

   1/* Copyright (c) 2010-2015, The Linux Foundation. All rights reserved.
   2 * Copyright (C) 2015 Linaro Ltd.
   3 *
   4 * This program is free software; you can redistribute it and/or modify
   5 * it under the terms of the GNU General Public License version 2 and
   6 * only version 2 as published by the Free Software Foundation.
   7 *
   8 * This program is distributed in the hope that it will be useful,
   9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11 * GNU General Public License for more details.
  12 */
  13#ifndef __QCOM_SCM_H
  14#define __QCOM_SCM_H
  15
  16#define QCOM_SCM_VERSION(major, minor)  (((major) << 16) | ((minor) & 0xFF))
  17#define QCOM_SCM_CPU_PWR_DOWN_L2_ON     0x0
  18#define QCOM_SCM_CPU_PWR_DOWN_L2_OFF    0x1
  19#define QCOM_SCM_HDCP_MAX_REQ_CNT       5
  20
  21struct qcom_scm_hdcp_req {
  22        u32 addr;
  23        u32 val;
  24};
  25
  26#if IS_ENABLED(CONFIG_QCOM_SCM)
  27extern int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus);
  28extern int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus);
  29extern bool qcom_scm_is_available(void);
  30extern bool qcom_scm_hdcp_available(void);
  31extern int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
  32                             u32 *resp);
  33extern bool qcom_scm_pas_supported(u32 peripheral);
  34extern int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
  35                                   size_t size);
  36extern int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
  37                                  phys_addr_t size);
  38extern int qcom_scm_pas_auth_and_reset(u32 peripheral);
  39extern int qcom_scm_pas_shutdown(u32 peripheral);
  40extern void qcom_scm_cpu_power_down(u32 flags);
  41extern u32 qcom_scm_get_version(void);
  42extern int qcom_scm_set_remote_state(u32 state, u32 id);
  43extern int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
  44extern int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
  45extern int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
  46#else
  47static inline
  48int qcom_scm_set_cold_boot_addr(void *entry, const cpumask_t *cpus)
  49{
  50        return -ENODEV;
  51}
  52static inline
  53int qcom_scm_set_warm_boot_addr(void *entry, const cpumask_t *cpus)
  54{
  55        return -ENODEV;
  56}
  57static inline bool qcom_scm_is_available(void) { return false; }
  58static inline bool qcom_scm_hdcp_available(void) { return false; }
  59static inline int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt,
  60                                    u32 *resp) { return -ENODEV; }
  61static inline bool qcom_scm_pas_supported(u32 peripheral) { return false; }
  62static inline int qcom_scm_pas_init_image(u32 peripheral, const void *metadata,
  63                                          size_t size) { return -ENODEV; }
  64static inline int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr,
  65                                         phys_addr_t size) { return -ENODEV; }
  66static inline int
  67qcom_scm_pas_auth_and_reset(u32 peripheral) { return -ENODEV; }
  68static inline int qcom_scm_pas_shutdown(u32 peripheral) { return -ENODEV; }
  69static inline void qcom_scm_cpu_power_down(u32 flags) {}
  70static inline u32 qcom_scm_get_version(void) { return 0; }
  71static inline u32
  72qcom_scm_set_remote_state(u32 state,u32 id) { return -ENODEV; }
  73static inline int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare) { return -ENODEV; }
  74static inline int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size) { return -ENODEV; }
  75static inline int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare) { return -ENODEV; }
  76#endif
  77#endif
  78