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12#include <linux/module.h>
13#include <linux/moduleparam.h>
14#include <linux/init.h>
15#include <linux/delay.h>
16#include <linux/pm.h>
17#include <linux/i2c.h>
18#include <linux/platform_device.h>
19#include <linux/spi/spi.h>
20#include <linux/acpi.h>
21#include <linux/gpio.h>
22#include <linux/of_gpio.h>
23#include <linux/regulator/consumer.h>
24#include <linux/mutex.h>
25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/jack.h>
29#include <sound/soc.h>
30#include <sound/soc-dapm.h>
31#include <sound/initval.h>
32#include <sound/tlv.h>
33#include <sound/rt5665.h>
34
35#include "rl6231.h"
36#include "rt5665.h"
37
38#define RT5665_NUM_SUPPLIES 3
39
40static const char *rt5665_supply_names[RT5665_NUM_SUPPLIES] = {
41 "AVDD",
42 "MICVDD",
43 "VBAT",
44};
45
46struct rt5665_priv {
47 struct snd_soc_codec *codec;
48 struct rt5665_platform_data pdata;
49 struct regmap *regmap;
50 struct gpio_desc *gpiod_ldo1_en;
51 struct gpio_desc *gpiod_reset;
52 struct snd_soc_jack *hs_jack;
53 struct regulator_bulk_data supplies[RT5665_NUM_SUPPLIES];
54 struct delayed_work jack_detect_work;
55 struct delayed_work calibrate_work;
56 struct delayed_work jd_check_work;
57 struct mutex calibrate_mutex;
58
59 int sysclk;
60 int sysclk_src;
61 int lrck[RT5665_AIFS];
62 int bclk[RT5665_AIFS];
63 int master[RT5665_AIFS];
64 int id;
65
66 int pll_src;
67 int pll_in;
68 int pll_out;
69
70 int jack_type;
71 int irq_work_delay_time;
72 unsigned int sar_adc_value;
73 bool calibration_done;
74};
75
76static const struct reg_default rt5665_reg[] = {
77 {0x0000, 0x0000},
78 {0x0001, 0xc8c8},
79 {0x0002, 0x8080},
80 {0x0003, 0x8000},
81 {0x0004, 0xc80a},
82 {0x0005, 0x0000},
83 {0x0006, 0x0000},
84 {0x0007, 0x0000},
85 {0x000a, 0x0000},
86 {0x000b, 0x0000},
87 {0x000c, 0x0000},
88 {0x000d, 0x0000},
89 {0x000f, 0x0808},
90 {0x0010, 0x4040},
91 {0x0011, 0x0000},
92 {0x0012, 0x1404},
93 {0x0013, 0x1000},
94 {0x0014, 0xa00a},
95 {0x0015, 0x0404},
96 {0x0016, 0x0404},
97 {0x0017, 0x0011},
98 {0x0018, 0xafaf},
99 {0x0019, 0xafaf},
100 {0x001a, 0xafaf},
101 {0x001b, 0x0011},
102 {0x001c, 0x2f2f},
103 {0x001d, 0x2f2f},
104 {0x001e, 0x2f2f},
105 {0x001f, 0x0000},
106 {0x0020, 0x0000},
107 {0x0021, 0x0000},
108 {0x0022, 0x5757},
109 {0x0023, 0x0039},
110 {0x0026, 0xc0c0},
111 {0x0027, 0xc0c0},
112 {0x0028, 0xc0c0},
113 {0x0029, 0x8080},
114 {0x002a, 0xaaaa},
115 {0x002b, 0xaaaa},
116 {0x002c, 0xaba8},
117 {0x002d, 0x0000},
118 {0x002e, 0x0000},
119 {0x002f, 0x0000},
120 {0x0030, 0x0000},
121 {0x0031, 0x5000},
122 {0x0032, 0x0000},
123 {0x0033, 0x0000},
124 {0x0034, 0x0000},
125 {0x0035, 0x0000},
126 {0x003a, 0x0000},
127 {0x003b, 0x0000},
128 {0x003c, 0x00ff},
129 {0x003d, 0x0000},
130 {0x003e, 0x00ff},
131 {0x003f, 0x0000},
132 {0x0040, 0x0000},
133 {0x0041, 0x00ff},
134 {0x0042, 0x0000},
135 {0x0043, 0x00ff},
136 {0x0044, 0x0c0c},
137 {0x0049, 0xc00b},
138 {0x004a, 0x0000},
139 {0x004b, 0x031f},
140 {0x004d, 0x0000},
141 {0x004e, 0x001f},
142 {0x004f, 0x0000},
143 {0x0050, 0x001f},
144 {0x0052, 0xf000},
145 {0x0061, 0x0000},
146 {0x0062, 0x0000},
147 {0x0063, 0x003e},
148 {0x0064, 0x0000},
149 {0x0065, 0x0000},
150 {0x0066, 0x003f},
151 {0x0067, 0x0000},
152 {0x006b, 0x0000},
153 {0x006d, 0xff00},
154 {0x006e, 0x2808},
155 {0x006f, 0x000a},
156 {0x0070, 0x8000},
157 {0x0071, 0x8000},
158 {0x0072, 0x8000},
159 {0x0073, 0x7000},
160 {0x0074, 0x7770},
161 {0x0075, 0x0002},
162 {0x0076, 0x0001},
163 {0x0078, 0x00f0},
164 {0x0079, 0x0000},
165 {0x007a, 0x0000},
166 {0x007b, 0x0000},
167 {0x007c, 0x0000},
168 {0x007d, 0x0123},
169 {0x007e, 0x4500},
170 {0x007f, 0x8003},
171 {0x0080, 0x0000},
172 {0x0081, 0x0000},
173 {0x0082, 0x0000},
174 {0x0083, 0x0000},
175 {0x0084, 0x0000},
176 {0x0085, 0x0000},
177 {0x0086, 0x0008},
178 {0x0087, 0x0000},
179 {0x0088, 0x0000},
180 {0x0089, 0x0000},
181 {0x008a, 0x0000},
182 {0x008b, 0x0000},
183 {0x008c, 0x0003},
184 {0x008e, 0x0060},
185 {0x008f, 0x1000},
186 {0x0091, 0x0c26},
187 {0x0092, 0x0073},
188 {0x0093, 0x0000},
189 {0x0094, 0x0080},
190 {0x0098, 0x0000},
191 {0x0099, 0x0000},
192 {0x009a, 0x0007},
193 {0x009f, 0x0000},
194 {0x00a0, 0x0000},
195 {0x00a1, 0x0002},
196 {0x00a2, 0x0001},
197 {0x00a3, 0x0002},
198 {0x00a4, 0x0001},
199 {0x00ae, 0x2040},
200 {0x00af, 0x0000},
201 {0x00b6, 0x0000},
202 {0x00b7, 0x0000},
203 {0x00b8, 0x0000},
204 {0x00b9, 0x0000},
205 {0x00ba, 0x0002},
206 {0x00bb, 0x0000},
207 {0x00be, 0x0000},
208 {0x00c0, 0x0000},
209 {0x00c1, 0x0aaa},
210 {0x00c2, 0xaa80},
211 {0x00c3, 0x0003},
212 {0x00c4, 0x0000},
213 {0x00d0, 0x0000},
214 {0x00d1, 0x2244},
215 {0x00d3, 0x3300},
216 {0x00d4, 0x2200},
217 {0x00d9, 0x0809},
218 {0x00da, 0x0000},
219 {0x00db, 0x0008},
220 {0x00dc, 0x00c0},
221 {0x00dd, 0x6724},
222 {0x00de, 0x3131},
223 {0x00df, 0x0008},
224 {0x00e0, 0x4000},
225 {0x00e1, 0x3131},
226 {0x00e2, 0x600c},
227 {0x00ea, 0xb320},
228 {0x00eb, 0x0000},
229 {0x00ec, 0xb300},
230 {0x00ed, 0x0000},
231 {0x00ee, 0xb320},
232 {0x00ef, 0x0000},
233 {0x00f0, 0x0201},
234 {0x00f1, 0x0ddd},
235 {0x00f2, 0x0ddd},
236 {0x00f6, 0x0000},
237 {0x00f7, 0x0000},
238 {0x00f8, 0x0000},
239 {0x00fa, 0x0000},
240 {0x00fb, 0x0000},
241 {0x00fc, 0x0000},
242 {0x00fd, 0x0000},
243 {0x00fe, 0x10ec},
244 {0x00ff, 0x6451},
245 {0x0100, 0xaaaa},
246 {0x0101, 0x000a},
247 {0x010a, 0xaaaa},
248 {0x010b, 0xa0a0},
249 {0x010c, 0xaeae},
250 {0x010d, 0xaaaa},
251 {0x010e, 0xaaaa},
252 {0x010f, 0xaaaa},
253 {0x0110, 0xe002},
254 {0x0111, 0xa402},
255 {0x0112, 0xaaaa},
256 {0x0113, 0x2000},
257 {0x0117, 0x0f00},
258 {0x0125, 0x0410},
259 {0x0132, 0x0000},
260 {0x0133, 0x0000},
261 {0x0137, 0x5540},
262 {0x0138, 0x3700},
263 {0x0139, 0x79a1},
264 {0x013a, 0x2020},
265 {0x013b, 0x2020},
266 {0x013c, 0x2005},
267 {0x013f, 0x0000},
268 {0x0145, 0x0002},
269 {0x0146, 0x0000},
270 {0x0147, 0x0000},
271 {0x0148, 0x0000},
272 {0x0150, 0x0000},
273 {0x0160, 0x4eff},
274 {0x0161, 0x0080},
275 {0x0162, 0x0200},
276 {0x0163, 0x0800},
277 {0x0164, 0x0000},
278 {0x0165, 0x0000},
279 {0x0166, 0x0000},
280 {0x0167, 0x000f},
281 {0x0170, 0x4e87},
282 {0x0171, 0x0080},
283 {0x0172, 0x0200},
284 {0x0173, 0x0800},
285 {0x0174, 0x00ff},
286 {0x0175, 0x0000},
287 {0x0190, 0x413d},
288 {0x0191, 0x4139},
289 {0x0192, 0x4135},
290 {0x0193, 0x413d},
291 {0x0194, 0x0000},
292 {0x0195, 0x0000},
293 {0x0196, 0x0000},
294 {0x0197, 0x0000},
295 {0x0198, 0x0000},
296 {0x0199, 0x0000},
297 {0x01a0, 0x1e64},
298 {0x01a1, 0x06a3},
299 {0x01a2, 0x0000},
300 {0x01a3, 0x0000},
301 {0x01a4, 0x0000},
302 {0x01a5, 0x0000},
303 {0x01a6, 0x0000},
304 {0x01a7, 0x8000},
305 {0x01a8, 0x0000},
306 {0x01a9, 0x0000},
307 {0x01aa, 0x0000},
308 {0x01ab, 0x0000},
309 {0x01b5, 0x0000},
310 {0x01b6, 0x01c3},
311 {0x01b7, 0x02a0},
312 {0x01b8, 0x03e9},
313 {0x01b9, 0x1389},
314 {0x01ba, 0xc351},
315 {0x01bb, 0x0009},
316 {0x01bc, 0x0018},
317 {0x01bd, 0x002a},
318 {0x01be, 0x004c},
319 {0x01bf, 0x0097},
320 {0x01c0, 0x433d},
321 {0x01c1, 0x0000},
322 {0x01c2, 0x0000},
323 {0x01c3, 0x0000},
324 {0x01c4, 0x0000},
325 {0x01c5, 0x0000},
326 {0x01c6, 0x0000},
327 {0x01c7, 0x0000},
328 {0x01c8, 0x40af},
329 {0x01c9, 0x0702},
330 {0x01ca, 0x0000},
331 {0x01cb, 0x0000},
332 {0x01cc, 0x5757},
333 {0x01cd, 0x5757},
334 {0x01ce, 0x5757},
335 {0x01cf, 0x5757},
336 {0x01d0, 0x5757},
337 {0x01d1, 0x5757},
338 {0x01d2, 0x5757},
339 {0x01d3, 0x5757},
340 {0x01d4, 0x5757},
341 {0x01d5, 0x5757},
342 {0x01d6, 0x003c},
343 {0x01da, 0x0000},
344 {0x01db, 0x0000},
345 {0x01dc, 0x0000},
346 {0x01de, 0x7c00},
347 {0x01df, 0x0320},
348 {0x01e0, 0x06a1},
349 {0x01e1, 0x0000},
350 {0x01e2, 0x0000},
351 {0x01e3, 0x0000},
352 {0x01e4, 0x0000},
353 {0x01e6, 0x0001},
354 {0x01e7, 0x0000},
355 {0x01e8, 0x0000},
356 {0x01ea, 0xbf3f},
357 {0x01eb, 0x0000},
358 {0x01ec, 0x0000},
359 {0x01ed, 0x0000},
360 {0x01ee, 0x0000},
361 {0x01ef, 0x0000},
362 {0x01f0, 0x0000},
363 {0x01f1, 0x0000},
364 {0x01f2, 0x0000},
365 {0x01f3, 0x0000},
366 {0x01f4, 0x0000},
367 {0x0200, 0x0000},
368 {0x0201, 0x0000},
369 {0x0202, 0x0000},
370 {0x0203, 0x0000},
371 {0x0204, 0x0000},
372 {0x0205, 0x0000},
373 {0x0206, 0x0000},
374 {0x0207, 0x0000},
375 {0x0208, 0x0000},
376 {0x0210, 0x60b1},
377 {0x0211, 0xa005},
378 {0x0212, 0x024c},
379 {0x0213, 0xf7ff},
380 {0x0214, 0x024c},
381 {0x0215, 0x0102},
382 {0x0216, 0x00a3},
383 {0x0217, 0x0048},
384 {0x0218, 0xa2c0},
385 {0x0219, 0x0400},
386 {0x021a, 0x00c8},
387 {0x021b, 0x00c0},
388 {0x02ff, 0x0110},
389 {0x0300, 0x001f},
390 {0x0301, 0x032c},
391 {0x0302, 0x5f21},
392 {0x0303, 0x4000},
393 {0x0304, 0x4000},
394 {0x0305, 0x06d5},
395 {0x0306, 0x8000},
396 {0x0307, 0x0700},
397 {0x0310, 0x4560},
398 {0x0311, 0xa4a8},
399 {0x0312, 0x7418},
400 {0x0313, 0x0000},
401 {0x0314, 0x0006},
402 {0x0315, 0xffff},
403 {0x0316, 0xc400},
404 {0x0317, 0x0000},
405 {0x0330, 0x00a6},
406 {0x0331, 0x04c3},
407 {0x0332, 0x27c8},
408 {0x0333, 0xbf50},
409 {0x0334, 0x0045},
410 {0x0335, 0x0007},
411 {0x0336, 0x7418},
412 {0x0337, 0x0501},
413 {0x0338, 0x0000},
414 {0x0339, 0x0010},
415 {0x033a, 0x1010},
416 {0x03c0, 0x7e00},
417 {0x03c1, 0x8000},
418 {0x03c2, 0x8000},
419 {0x03c3, 0x8000},
420 {0x03c4, 0x8000},
421 {0x03c5, 0x8000},
422 {0x03c6, 0x8000},
423 {0x03c7, 0x8000},
424 {0x03c8, 0x8000},
425 {0x03c9, 0x8000},
426 {0x03ca, 0x8000},
427 {0x03cb, 0x8000},
428 {0x03cc, 0x8000},
429 {0x03d0, 0x0000},
430 {0x03d1, 0x0000},
431 {0x03d2, 0x0000},
432 {0x03d3, 0x0000},
433 {0x03d4, 0x2000},
434 {0x03d5, 0x2000},
435 {0x03d6, 0x0000},
436 {0x03d7, 0x0000},
437 {0x03d8, 0x2000},
438 {0x03d9, 0x2000},
439 {0x03da, 0x2000},
440 {0x03db, 0x2000},
441 {0x03dc, 0x0000},
442 {0x03dd, 0x0000},
443 {0x03de, 0x0000},
444 {0x03df, 0x2000},
445 {0x03e0, 0x0000},
446 {0x03e1, 0x0000},
447 {0x03e2, 0x0000},
448 {0x03e3, 0x0000},
449 {0x03e4, 0x0000},
450 {0x03e5, 0x0000},
451 {0x03e6, 0x0000},
452 {0x03e7, 0x0000},
453 {0x03e8, 0x0000},
454 {0x03e9, 0x0000},
455 {0x03ea, 0x0000},
456 {0x03eb, 0x0000},
457 {0x03ec, 0x0000},
458 {0x03ed, 0x0000},
459 {0x03ee, 0x0000},
460 {0x03ef, 0x0000},
461 {0x03f0, 0x0800},
462 {0x03f1, 0x0800},
463 {0x03f2, 0x0800},
464 {0x03f3, 0x0800},
465};
466
467static bool rt5665_volatile_register(struct device *dev, unsigned int reg)
468{
469 switch (reg) {
470 case RT5665_RESET:
471 case RT5665_EJD_CTRL_2:
472 case RT5665_GPIO_STA:
473 case RT5665_INT_ST_1:
474 case RT5665_IL_CMD_1:
475 case RT5665_4BTN_IL_CMD_1:
476 case RT5665_PSV_IL_CMD_1:
477 case RT5665_AJD1_CTRL:
478 case RT5665_JD_CTRL_3:
479 case RT5665_STO_NG2_CTRL_1:
480 case RT5665_SAR_IL_CMD_4:
481 case RT5665_DEVICE_ID:
482 case RT5665_STO1_DAC_SIL_DET ... RT5665_STO2_DAC_SIL_DET:
483 case RT5665_MONO_AMP_CALIB_STA1 ... RT5665_MONO_AMP_CALIB_STA6:
484 case RT5665_HP_IMP_SENS_CTRL_12 ... RT5665_HP_IMP_SENS_CTRL_15:
485 case RT5665_HP_CALIB_STA_1 ... RT5665_HP_CALIB_STA_11:
486 return true;
487 default:
488 return false;
489 }
490}
491
492static bool rt5665_readable_register(struct device *dev, unsigned int reg)
493{
494 switch (reg) {
495 case RT5665_RESET:
496 case RT5665_VENDOR_ID:
497 case RT5665_VENDOR_ID_1:
498 case RT5665_DEVICE_ID:
499 case RT5665_LOUT:
500 case RT5665_HP_CTRL_1:
501 case RT5665_HP_CTRL_2:
502 case RT5665_MONO_OUT:
503 case RT5665_HPL_GAIN:
504 case RT5665_HPR_GAIN:
505 case RT5665_MONO_GAIN:
506 case RT5665_CAL_BST_CTRL:
507 case RT5665_CBJ_BST_CTRL:
508 case RT5665_IN1_IN2:
509 case RT5665_IN3_IN4:
510 case RT5665_INL1_INR1_VOL:
511 case RT5665_EJD_CTRL_1:
512 case RT5665_EJD_CTRL_2:
513 case RT5665_EJD_CTRL_3:
514 case RT5665_EJD_CTRL_4:
515 case RT5665_EJD_CTRL_5:
516 case RT5665_EJD_CTRL_6:
517 case RT5665_EJD_CTRL_7:
518 case RT5665_DAC2_CTRL:
519 case RT5665_DAC2_DIG_VOL:
520 case RT5665_DAC1_DIG_VOL:
521 case RT5665_DAC3_DIG_VOL:
522 case RT5665_DAC3_CTRL:
523 case RT5665_STO1_ADC_DIG_VOL:
524 case RT5665_MONO_ADC_DIG_VOL:
525 case RT5665_STO2_ADC_DIG_VOL:
526 case RT5665_STO1_ADC_BOOST:
527 case RT5665_MONO_ADC_BOOST:
528 case RT5665_STO2_ADC_BOOST:
529 case RT5665_HP_IMP_GAIN_1:
530 case RT5665_HP_IMP_GAIN_2:
531 case RT5665_STO1_ADC_MIXER:
532 case RT5665_MONO_ADC_MIXER:
533 case RT5665_STO2_ADC_MIXER:
534 case RT5665_AD_DA_MIXER:
535 case RT5665_STO1_DAC_MIXER:
536 case RT5665_MONO_DAC_MIXER:
537 case RT5665_STO2_DAC_MIXER:
538 case RT5665_A_DAC1_MUX:
539 case RT5665_A_DAC2_MUX:
540 case RT5665_DIG_INF2_DATA:
541 case RT5665_DIG_INF3_DATA:
542 case RT5665_PDM_OUT_CTRL:
543 case RT5665_PDM_DATA_CTRL_1:
544 case RT5665_PDM_DATA_CTRL_2:
545 case RT5665_PDM_DATA_CTRL_3:
546 case RT5665_PDM_DATA_CTRL_4:
547 case RT5665_REC1_GAIN:
548 case RT5665_REC1_L1_MIXER:
549 case RT5665_REC1_L2_MIXER:
550 case RT5665_REC1_R1_MIXER:
551 case RT5665_REC1_R2_MIXER:
552 case RT5665_REC2_GAIN:
553 case RT5665_REC2_L1_MIXER:
554 case RT5665_REC2_L2_MIXER:
555 case RT5665_REC2_R1_MIXER:
556 case RT5665_REC2_R2_MIXER:
557 case RT5665_CAL_REC:
558 case RT5665_ALC_BACK_GAIN:
559 case RT5665_MONOMIX_GAIN:
560 case RT5665_MONOMIX_IN_GAIN:
561 case RT5665_OUT_L_GAIN:
562 case RT5665_OUT_L_MIXER:
563 case RT5665_OUT_R_GAIN:
564 case RT5665_OUT_R_MIXER:
565 case RT5665_LOUT_MIXER:
566 case RT5665_PWR_DIG_1:
567 case RT5665_PWR_DIG_2:
568 case RT5665_PWR_ANLG_1:
569 case RT5665_PWR_ANLG_2:
570 case RT5665_PWR_ANLG_3:
571 case RT5665_PWR_MIXER:
572 case RT5665_PWR_VOL:
573 case RT5665_CLK_DET:
574 case RT5665_HPF_CTRL1:
575 case RT5665_DMIC_CTRL_1:
576 case RT5665_DMIC_CTRL_2:
577 case RT5665_I2S1_SDP:
578 case RT5665_I2S2_SDP:
579 case RT5665_I2S3_SDP:
580 case RT5665_ADDA_CLK_1:
581 case RT5665_ADDA_CLK_2:
582 case RT5665_I2S1_F_DIV_CTRL_1:
583 case RT5665_I2S1_F_DIV_CTRL_2:
584 case RT5665_TDM_CTRL_1:
585 case RT5665_TDM_CTRL_2:
586 case RT5665_TDM_CTRL_3:
587 case RT5665_TDM_CTRL_4:
588 case RT5665_TDM_CTRL_5:
589 case RT5665_TDM_CTRL_6:
590 case RT5665_TDM_CTRL_7:
591 case RT5665_TDM_CTRL_8:
592 case RT5665_GLB_CLK:
593 case RT5665_PLL_CTRL_1:
594 case RT5665_PLL_CTRL_2:
595 case RT5665_ASRC_1:
596 case RT5665_ASRC_2:
597 case RT5665_ASRC_3:
598 case RT5665_ASRC_4:
599 case RT5665_ASRC_5:
600 case RT5665_ASRC_6:
601 case RT5665_ASRC_7:
602 case RT5665_ASRC_8:
603 case RT5665_ASRC_9:
604 case RT5665_ASRC_10:
605 case RT5665_DEPOP_1:
606 case RT5665_DEPOP_2:
607 case RT5665_HP_CHARGE_PUMP_1:
608 case RT5665_HP_CHARGE_PUMP_2:
609 case RT5665_MICBIAS_1:
610 case RT5665_MICBIAS_2:
611 case RT5665_ASRC_12:
612 case RT5665_ASRC_13:
613 case RT5665_ASRC_14:
614 case RT5665_RC_CLK_CTRL:
615 case RT5665_I2S_M_CLK_CTRL_1:
616 case RT5665_I2S2_F_DIV_CTRL_1:
617 case RT5665_I2S2_F_DIV_CTRL_2:
618 case RT5665_I2S3_F_DIV_CTRL_1:
619 case RT5665_I2S3_F_DIV_CTRL_2:
620 case RT5665_EQ_CTRL_1:
621 case RT5665_EQ_CTRL_2:
622 case RT5665_IRQ_CTRL_1:
623 case RT5665_IRQ_CTRL_2:
624 case RT5665_IRQ_CTRL_3:
625 case RT5665_IRQ_CTRL_4:
626 case RT5665_IRQ_CTRL_5:
627 case RT5665_IRQ_CTRL_6:
628 case RT5665_INT_ST_1:
629 case RT5665_GPIO_CTRL_1:
630 case RT5665_GPIO_CTRL_2:
631 case RT5665_GPIO_CTRL_3:
632 case RT5665_GPIO_CTRL_4:
633 case RT5665_GPIO_STA:
634 case RT5665_HP_AMP_DET_CTRL_1:
635 case RT5665_HP_AMP_DET_CTRL_2:
636 case RT5665_MID_HP_AMP_DET:
637 case RT5665_LOW_HP_AMP_DET:
638 case RT5665_SV_ZCD_1:
639 case RT5665_SV_ZCD_2:
640 case RT5665_IL_CMD_1:
641 case RT5665_IL_CMD_2:
642 case RT5665_IL_CMD_3:
643 case RT5665_IL_CMD_4:
644 case RT5665_4BTN_IL_CMD_1:
645 case RT5665_4BTN_IL_CMD_2:
646 case RT5665_4BTN_IL_CMD_3:
647 case RT5665_PSV_IL_CMD_1:
648 case RT5665_ADC_STO1_HP_CTRL_1:
649 case RT5665_ADC_STO1_HP_CTRL_2:
650 case RT5665_ADC_MONO_HP_CTRL_1:
651 case RT5665_ADC_MONO_HP_CTRL_2:
652 case RT5665_ADC_STO2_HP_CTRL_1:
653 case RT5665_ADC_STO2_HP_CTRL_2:
654 case RT5665_AJD1_CTRL:
655 case RT5665_JD1_THD:
656 case RT5665_JD2_THD:
657 case RT5665_JD_CTRL_1:
658 case RT5665_JD_CTRL_2:
659 case RT5665_JD_CTRL_3:
660 case RT5665_DIG_MISC:
661 case RT5665_DUMMY_2:
662 case RT5665_DUMMY_3:
663 case RT5665_DAC_ADC_DIG_VOL1:
664 case RT5665_DAC_ADC_DIG_VOL2:
665 case RT5665_BIAS_CUR_CTRL_1:
666 case RT5665_BIAS_CUR_CTRL_2:
667 case RT5665_BIAS_CUR_CTRL_3:
668 case RT5665_BIAS_CUR_CTRL_4:
669 case RT5665_BIAS_CUR_CTRL_5:
670 case RT5665_BIAS_CUR_CTRL_6:
671 case RT5665_BIAS_CUR_CTRL_7:
672 case RT5665_BIAS_CUR_CTRL_8:
673 case RT5665_BIAS_CUR_CTRL_9:
674 case RT5665_BIAS_CUR_CTRL_10:
675 case RT5665_VREF_REC_OP_FB_CAP_CTRL:
676 case RT5665_CHARGE_PUMP_1:
677 case RT5665_DIG_IN_CTRL_1:
678 case RT5665_DIG_IN_CTRL_2:
679 case RT5665_PAD_DRIVING_CTRL:
680 case RT5665_SOFT_RAMP_DEPOP:
681 case RT5665_PLL:
682 case RT5665_CHOP_DAC:
683 case RT5665_CHOP_ADC:
684 case RT5665_CALIB_ADC_CTRL:
685 case RT5665_VOL_TEST:
686 case RT5665_TEST_MODE_CTRL_1:
687 case RT5665_TEST_MODE_CTRL_2:
688 case RT5665_TEST_MODE_CTRL_3:
689 case RT5665_TEST_MODE_CTRL_4:
690 case RT5665_BASSBACK_CTRL:
691 case RT5665_STO_NG2_CTRL_1:
692 case RT5665_STO_NG2_CTRL_2:
693 case RT5665_STO_NG2_CTRL_3:
694 case RT5665_STO_NG2_CTRL_4:
695 case RT5665_STO_NG2_CTRL_5:
696 case RT5665_STO_NG2_CTRL_6:
697 case RT5665_STO_NG2_CTRL_7:
698 case RT5665_STO_NG2_CTRL_8:
699 case RT5665_MONO_NG2_CTRL_1:
700 case RT5665_MONO_NG2_CTRL_2:
701 case RT5665_MONO_NG2_CTRL_3:
702 case RT5665_MONO_NG2_CTRL_4:
703 case RT5665_MONO_NG2_CTRL_5:
704 case RT5665_MONO_NG2_CTRL_6:
705 case RT5665_STO1_DAC_SIL_DET:
706 case RT5665_MONOL_DAC_SIL_DET:
707 case RT5665_MONOR_DAC_SIL_DET:
708 case RT5665_STO2_DAC_SIL_DET:
709 case RT5665_SIL_PSV_CTRL1:
710 case RT5665_SIL_PSV_CTRL2:
711 case RT5665_SIL_PSV_CTRL3:
712 case RT5665_SIL_PSV_CTRL4:
713 case RT5665_SIL_PSV_CTRL5:
714 case RT5665_SIL_PSV_CTRL6:
715 case RT5665_MONO_AMP_CALIB_CTRL_1:
716 case RT5665_MONO_AMP_CALIB_CTRL_2:
717 case RT5665_MONO_AMP_CALIB_CTRL_3:
718 case RT5665_MONO_AMP_CALIB_CTRL_4:
719 case RT5665_MONO_AMP_CALIB_CTRL_5:
720 case RT5665_MONO_AMP_CALIB_CTRL_6:
721 case RT5665_MONO_AMP_CALIB_CTRL_7:
722 case RT5665_MONO_AMP_CALIB_STA1:
723 case RT5665_MONO_AMP_CALIB_STA2:
724 case RT5665_MONO_AMP_CALIB_STA3:
725 case RT5665_MONO_AMP_CALIB_STA4:
726 case RT5665_MONO_AMP_CALIB_STA6:
727 case RT5665_HP_IMP_SENS_CTRL_01:
728 case RT5665_HP_IMP_SENS_CTRL_02:
729 case RT5665_HP_IMP_SENS_CTRL_03:
730 case RT5665_HP_IMP_SENS_CTRL_04:
731 case RT5665_HP_IMP_SENS_CTRL_05:
732 case RT5665_HP_IMP_SENS_CTRL_06:
733 case RT5665_HP_IMP_SENS_CTRL_07:
734 case RT5665_HP_IMP_SENS_CTRL_08:
735 case RT5665_HP_IMP_SENS_CTRL_09:
736 case RT5665_HP_IMP_SENS_CTRL_10:
737 case RT5665_HP_IMP_SENS_CTRL_11:
738 case RT5665_HP_IMP_SENS_CTRL_12:
739 case RT5665_HP_IMP_SENS_CTRL_13:
740 case RT5665_HP_IMP_SENS_CTRL_14:
741 case RT5665_HP_IMP_SENS_CTRL_15:
742 case RT5665_HP_IMP_SENS_CTRL_16:
743 case RT5665_HP_IMP_SENS_CTRL_17:
744 case RT5665_HP_IMP_SENS_CTRL_18:
745 case RT5665_HP_IMP_SENS_CTRL_19:
746 case RT5665_HP_IMP_SENS_CTRL_20:
747 case RT5665_HP_IMP_SENS_CTRL_21:
748 case RT5665_HP_IMP_SENS_CTRL_22:
749 case RT5665_HP_IMP_SENS_CTRL_23:
750 case RT5665_HP_IMP_SENS_CTRL_24:
751 case RT5665_HP_IMP_SENS_CTRL_25:
752 case RT5665_HP_IMP_SENS_CTRL_26:
753 case RT5665_HP_IMP_SENS_CTRL_27:
754 case RT5665_HP_IMP_SENS_CTRL_28:
755 case RT5665_HP_IMP_SENS_CTRL_29:
756 case RT5665_HP_IMP_SENS_CTRL_30:
757 case RT5665_HP_IMP_SENS_CTRL_31:
758 case RT5665_HP_IMP_SENS_CTRL_32:
759 case RT5665_HP_IMP_SENS_CTRL_33:
760 case RT5665_HP_IMP_SENS_CTRL_34:
761 case RT5665_HP_LOGIC_CTRL_1:
762 case RT5665_HP_LOGIC_CTRL_2:
763 case RT5665_HP_LOGIC_CTRL_3:
764 case RT5665_HP_CALIB_CTRL_1:
765 case RT5665_HP_CALIB_CTRL_2:
766 case RT5665_HP_CALIB_CTRL_3:
767 case RT5665_HP_CALIB_CTRL_4:
768 case RT5665_HP_CALIB_CTRL_5:
769 case RT5665_HP_CALIB_CTRL_6:
770 case RT5665_HP_CALIB_CTRL_7:
771 case RT5665_HP_CALIB_CTRL_9:
772 case RT5665_HP_CALIB_CTRL_10:
773 case RT5665_HP_CALIB_CTRL_11:
774 case RT5665_HP_CALIB_STA_1:
775 case RT5665_HP_CALIB_STA_2:
776 case RT5665_HP_CALIB_STA_3:
777 case RT5665_HP_CALIB_STA_4:
778 case RT5665_HP_CALIB_STA_5:
779 case RT5665_HP_CALIB_STA_6:
780 case RT5665_HP_CALIB_STA_7:
781 case RT5665_HP_CALIB_STA_8:
782 case RT5665_HP_CALIB_STA_9:
783 case RT5665_HP_CALIB_STA_10:
784 case RT5665_HP_CALIB_STA_11:
785 case RT5665_PGM_TAB_CTRL1:
786 case RT5665_PGM_TAB_CTRL2:
787 case RT5665_PGM_TAB_CTRL3:
788 case RT5665_PGM_TAB_CTRL4:
789 case RT5665_PGM_TAB_CTRL5:
790 case RT5665_PGM_TAB_CTRL6:
791 case RT5665_PGM_TAB_CTRL7:
792 case RT5665_PGM_TAB_CTRL8:
793 case RT5665_PGM_TAB_CTRL9:
794 case RT5665_SAR_IL_CMD_1:
795 case RT5665_SAR_IL_CMD_2:
796 case RT5665_SAR_IL_CMD_3:
797 case RT5665_SAR_IL_CMD_4:
798 case RT5665_SAR_IL_CMD_5:
799 case RT5665_SAR_IL_CMD_6:
800 case RT5665_SAR_IL_CMD_7:
801 case RT5665_SAR_IL_CMD_8:
802 case RT5665_SAR_IL_CMD_9:
803 case RT5665_SAR_IL_CMD_10:
804 case RT5665_SAR_IL_CMD_11:
805 case RT5665_SAR_IL_CMD_12:
806 case RT5665_DRC1_CTRL_0:
807 case RT5665_DRC1_CTRL_1:
808 case RT5665_DRC1_CTRL_2:
809 case RT5665_DRC1_CTRL_3:
810 case RT5665_DRC1_CTRL_4:
811 case RT5665_DRC1_CTRL_5:
812 case RT5665_DRC1_CTRL_6:
813 case RT5665_DRC1_HARD_LMT_CTRL_1:
814 case RT5665_DRC1_HARD_LMT_CTRL_2:
815 case RT5665_DRC1_PRIV_1:
816 case RT5665_DRC1_PRIV_2:
817 case RT5665_DRC1_PRIV_3:
818 case RT5665_DRC1_PRIV_4:
819 case RT5665_DRC1_PRIV_5:
820 case RT5665_DRC1_PRIV_6:
821 case RT5665_DRC1_PRIV_7:
822 case RT5665_DRC1_PRIV_8:
823 case RT5665_ALC_PGA_CTRL_1:
824 case RT5665_ALC_PGA_CTRL_2:
825 case RT5665_ALC_PGA_CTRL_3:
826 case RT5665_ALC_PGA_CTRL_4:
827 case RT5665_ALC_PGA_CTRL_5:
828 case RT5665_ALC_PGA_CTRL_6:
829 case RT5665_ALC_PGA_CTRL_7:
830 case RT5665_ALC_PGA_CTRL_8:
831 case RT5665_ALC_PGA_STA_1:
832 case RT5665_ALC_PGA_STA_2:
833 case RT5665_ALC_PGA_STA_3:
834 case RT5665_EQ_AUTO_RCV_CTRL1:
835 case RT5665_EQ_AUTO_RCV_CTRL2:
836 case RT5665_EQ_AUTO_RCV_CTRL3:
837 case RT5665_EQ_AUTO_RCV_CTRL4:
838 case RT5665_EQ_AUTO_RCV_CTRL5:
839 case RT5665_EQ_AUTO_RCV_CTRL6:
840 case RT5665_EQ_AUTO_RCV_CTRL7:
841 case RT5665_EQ_AUTO_RCV_CTRL8:
842 case RT5665_EQ_AUTO_RCV_CTRL9:
843 case RT5665_EQ_AUTO_RCV_CTRL10:
844 case RT5665_EQ_AUTO_RCV_CTRL11:
845 case RT5665_EQ_AUTO_RCV_CTRL12:
846 case RT5665_EQ_AUTO_RCV_CTRL13:
847 case RT5665_ADC_L_EQ_LPF1_A1:
848 case RT5665_R_EQ_LPF1_A1:
849 case RT5665_L_EQ_LPF1_H0:
850 case RT5665_R_EQ_LPF1_H0:
851 case RT5665_L_EQ_BPF1_A1:
852 case RT5665_R_EQ_BPF1_A1:
853 case RT5665_L_EQ_BPF1_A2:
854 case RT5665_R_EQ_BPF1_A2:
855 case RT5665_L_EQ_BPF1_H0:
856 case RT5665_R_EQ_BPF1_H0:
857 case RT5665_L_EQ_BPF2_A1:
858 case RT5665_R_EQ_BPF2_A1:
859 case RT5665_L_EQ_BPF2_A2:
860 case RT5665_R_EQ_BPF2_A2:
861 case RT5665_L_EQ_BPF2_H0:
862 case RT5665_R_EQ_BPF2_H0:
863 case RT5665_L_EQ_BPF3_A1:
864 case RT5665_R_EQ_BPF3_A1:
865 case RT5665_L_EQ_BPF3_A2:
866 case RT5665_R_EQ_BPF3_A2:
867 case RT5665_L_EQ_BPF3_H0:
868 case RT5665_R_EQ_BPF3_H0:
869 case RT5665_L_EQ_BPF4_A1:
870 case RT5665_R_EQ_BPF4_A1:
871 case RT5665_L_EQ_BPF4_A2:
872 case RT5665_R_EQ_BPF4_A2:
873 case RT5665_L_EQ_BPF4_H0:
874 case RT5665_R_EQ_BPF4_H0:
875 case RT5665_L_EQ_HPF1_A1:
876 case RT5665_R_EQ_HPF1_A1:
877 case RT5665_L_EQ_HPF1_H0:
878 case RT5665_R_EQ_HPF1_H0:
879 case RT5665_L_EQ_PRE_VOL:
880 case RT5665_R_EQ_PRE_VOL:
881 case RT5665_L_EQ_POST_VOL:
882 case RT5665_R_EQ_POST_VOL:
883 case RT5665_SCAN_MODE_CTRL:
884 case RT5665_I2C_MODE:
885 return true;
886 default:
887 return false;
888 }
889}
890
891static const DECLARE_TLV_DB_SCALE(hp_vol_tlv, -2250, 150, 0);
892static const DECLARE_TLV_DB_SCALE(mono_vol_tlv, -1400, 150, 0);
893static const DECLARE_TLV_DB_SCALE(out_vol_tlv, -4650, 150, 0);
894static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -65625, 375, 0);
895static const DECLARE_TLV_DB_SCALE(in_vol_tlv, -3450, 150, 0);
896static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -17625, 375, 0);
897static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
898static const DECLARE_TLV_DB_SCALE(in_bst_tlv, -1200, 75, 0);
899
900
901static const DECLARE_TLV_DB_RANGE(bst_tlv,
902 0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
903 1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
904 2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
905 3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
906 6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
907 7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
908 8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
909);
910
911
912static const char * const rt5665_data_select[] = {
913 "L/R", "R/L", "L/L", "R/R"
914};
915
916static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_01_adc_enum,
917 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT01_SFT, rt5665_data_select);
918
919static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_23_adc_enum,
920 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT23_SFT, rt5665_data_select);
921
922static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_45_adc_enum,
923 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT45_SFT, rt5665_data_select);
924
925static SOC_ENUM_SINGLE_DECL(rt5665_if1_1_67_adc_enum,
926 RT5665_TDM_CTRL_2, RT5665_I2S1_1_DS_ADC_SLOT67_SFT, rt5665_data_select);
927
928static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_01_adc_enum,
929 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT01_SFT, rt5665_data_select);
930
931static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_23_adc_enum,
932 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT23_SFT, rt5665_data_select);
933
934static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_45_adc_enum,
935 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT45_SFT, rt5665_data_select);
936
937static SOC_ENUM_SINGLE_DECL(rt5665_if1_2_67_adc_enum,
938 RT5665_TDM_CTRL_2, RT5665_I2S1_2_DS_ADC_SLOT67_SFT, rt5665_data_select);
939
940static SOC_ENUM_SINGLE_DECL(rt5665_if2_1_dac_enum,
941 RT5665_DIG_INF2_DATA, RT5665_IF2_1_DAC_SEL_SFT, rt5665_data_select);
942
943static SOC_ENUM_SINGLE_DECL(rt5665_if2_1_adc_enum,
944 RT5665_DIG_INF2_DATA, RT5665_IF2_1_ADC_SEL_SFT, rt5665_data_select);
945
946static SOC_ENUM_SINGLE_DECL(rt5665_if2_2_dac_enum,
947 RT5665_DIG_INF2_DATA, RT5665_IF2_2_DAC_SEL_SFT, rt5665_data_select);
948
949static SOC_ENUM_SINGLE_DECL(rt5665_if2_2_adc_enum,
950 RT5665_DIG_INF2_DATA, RT5665_IF2_2_ADC_SEL_SFT, rt5665_data_select);
951
952static SOC_ENUM_SINGLE_DECL(rt5665_if3_dac_enum,
953 RT5665_DIG_INF3_DATA, RT5665_IF3_DAC_SEL_SFT, rt5665_data_select);
954
955static SOC_ENUM_SINGLE_DECL(rt5665_if3_adc_enum,
956 RT5665_DIG_INF3_DATA, RT5665_IF3_ADC_SEL_SFT, rt5665_data_select);
957
958static const struct snd_kcontrol_new rt5665_if1_1_01_adc_swap_mux =
959 SOC_DAPM_ENUM("IF1_1 01 ADC Swap Mux", rt5665_if1_1_01_adc_enum);
960
961static const struct snd_kcontrol_new rt5665_if1_1_23_adc_swap_mux =
962 SOC_DAPM_ENUM("IF1_1 23 ADC Swap Mux", rt5665_if1_1_23_adc_enum);
963
964static const struct snd_kcontrol_new rt5665_if1_1_45_adc_swap_mux =
965 SOC_DAPM_ENUM("IF1_1 45 ADC Swap Mux", rt5665_if1_1_45_adc_enum);
966
967static const struct snd_kcontrol_new rt5665_if1_1_67_adc_swap_mux =
968 SOC_DAPM_ENUM("IF1_1 67 ADC Swap Mux", rt5665_if1_1_67_adc_enum);
969
970static const struct snd_kcontrol_new rt5665_if1_2_01_adc_swap_mux =
971 SOC_DAPM_ENUM("IF1_2 01 ADC Swap Mux", rt5665_if1_2_01_adc_enum);
972
973static const struct snd_kcontrol_new rt5665_if1_2_23_adc_swap_mux =
974 SOC_DAPM_ENUM("IF1_2 23 ADC1 Swap Mux", rt5665_if1_2_23_adc_enum);
975
976static const struct snd_kcontrol_new rt5665_if1_2_45_adc_swap_mux =
977 SOC_DAPM_ENUM("IF1_2 45 ADC1 Swap Mux", rt5665_if1_2_45_adc_enum);
978
979static const struct snd_kcontrol_new rt5665_if1_2_67_adc_swap_mux =
980 SOC_DAPM_ENUM("IF1_2 67 ADC1 Swap Mux", rt5665_if1_2_67_adc_enum);
981
982static const struct snd_kcontrol_new rt5665_if2_1_dac_swap_mux =
983 SOC_DAPM_ENUM("IF2_1 DAC Swap Source", rt5665_if2_1_dac_enum);
984
985static const struct snd_kcontrol_new rt5665_if2_1_adc_swap_mux =
986 SOC_DAPM_ENUM("IF2_1 ADC Swap Source", rt5665_if2_1_adc_enum);
987
988static const struct snd_kcontrol_new rt5665_if2_2_dac_swap_mux =
989 SOC_DAPM_ENUM("IF2_2 DAC Swap Source", rt5665_if2_2_dac_enum);
990
991static const struct snd_kcontrol_new rt5665_if2_2_adc_swap_mux =
992 SOC_DAPM_ENUM("IF2_2 ADC Swap Source", rt5665_if2_2_adc_enum);
993
994static const struct snd_kcontrol_new rt5665_if3_dac_swap_mux =
995 SOC_DAPM_ENUM("IF3 DAC Swap Source", rt5665_if3_dac_enum);
996
997static const struct snd_kcontrol_new rt5665_if3_adc_swap_mux =
998 SOC_DAPM_ENUM("IF3 ADC Swap Source", rt5665_if3_adc_enum);
999
1000static int rt5665_hp_vol_put(struct snd_kcontrol *kcontrol,
1001 struct snd_ctl_elem_value *ucontrol)
1002{
1003 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1004 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1005
1006 if (snd_soc_read(codec, RT5665_STO_NG2_CTRL_1) & RT5665_NG2_EN) {
1007 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
1008 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
1009 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
1010 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
1011 }
1012
1013 return ret;
1014}
1015
1016static int rt5665_mono_vol_put(struct snd_kcontrol *kcontrol,
1017 struct snd_ctl_elem_value *ucontrol)
1018{
1019 struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
1020 int ret = snd_soc_put_volsw(kcontrol, ucontrol);
1021
1022 if (snd_soc_read(codec, RT5665_MONO_NG2_CTRL_1) & RT5665_NG2_EN) {
1023 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
1024 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
1025 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
1026 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
1027 }
1028
1029 return ret;
1030}
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046int rt5665_sel_asrc_clk_src(struct snd_soc_codec *codec,
1047 unsigned int filter_mask, unsigned int clk_src)
1048{
1049 unsigned int asrc2_mask = 0;
1050 unsigned int asrc2_value = 0;
1051 unsigned int asrc3_mask = 0;
1052 unsigned int asrc3_value = 0;
1053
1054 switch (clk_src) {
1055 case RT5665_CLK_SEL_SYS:
1056 case RT5665_CLK_SEL_I2S1_ASRC:
1057 case RT5665_CLK_SEL_I2S2_ASRC:
1058 case RT5665_CLK_SEL_I2S3_ASRC:
1059 case RT5665_CLK_SEL_SYS2:
1060 case RT5665_CLK_SEL_SYS3:
1061 case RT5665_CLK_SEL_SYS4:
1062 break;
1063
1064 default:
1065 return -EINVAL;
1066 }
1067
1068 if (filter_mask & RT5665_DA_STEREO1_FILTER) {
1069 asrc2_mask |= RT5665_DA_STO1_CLK_SEL_MASK;
1070 asrc2_value = (asrc2_value & ~RT5665_DA_STO1_CLK_SEL_MASK)
1071 | (clk_src << RT5665_DA_STO1_CLK_SEL_SFT);
1072 }
1073
1074 if (filter_mask & RT5665_DA_STEREO2_FILTER) {
1075 asrc2_mask |= RT5665_DA_STO2_CLK_SEL_MASK;
1076 asrc2_value = (asrc2_value & ~RT5665_DA_STO2_CLK_SEL_MASK)
1077 | (clk_src << RT5665_DA_STO2_CLK_SEL_SFT);
1078 }
1079
1080 if (filter_mask & RT5665_DA_MONO_L_FILTER) {
1081 asrc2_mask |= RT5665_DA_MONOL_CLK_SEL_MASK;
1082 asrc2_value = (asrc2_value & ~RT5665_DA_MONOL_CLK_SEL_MASK)
1083 | (clk_src << RT5665_DA_MONOL_CLK_SEL_SFT);
1084 }
1085
1086 if (filter_mask & RT5665_DA_MONO_R_FILTER) {
1087 asrc2_mask |= RT5665_DA_MONOR_CLK_SEL_MASK;
1088 asrc2_value = (asrc2_value & ~RT5665_DA_MONOR_CLK_SEL_MASK)
1089 | (clk_src << RT5665_DA_MONOR_CLK_SEL_SFT);
1090 }
1091
1092 if (filter_mask & RT5665_AD_STEREO1_FILTER) {
1093 asrc3_mask |= RT5665_AD_STO1_CLK_SEL_MASK;
1094 asrc3_value = (asrc2_value & ~RT5665_AD_STO1_CLK_SEL_MASK)
1095 | (clk_src << RT5665_AD_STO1_CLK_SEL_SFT);
1096 }
1097
1098 if (filter_mask & RT5665_AD_STEREO2_FILTER) {
1099 asrc3_mask |= RT5665_AD_STO2_CLK_SEL_MASK;
1100 asrc3_value = (asrc2_value & ~RT5665_AD_STO2_CLK_SEL_MASK)
1101 | (clk_src << RT5665_AD_STO2_CLK_SEL_SFT);
1102 }
1103
1104 if (filter_mask & RT5665_AD_MONO_L_FILTER) {
1105 asrc3_mask |= RT5665_AD_MONOL_CLK_SEL_MASK;
1106 asrc3_value = (asrc3_value & ~RT5665_AD_MONOL_CLK_SEL_MASK)
1107 | (clk_src << RT5665_AD_MONOL_CLK_SEL_SFT);
1108 }
1109
1110 if (filter_mask & RT5665_AD_MONO_R_FILTER) {
1111 asrc3_mask |= RT5665_AD_MONOR_CLK_SEL_MASK;
1112 asrc3_value = (asrc3_value & ~RT5665_AD_MONOR_CLK_SEL_MASK)
1113 | (clk_src << RT5665_AD_MONOR_CLK_SEL_SFT);
1114 }
1115
1116 if (asrc2_mask)
1117 snd_soc_update_bits(codec, RT5665_ASRC_2,
1118 asrc2_mask, asrc2_value);
1119
1120 if (asrc3_mask)
1121 snd_soc_update_bits(codec, RT5665_ASRC_3,
1122 asrc3_mask, asrc3_value);
1123
1124 return 0;
1125}
1126EXPORT_SYMBOL_GPL(rt5665_sel_asrc_clk_src);
1127
1128static int rt5665_button_detect(struct snd_soc_codec *codec)
1129{
1130 int btn_type, val;
1131
1132 val = snd_soc_read(codec, RT5665_4BTN_IL_CMD_1);
1133 btn_type = val & 0xfff0;
1134 snd_soc_write(codec, RT5665_4BTN_IL_CMD_1, val);
1135
1136 return btn_type;
1137}
1138
1139static void rt5665_enable_push_button_irq(struct snd_soc_codec *codec,
1140 bool enable)
1141{
1142 if (enable) {
1143 snd_soc_write(codec, RT5665_4BTN_IL_CMD_1, 0x0003);
1144 snd_soc_update_bits(codec, RT5665_SAR_IL_CMD_9, 0x1, 0x1);
1145 snd_soc_write(codec, RT5665_IL_CMD_1, 0x0048);
1146 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1147 RT5665_4BTN_IL_MASK | RT5665_4BTN_IL_RST_MASK,
1148 RT5665_4BTN_IL_EN | RT5665_4BTN_IL_NOR);
1149 snd_soc_update_bits(codec, RT5665_IRQ_CTRL_3,
1150 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_EN);
1151 } else {
1152 snd_soc_update_bits(codec, RT5665_IRQ_CTRL_3,
1153 RT5665_IL_IRQ_MASK, RT5665_IL_IRQ_DIS);
1154 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1155 RT5665_4BTN_IL_MASK, RT5665_4BTN_IL_DIS);
1156 snd_soc_update_bits(codec, RT5665_4BTN_IL_CMD_2,
1157 RT5665_4BTN_IL_RST_MASK, RT5665_4BTN_IL_RST);
1158 }
1159}
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170static int rt5665_headset_detect(struct snd_soc_codec *codec, int jack_insert)
1171{
1172 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1173 struct snd_soc_dapm_context *dapm = snd_soc_codec_get_dapm(codec);
1174 unsigned int sar_hs_type, val;
1175
1176 if (jack_insert) {
1177 snd_soc_dapm_force_enable_pin(dapm, "MICBIAS1");
1178 snd_soc_dapm_sync(dapm);
1179
1180 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100,
1181 0x100);
1182
1183 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1184 if (val & 0x4) {
1185 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
1186 0x100, 0);
1187
1188 regmap_read(rt5665->regmap, RT5665_GPIO_STA, &val);
1189 while (val & 0x4) {
1190 usleep_range(10000, 15000);
1191 regmap_read(rt5665->regmap, RT5665_GPIO_STA,
1192 &val);
1193 }
1194 }
1195
1196 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
1197 0x1a0, 0x120);
1198 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_3, 0x3424);
1199 regmap_write(rt5665->regmap, RT5665_IL_CMD_1, 0x0048);
1200 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0xa291);
1201
1202 usleep_range(10000, 15000);
1203
1204 rt5665->sar_adc_value = snd_soc_read(rt5665->codec,
1205 RT5665_SAR_IL_CMD_4) & 0x7ff;
1206
1207 sar_hs_type = rt5665->pdata.sar_hs_type ?
1208 rt5665->pdata.sar_hs_type : 729;
1209
1210 if (rt5665->sar_adc_value > sar_hs_type) {
1211 rt5665->jack_type = SND_JACK_HEADSET;
1212 rt5665_enable_push_button_irq(codec, true);
1213 } else {
1214 rt5665->jack_type = SND_JACK_HEADPHONE;
1215 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1,
1216 0x2291);
1217 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2,
1218 0x100, 0);
1219 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1220 snd_soc_dapm_sync(dapm);
1221 }
1222 } else {
1223 regmap_write(rt5665->regmap, RT5665_SAR_IL_CMD_1, 0x2291);
1224 regmap_update_bits(rt5665->regmap, RT5665_MICBIAS_2, 0x100, 0);
1225 snd_soc_dapm_disable_pin(dapm, "MICBIAS1");
1226 snd_soc_dapm_sync(dapm);
1227 if (rt5665->jack_type == SND_JACK_HEADSET)
1228 rt5665_enable_push_button_irq(codec, false);
1229 rt5665->jack_type = 0;
1230 }
1231
1232 dev_dbg(codec->dev, "jack_type = %d\n", rt5665->jack_type);
1233 return rt5665->jack_type;
1234}
1235
1236static irqreturn_t rt5665_irq(int irq, void *data)
1237{
1238 struct rt5665_priv *rt5665 = data;
1239
1240 mod_delayed_work(system_power_efficient_wq,
1241 &rt5665->jack_detect_work, msecs_to_jiffies(250));
1242
1243 return IRQ_HANDLED;
1244}
1245
1246static void rt5665_jd_check_handler(struct work_struct *work)
1247{
1248 struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
1249 jd_check_work.work);
1250
1251 if (snd_soc_read(rt5665->codec, RT5665_AJD1_CTRL) & 0x0010) {
1252
1253 rt5665->jack_type = rt5665_headset_detect(rt5665->codec, 0);
1254
1255 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1256 SND_JACK_HEADSET |
1257 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1258 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1259 } else {
1260 schedule_delayed_work(&rt5665->jd_check_work, 500);
1261 }
1262}
1263
1264static int rt5665_set_jack_detect(struct snd_soc_codec *codec,
1265 struct snd_soc_jack *hs_jack, void *data)
1266{
1267 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1268
1269 switch (rt5665->pdata.jd_src) {
1270 case RT5665_JD1:
1271 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
1272 RT5665_GP1_PIN_MASK, RT5665_GP1_PIN_IRQ);
1273 regmap_update_bits(rt5665->regmap, RT5665_RC_CLK_CTRL,
1274 0xc000, 0xc000);
1275 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_2,
1276 RT5665_PWR_JD1, RT5665_PWR_JD1);
1277 regmap_update_bits(rt5665->regmap, RT5665_IRQ_CTRL_1, 0x8, 0x8);
1278 break;
1279
1280 case RT5665_JD_NULL:
1281 break;
1282
1283 default:
1284 dev_warn(codec->dev, "Wrong JD source\n");
1285 break;
1286 }
1287
1288 rt5665->hs_jack = hs_jack;
1289
1290 return 0;
1291}
1292
1293static void rt5665_jack_detect_handler(struct work_struct *work)
1294{
1295 struct rt5665_priv *rt5665 =
1296 container_of(work, struct rt5665_priv, jack_detect_work.work);
1297 int val, btn_type;
1298
1299 while (!rt5665->codec) {
1300 pr_debug("%s codec = null\n", __func__);
1301 usleep_range(10000, 15000);
1302 }
1303
1304 while (!rt5665->codec->component.card->instantiated) {
1305 pr_debug("%s\n", __func__);
1306 usleep_range(10000, 15000);
1307 }
1308
1309 while (!rt5665->calibration_done) {
1310 pr_debug("%s calibration not ready\n", __func__);
1311 usleep_range(10000, 15000);
1312 }
1313
1314 mutex_lock(&rt5665->calibrate_mutex);
1315
1316 val = snd_soc_read(rt5665->codec, RT5665_AJD1_CTRL) & 0x0010;
1317 if (!val) {
1318
1319 if (rt5665->jack_type == 0) {
1320
1321 rt5665->jack_type =
1322 rt5665_headset_detect(rt5665->codec, 1);
1323 } else {
1324
1325 rt5665->jack_type = SND_JACK_HEADSET;
1326 btn_type = rt5665_button_detect(rt5665->codec);
1327
1328
1329
1330
1331
1332
1333
1334 switch (btn_type) {
1335 case 0x8000:
1336 case 0x4000:
1337 case 0x2000:
1338 rt5665->jack_type |= SND_JACK_BTN_0;
1339 break;
1340 case 0x1000:
1341 case 0x0800:
1342 case 0x0400:
1343 rt5665->jack_type |= SND_JACK_BTN_1;
1344 break;
1345 case 0x0200:
1346 case 0x0100:
1347 case 0x0080:
1348 rt5665->jack_type |= SND_JACK_BTN_2;
1349 break;
1350 case 0x0040:
1351 case 0x0020:
1352 case 0x0010:
1353 rt5665->jack_type |= SND_JACK_BTN_3;
1354 break;
1355 case 0x0000:
1356 break;
1357 default:
1358 btn_type = 0;
1359 dev_err(rt5665->codec->dev,
1360 "Unexpected button code 0x%04x\n",
1361 btn_type);
1362 break;
1363 }
1364 }
1365 } else {
1366
1367 rt5665->jack_type = rt5665_headset_detect(rt5665->codec, 0);
1368 }
1369
1370 snd_soc_jack_report(rt5665->hs_jack, rt5665->jack_type,
1371 SND_JACK_HEADSET |
1372 SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1373 SND_JACK_BTN_2 | SND_JACK_BTN_3);
1374
1375 if (rt5665->jack_type & (SND_JACK_BTN_0 | SND_JACK_BTN_1 |
1376 SND_JACK_BTN_2 | SND_JACK_BTN_3))
1377 schedule_delayed_work(&rt5665->jd_check_work, 0);
1378 else
1379 cancel_delayed_work_sync(&rt5665->jd_check_work);
1380
1381 mutex_unlock(&rt5665->calibrate_mutex);
1382}
1383
1384static const struct snd_kcontrol_new rt5665_snd_controls[] = {
1385
1386 SOC_DOUBLE_R_EXT_TLV("Headphone Playback Volume", RT5665_HPL_GAIN,
1387 RT5665_HPR_GAIN, RT5665_G_HP_SFT, 15, 1, snd_soc_get_volsw,
1388 rt5665_hp_vol_put, hp_vol_tlv),
1389
1390
1391 SOC_SINGLE_EXT_TLV("Mono Playback Volume", RT5665_MONO_GAIN,
1392 RT5665_L_VOL_SFT, 15, 1, snd_soc_get_volsw,
1393 rt5665_mono_vol_put, mono_vol_tlv),
1394
1395
1396 SOC_DOUBLE_TLV("OUT Playback Volume", RT5665_LOUT, RT5665_L_VOL_SFT,
1397 RT5665_R_VOL_SFT, 39, 1, out_vol_tlv),
1398
1399
1400 SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5665_DAC1_DIG_VOL,
1401 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
1402 SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5665_DAC2_DIG_VOL,
1403 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 175, 0, dac_vol_tlv),
1404 SOC_DOUBLE("DAC2 Playback Switch", RT5665_DAC2_CTRL,
1405 RT5665_M_DAC2_L_VOL_SFT, RT5665_M_DAC2_R_VOL_SFT, 1, 1),
1406
1407
1408 SOC_SINGLE_TLV("IN1 Boost Volume", RT5665_IN1_IN2,
1409 RT5665_BST1_SFT, 69, 0, in_bst_tlv),
1410 SOC_SINGLE_TLV("IN2 Boost Volume", RT5665_IN1_IN2,
1411 RT5665_BST2_SFT, 69, 0, in_bst_tlv),
1412 SOC_SINGLE_TLV("IN3 Boost Volume", RT5665_IN3_IN4,
1413 RT5665_BST3_SFT, 69, 0, in_bst_tlv),
1414 SOC_SINGLE_TLV("IN4 Boost Volume", RT5665_IN3_IN4,
1415 RT5665_BST4_SFT, 69, 0, in_bst_tlv),
1416 SOC_SINGLE_TLV("CBJ Boost Volume", RT5665_CBJ_BST_CTRL,
1417 RT5665_BST_CBJ_SFT, 8, 0, bst_tlv),
1418
1419
1420 SOC_DOUBLE_TLV("IN Capture Volume", RT5665_INL1_INR1_VOL,
1421 RT5665_INL_VOL_SFT, RT5665_INR_VOL_SFT, 31, 1, in_vol_tlv),
1422
1423
1424 SOC_DOUBLE("STO1 ADC Capture Switch", RT5665_STO1_ADC_DIG_VOL,
1425 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1426 SOC_DOUBLE_TLV("STO1 ADC Capture Volume", RT5665_STO1_ADC_DIG_VOL,
1427 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1428 SOC_DOUBLE("Mono ADC Capture Switch", RT5665_MONO_ADC_DIG_VOL,
1429 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1430 SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5665_MONO_ADC_DIG_VOL,
1431 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1432 SOC_DOUBLE("STO2 ADC Capture Switch", RT5665_STO2_ADC_DIG_VOL,
1433 RT5665_L_MUTE_SFT, RT5665_R_MUTE_SFT, 1, 1),
1434 SOC_DOUBLE_TLV("STO2 ADC Capture Volume", RT5665_STO2_ADC_DIG_VOL,
1435 RT5665_L_VOL_SFT, RT5665_R_VOL_SFT, 127, 0, adc_vol_tlv),
1436
1437
1438 SOC_DOUBLE_TLV("STO1 ADC Boost Gain Volume", RT5665_STO1_ADC_BOOST,
1439 RT5665_STO1_ADC_L_BST_SFT, RT5665_STO1_ADC_R_BST_SFT,
1440 3, 0, adc_bst_tlv),
1441
1442 SOC_DOUBLE_TLV("Mono ADC Boost Gain Volume", RT5665_MONO_ADC_BOOST,
1443 RT5665_MONO_ADC_L_BST_SFT, RT5665_MONO_ADC_R_BST_SFT,
1444 3, 0, adc_bst_tlv),
1445
1446 SOC_DOUBLE_TLV("STO2 ADC Boost Gain Volume", RT5665_STO2_ADC_BOOST,
1447 RT5665_STO2_ADC_L_BST_SFT, RT5665_STO2_ADC_R_BST_SFT,
1448 3, 0, adc_bst_tlv),
1449};
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461static int set_dmic_clk(struct snd_soc_dapm_widget *w,
1462 struct snd_kcontrol *kcontrol, int event)
1463{
1464 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1465 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
1466 int pd, idx = -EINVAL;
1467
1468 pd = rl6231_get_pre_div(rt5665->regmap,
1469 RT5665_ADDA_CLK_1, RT5665_I2S_PD1_SFT);
1470 idx = rl6231_calc_dmic_clk(rt5665->sysclk / pd);
1471
1472 if (idx < 0)
1473 dev_err(codec->dev, "Failed to set DMIC clock\n");
1474 else {
1475 snd_soc_update_bits(codec, RT5665_DMIC_CTRL_1,
1476 RT5665_DMIC_CLK_MASK, idx << RT5665_DMIC_CLK_SFT);
1477 }
1478 return idx;
1479}
1480
1481static int rt5665_charge_pump_event(struct snd_soc_dapm_widget *w,
1482 struct snd_kcontrol *kcontrol, int event)
1483{
1484 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1485
1486 switch (event) {
1487 case SND_SOC_DAPM_PRE_PMU:
1488 snd_soc_update_bits(codec, RT5665_HP_CHARGE_PUMP_1,
1489 RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
1490 RT5665_PM_HP_HV | RT5665_OSW_L_EN);
1491 break;
1492 case SND_SOC_DAPM_POST_PMD:
1493 snd_soc_update_bits(codec, RT5665_HP_CHARGE_PUMP_1,
1494 RT5665_PM_HP_MASK | RT5665_OSW_L_MASK,
1495 RT5665_PM_HP_LV | RT5665_OSW_L_DIS);
1496 break;
1497 default:
1498 return 0;
1499 }
1500
1501 return 0;
1502}
1503
1504static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *w,
1505 struct snd_soc_dapm_widget *sink)
1506{
1507 unsigned int val;
1508 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1509
1510 val = snd_soc_read(codec, RT5665_GLB_CLK);
1511 val &= RT5665_SCLK_SRC_MASK;
1512 if (val == RT5665_SCLK_SRC_PLL1)
1513 return 1;
1514 else
1515 return 0;
1516}
1517
1518static int is_using_asrc(struct snd_soc_dapm_widget *w,
1519 struct snd_soc_dapm_widget *sink)
1520{
1521 unsigned int reg, shift, val;
1522 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
1523
1524 switch (w->shift) {
1525 case RT5665_ADC_MONO_R_ASRC_SFT:
1526 reg = RT5665_ASRC_3;
1527 shift = RT5665_AD_MONOR_CLK_SEL_SFT;
1528 break;
1529 case RT5665_ADC_MONO_L_ASRC_SFT:
1530 reg = RT5665_ASRC_3;
1531 shift = RT5665_AD_MONOL_CLK_SEL_SFT;
1532 break;
1533 case RT5665_ADC_STO1_ASRC_SFT:
1534 reg = RT5665_ASRC_3;
1535 shift = RT5665_AD_STO1_CLK_SEL_SFT;
1536 break;
1537 case RT5665_ADC_STO2_ASRC_SFT:
1538 reg = RT5665_ASRC_3;
1539 shift = RT5665_AD_STO2_CLK_SEL_SFT;
1540 break;
1541 case RT5665_DAC_MONO_R_ASRC_SFT:
1542 reg = RT5665_ASRC_2;
1543 shift = RT5665_DA_MONOR_CLK_SEL_SFT;
1544 break;
1545 case RT5665_DAC_MONO_L_ASRC_SFT:
1546 reg = RT5665_ASRC_2;
1547 shift = RT5665_DA_MONOL_CLK_SEL_SFT;
1548 break;
1549 case RT5665_DAC_STO1_ASRC_SFT:
1550 reg = RT5665_ASRC_2;
1551 shift = RT5665_DA_STO1_CLK_SEL_SFT;
1552 break;
1553 case RT5665_DAC_STO2_ASRC_SFT:
1554 reg = RT5665_ASRC_2;
1555 shift = RT5665_DA_STO2_CLK_SEL_SFT;
1556 break;
1557 default:
1558 return 0;
1559 }
1560
1561 val = (snd_soc_read(codec, reg) >> shift) & 0xf;
1562 switch (val) {
1563 case RT5665_CLK_SEL_I2S1_ASRC:
1564 case RT5665_CLK_SEL_I2S2_ASRC:
1565 case RT5665_CLK_SEL_I2S3_ASRC:
1566
1567 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
1568 RT5665_I2S_PD1_MASK, RT5665_I2S_PD1_2);
1569 return 1;
1570 default:
1571 return 0;
1572 }
1573
1574}
1575
1576
1577static const struct snd_kcontrol_new rt5665_sto1_adc_l_mix[] = {
1578 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
1579 RT5665_M_STO1_ADC_L1_SFT, 1, 1),
1580 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
1581 RT5665_M_STO1_ADC_L2_SFT, 1, 1),
1582};
1583
1584static const struct snd_kcontrol_new rt5665_sto1_adc_r_mix[] = {
1585 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO1_ADC_MIXER,
1586 RT5665_M_STO1_ADC_R1_SFT, 1, 1),
1587 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO1_ADC_MIXER,
1588 RT5665_M_STO1_ADC_R2_SFT, 1, 1),
1589};
1590
1591static const struct snd_kcontrol_new rt5665_sto2_adc_l_mix[] = {
1592 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
1593 RT5665_M_STO2_ADC_L1_SFT, 1, 1),
1594 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
1595 RT5665_M_STO2_ADC_L2_SFT, 1, 1),
1596};
1597
1598static const struct snd_kcontrol_new rt5665_sto2_adc_r_mix[] = {
1599 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_STO2_ADC_MIXER,
1600 RT5665_M_STO2_ADC_R1_SFT, 1, 1),
1601 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_STO2_ADC_MIXER,
1602 RT5665_M_STO2_ADC_R2_SFT, 1, 1),
1603};
1604
1605static const struct snd_kcontrol_new rt5665_mono_adc_l_mix[] = {
1606 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
1607 RT5665_M_MONO_ADC_L1_SFT, 1, 1),
1608 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
1609 RT5665_M_MONO_ADC_L2_SFT, 1, 1),
1610};
1611
1612static const struct snd_kcontrol_new rt5665_mono_adc_r_mix[] = {
1613 SOC_DAPM_SINGLE("ADC1 Switch", RT5665_MONO_ADC_MIXER,
1614 RT5665_M_MONO_ADC_R1_SFT, 1, 1),
1615 SOC_DAPM_SINGLE("ADC2 Switch", RT5665_MONO_ADC_MIXER,
1616 RT5665_M_MONO_ADC_R2_SFT, 1, 1),
1617};
1618
1619static const struct snd_kcontrol_new rt5665_dac_l_mix[] = {
1620 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
1621 RT5665_M_ADCMIX_L_SFT, 1, 1),
1622 SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
1623 RT5665_M_DAC1_L_SFT, 1, 1),
1624};
1625
1626static const struct snd_kcontrol_new rt5665_dac_r_mix[] = {
1627 SOC_DAPM_SINGLE("Stereo ADC Switch", RT5665_AD_DA_MIXER,
1628 RT5665_M_ADCMIX_R_SFT, 1, 1),
1629 SOC_DAPM_SINGLE("DAC1 Switch", RT5665_AD_DA_MIXER,
1630 RT5665_M_DAC1_R_SFT, 1, 1),
1631};
1632
1633static const struct snd_kcontrol_new rt5665_sto1_dac_l_mix[] = {
1634 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
1635 RT5665_M_DAC_L1_STO_L_SFT, 1, 1),
1636 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
1637 RT5665_M_DAC_R1_STO_L_SFT, 1, 1),
1638 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
1639 RT5665_M_DAC_L2_STO_L_SFT, 1, 1),
1640 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
1641 RT5665_M_DAC_R2_STO_L_SFT, 1, 1),
1642};
1643
1644static const struct snd_kcontrol_new rt5665_sto1_dac_r_mix[] = {
1645 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO1_DAC_MIXER,
1646 RT5665_M_DAC_L1_STO_R_SFT, 1, 1),
1647 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO1_DAC_MIXER,
1648 RT5665_M_DAC_R1_STO_R_SFT, 1, 1),
1649 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO1_DAC_MIXER,
1650 RT5665_M_DAC_L2_STO_R_SFT, 1, 1),
1651 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO1_DAC_MIXER,
1652 RT5665_M_DAC_R2_STO_R_SFT, 1, 1),
1653};
1654
1655static const struct snd_kcontrol_new rt5665_sto2_dac_l_mix[] = {
1656 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_STO2_DAC_MIXER,
1657 RT5665_M_DAC_L1_STO2_L_SFT, 1, 1),
1658 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_STO2_DAC_MIXER,
1659 RT5665_M_DAC_L2_STO2_L_SFT, 1, 1),
1660 SOC_DAPM_SINGLE("DAC L3 Switch", RT5665_STO2_DAC_MIXER,
1661 RT5665_M_DAC_L3_STO2_L_SFT, 1, 1),
1662};
1663
1664static const struct snd_kcontrol_new rt5665_sto2_dac_r_mix[] = {
1665 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_STO2_DAC_MIXER,
1666 RT5665_M_DAC_R1_STO2_R_SFT, 1, 1),
1667 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_STO2_DAC_MIXER,
1668 RT5665_M_DAC_R2_STO2_R_SFT, 1, 1),
1669 SOC_DAPM_SINGLE("DAC R3 Switch", RT5665_STO2_DAC_MIXER,
1670 RT5665_M_DAC_R3_STO2_R_SFT, 1, 1),
1671};
1672
1673static const struct snd_kcontrol_new rt5665_mono_dac_l_mix[] = {
1674 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
1675 RT5665_M_DAC_L1_MONO_L_SFT, 1, 1),
1676 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
1677 RT5665_M_DAC_R1_MONO_L_SFT, 1, 1),
1678 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
1679 RT5665_M_DAC_L2_MONO_L_SFT, 1, 1),
1680 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
1681 RT5665_M_DAC_R2_MONO_L_SFT, 1, 1),
1682};
1683
1684static const struct snd_kcontrol_new rt5665_mono_dac_r_mix[] = {
1685 SOC_DAPM_SINGLE("DAC L1 Switch", RT5665_MONO_DAC_MIXER,
1686 RT5665_M_DAC_L1_MONO_R_SFT, 1, 1),
1687 SOC_DAPM_SINGLE("DAC R1 Switch", RT5665_MONO_DAC_MIXER,
1688 RT5665_M_DAC_R1_MONO_R_SFT, 1, 1),
1689 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONO_DAC_MIXER,
1690 RT5665_M_DAC_L2_MONO_R_SFT, 1, 1),
1691 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_MONO_DAC_MIXER,
1692 RT5665_M_DAC_R2_MONO_R_SFT, 1, 1),
1693};
1694
1695
1696static const struct snd_kcontrol_new rt5665_rec1_l_mix[] = {
1697 SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC1_L2_MIXER,
1698 RT5665_M_CBJ_RM1_L_SFT, 1, 1),
1699 SOC_DAPM_SINGLE("INL Switch", RT5665_REC1_L2_MIXER,
1700 RT5665_M_INL_RM1_L_SFT, 1, 1),
1701 SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_L2_MIXER,
1702 RT5665_M_INR_RM1_L_SFT, 1, 1),
1703 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_L2_MIXER,
1704 RT5665_M_BST4_RM1_L_SFT, 1, 1),
1705 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_L2_MIXER,
1706 RT5665_M_BST3_RM1_L_SFT, 1, 1),
1707 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_L2_MIXER,
1708 RT5665_M_BST2_RM1_L_SFT, 1, 1),
1709 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_L2_MIXER,
1710 RT5665_M_BST1_RM1_L_SFT, 1, 1),
1711};
1712
1713static const struct snd_kcontrol_new rt5665_rec1_r_mix[] = {
1714 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC1_R2_MIXER,
1715 RT5665_M_AEC_REF_RM1_R_SFT, 1, 1),
1716 SOC_DAPM_SINGLE("INR Switch", RT5665_REC1_R2_MIXER,
1717 RT5665_M_INR_RM1_R_SFT, 1, 1),
1718 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC1_R2_MIXER,
1719 RT5665_M_BST4_RM1_R_SFT, 1, 1),
1720 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC1_R2_MIXER,
1721 RT5665_M_BST3_RM1_R_SFT, 1, 1),
1722 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC1_R2_MIXER,
1723 RT5665_M_BST2_RM1_R_SFT, 1, 1),
1724 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC1_R2_MIXER,
1725 RT5665_M_BST1_RM1_R_SFT, 1, 1),
1726};
1727
1728static const struct snd_kcontrol_new rt5665_rec2_l_mix[] = {
1729 SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_L2_MIXER,
1730 RT5665_M_INL_RM2_L_SFT, 1, 1),
1731 SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_L2_MIXER,
1732 RT5665_M_INR_RM2_L_SFT, 1, 1),
1733 SOC_DAPM_SINGLE("CBJ Switch", RT5665_REC2_L2_MIXER,
1734 RT5665_M_CBJ_RM2_L_SFT, 1, 1),
1735 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_L2_MIXER,
1736 RT5665_M_BST4_RM2_L_SFT, 1, 1),
1737 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_L2_MIXER,
1738 RT5665_M_BST3_RM2_L_SFT, 1, 1),
1739 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_L2_MIXER,
1740 RT5665_M_BST2_RM2_L_SFT, 1, 1),
1741 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_L2_MIXER,
1742 RT5665_M_BST1_RM2_L_SFT, 1, 1),
1743};
1744
1745static const struct snd_kcontrol_new rt5665_rec2_r_mix[] = {
1746 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_REC2_R2_MIXER,
1747 RT5665_M_MONOVOL_RM2_R_SFT, 1, 1),
1748 SOC_DAPM_SINGLE("INL Switch", RT5665_REC2_R2_MIXER,
1749 RT5665_M_INL_RM2_R_SFT, 1, 1),
1750 SOC_DAPM_SINGLE("INR Switch", RT5665_REC2_R2_MIXER,
1751 RT5665_M_INR_RM2_R_SFT, 1, 1),
1752 SOC_DAPM_SINGLE("BST4 Switch", RT5665_REC2_R2_MIXER,
1753 RT5665_M_BST4_RM2_R_SFT, 1, 1),
1754 SOC_DAPM_SINGLE("BST3 Switch", RT5665_REC2_R2_MIXER,
1755 RT5665_M_BST3_RM2_R_SFT, 1, 1),
1756 SOC_DAPM_SINGLE("BST2 Switch", RT5665_REC2_R2_MIXER,
1757 RT5665_M_BST2_RM2_R_SFT, 1, 1),
1758 SOC_DAPM_SINGLE("BST1 Switch", RT5665_REC2_R2_MIXER,
1759 RT5665_M_BST1_RM2_R_SFT, 1, 1),
1760};
1761
1762static const struct snd_kcontrol_new rt5665_monovol_mix[] = {
1763 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
1764 RT5665_M_DAC_L2_MM_SFT, 1, 1),
1765 SOC_DAPM_SINGLE("RECMIX2L Switch", RT5665_MONOMIX_IN_GAIN,
1766 RT5665_M_RECMIC2L_MM_SFT, 1, 1),
1767 SOC_DAPM_SINGLE("BST1 Switch", RT5665_MONOMIX_IN_GAIN,
1768 RT5665_M_BST1_MM_SFT, 1, 1),
1769 SOC_DAPM_SINGLE("BST2 Switch", RT5665_MONOMIX_IN_GAIN,
1770 RT5665_M_BST2_MM_SFT, 1, 1),
1771 SOC_DAPM_SINGLE("BST3 Switch", RT5665_MONOMIX_IN_GAIN,
1772 RT5665_M_BST3_MM_SFT, 1, 1),
1773};
1774
1775static const struct snd_kcontrol_new rt5665_out_l_mix[] = {
1776 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_OUT_L_MIXER,
1777 RT5665_M_DAC_L2_OM_L_SFT, 1, 1),
1778 SOC_DAPM_SINGLE("INL Switch", RT5665_OUT_L_MIXER,
1779 RT5665_M_IN_L_OM_L_SFT, 1, 1),
1780 SOC_DAPM_SINGLE("BST1 Switch", RT5665_OUT_L_MIXER,
1781 RT5665_M_BST1_OM_L_SFT, 1, 1),
1782 SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_L_MIXER,
1783 RT5665_M_BST2_OM_L_SFT, 1, 1),
1784 SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_L_MIXER,
1785 RT5665_M_BST3_OM_L_SFT, 1, 1),
1786};
1787
1788static const struct snd_kcontrol_new rt5665_out_r_mix[] = {
1789 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_OUT_R_MIXER,
1790 RT5665_M_DAC_R2_OM_R_SFT, 1, 1),
1791 SOC_DAPM_SINGLE("INR Switch", RT5665_OUT_R_MIXER,
1792 RT5665_M_IN_R_OM_R_SFT, 1, 1),
1793 SOC_DAPM_SINGLE("BST2 Switch", RT5665_OUT_R_MIXER,
1794 RT5665_M_BST2_OM_R_SFT, 1, 1),
1795 SOC_DAPM_SINGLE("BST3 Switch", RT5665_OUT_R_MIXER,
1796 RT5665_M_BST3_OM_R_SFT, 1, 1),
1797 SOC_DAPM_SINGLE("BST4 Switch", RT5665_OUT_R_MIXER,
1798 RT5665_M_BST4_OM_R_SFT, 1, 1),
1799};
1800
1801static const struct snd_kcontrol_new rt5665_mono_mix[] = {
1802 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_MONOMIX_IN_GAIN,
1803 RT5665_M_DAC_L2_MA_SFT, 1, 1),
1804 SOC_DAPM_SINGLE("MONOVOL Switch", RT5665_MONOMIX_IN_GAIN,
1805 RT5665_M_MONOVOL_MA_SFT, 1, 1),
1806};
1807
1808static const struct snd_kcontrol_new rt5665_lout_l_mix[] = {
1809 SOC_DAPM_SINGLE("DAC L2 Switch", RT5665_LOUT_MIXER,
1810 RT5665_M_DAC_L2_LM_SFT, 1, 1),
1811 SOC_DAPM_SINGLE("OUTVOL L Switch", RT5665_LOUT_MIXER,
1812 RT5665_M_OV_L_LM_SFT, 1, 1),
1813};
1814
1815static const struct snd_kcontrol_new rt5665_lout_r_mix[] = {
1816 SOC_DAPM_SINGLE("DAC R2 Switch", RT5665_LOUT_MIXER,
1817 RT5665_M_DAC_R2_LM_SFT, 1, 1),
1818 SOC_DAPM_SINGLE("OUTVOL R Switch", RT5665_LOUT_MIXER,
1819 RT5665_M_OV_R_LM_SFT, 1, 1),
1820};
1821
1822
1823
1824static const char * const rt5665_dac2_src[] = {
1825 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "Mono ADC MIX"
1826};
1827
1828static SOC_ENUM_SINGLE_DECL(
1829 rt5665_dac_l2_enum, RT5665_DAC2_CTRL,
1830 RT5665_DAC_L2_SEL_SFT, rt5665_dac2_src);
1831
1832static const struct snd_kcontrol_new rt5665_dac_l2_mux =
1833 SOC_DAPM_ENUM("Digital DAC L2 Source", rt5665_dac_l2_enum);
1834
1835static SOC_ENUM_SINGLE_DECL(
1836 rt5665_dac_r2_enum, RT5665_DAC2_CTRL,
1837 RT5665_DAC_R2_SEL_SFT, rt5665_dac2_src);
1838
1839static const struct snd_kcontrol_new rt5665_dac_r2_mux =
1840 SOC_DAPM_ENUM("Digital DAC R2 Source", rt5665_dac_r2_enum);
1841
1842
1843
1844static const char * const rt5665_dac3_src[] = {
1845 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC", "STO2 ADC MIX"
1846};
1847
1848static SOC_ENUM_SINGLE_DECL(
1849 rt5665_dac_l3_enum, RT5665_DAC3_CTRL,
1850 RT5665_DAC_L3_SEL_SFT, rt5665_dac3_src);
1851
1852static const struct snd_kcontrol_new rt5665_dac_l3_mux =
1853 SOC_DAPM_ENUM("Digital DAC L3 Source", rt5665_dac_l3_enum);
1854
1855static SOC_ENUM_SINGLE_DECL(
1856 rt5665_dac_r3_enum, RT5665_DAC3_CTRL,
1857 RT5665_DAC_R3_SEL_SFT, rt5665_dac3_src);
1858
1859static const struct snd_kcontrol_new rt5665_dac_r3_mux =
1860 SOC_DAPM_ENUM("Digital DAC R3 Source", rt5665_dac_r3_enum);
1861
1862
1863
1864static const char * const rt5665_sto1_adc1_src[] = {
1865 "DD Mux", "ADC"
1866};
1867
1868static SOC_ENUM_SINGLE_DECL(
1869 rt5665_sto1_adc1l_enum, RT5665_STO1_ADC_MIXER,
1870 RT5665_STO1_ADC1L_SRC_SFT, rt5665_sto1_adc1_src);
1871
1872static const struct snd_kcontrol_new rt5665_sto1_adc1l_mux =
1873 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1l_enum);
1874
1875static SOC_ENUM_SINGLE_DECL(
1876 rt5665_sto1_adc1r_enum, RT5665_STO1_ADC_MIXER,
1877 RT5665_STO1_ADC1R_SRC_SFT, rt5665_sto1_adc1_src);
1878
1879static const struct snd_kcontrol_new rt5665_sto1_adc1r_mux =
1880 SOC_DAPM_ENUM("Stereo1 ADC1L Source", rt5665_sto1_adc1r_enum);
1881
1882
1883
1884static const char * const rt5665_sto1_adc_src[] = {
1885 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
1886};
1887
1888static SOC_ENUM_SINGLE_DECL(
1889 rt5665_sto1_adcl_enum, RT5665_STO1_ADC_MIXER,
1890 RT5665_STO1_ADCL_SRC_SFT, rt5665_sto1_adc_src);
1891
1892static const struct snd_kcontrol_new rt5665_sto1_adcl_mux =
1893 SOC_DAPM_ENUM("Stereo1 ADCL Source", rt5665_sto1_adcl_enum);
1894
1895static SOC_ENUM_SINGLE_DECL(
1896 rt5665_sto1_adcr_enum, RT5665_STO1_ADC_MIXER,
1897 RT5665_STO1_ADCR_SRC_SFT, rt5665_sto1_adc_src);
1898
1899static const struct snd_kcontrol_new rt5665_sto1_adcr_mux =
1900 SOC_DAPM_ENUM("Stereo1 ADCR Source", rt5665_sto1_adcr_enum);
1901
1902
1903
1904static const char * const rt5665_sto1_adc2_src[] = {
1905 "DAC MIX", "DMIC"
1906};
1907
1908static SOC_ENUM_SINGLE_DECL(
1909 rt5665_sto1_adc2l_enum, RT5665_STO1_ADC_MIXER,
1910 RT5665_STO1_ADC2L_SRC_SFT, rt5665_sto1_adc2_src);
1911
1912static const struct snd_kcontrol_new rt5665_sto1_adc2l_mux =
1913 SOC_DAPM_ENUM("Stereo1 ADC2L Source", rt5665_sto1_adc2l_enum);
1914
1915static SOC_ENUM_SINGLE_DECL(
1916 rt5665_sto1_adc2r_enum, RT5665_STO1_ADC_MIXER,
1917 RT5665_STO1_ADC2R_SRC_SFT, rt5665_sto1_adc2_src);
1918
1919static const struct snd_kcontrol_new rt5665_sto1_adc2r_mux =
1920 SOC_DAPM_ENUM("Stereo1 ADC2R Source", rt5665_sto1_adc2r_enum);
1921
1922
1923
1924static const char * const rt5665_sto1_dmic_src[] = {
1925 "DMIC1", "DMIC2"
1926};
1927
1928static SOC_ENUM_SINGLE_DECL(
1929 rt5665_sto1_dmic_enum, RT5665_STO1_ADC_MIXER,
1930 RT5665_STO1_DMIC_SRC_SFT, rt5665_sto1_dmic_src);
1931
1932static const struct snd_kcontrol_new rt5665_sto1_dmic_mux =
1933 SOC_DAPM_ENUM("Stereo1 DMIC Mux", rt5665_sto1_dmic_enum);
1934
1935
1936static const char * const rt5665_sto1_dd_l_src[] = {
1937 "STO2 DAC", "MONO DAC"
1938};
1939
1940static SOC_ENUM_SINGLE_DECL(
1941 rt5665_sto1_dd_l_enum, RT5665_STO1_ADC_MIXER,
1942 RT5665_STO1_DD_L_SRC_SFT, rt5665_sto1_dd_l_src);
1943
1944static const struct snd_kcontrol_new rt5665_sto1_dd_l_mux =
1945 SOC_DAPM_ENUM("Stereo1 DD L Source", rt5665_sto1_dd_l_enum);
1946
1947
1948static const char * const rt5665_sto1_dd_r_src[] = {
1949 "STO2 DAC", "MONO DAC", "AEC REF"
1950};
1951
1952static SOC_ENUM_SINGLE_DECL(
1953 rt5665_sto1_dd_r_enum, RT5665_STO1_ADC_MIXER,
1954 RT5665_STO1_DD_R_SRC_SFT, rt5665_sto1_dd_r_src);
1955
1956static const struct snd_kcontrol_new rt5665_sto1_dd_r_mux =
1957 SOC_DAPM_ENUM("Stereo1 DD R Source", rt5665_sto1_dd_r_enum);
1958
1959
1960
1961static const char * const rt5665_mono_adc_l2_src[] = {
1962 "DAC MIXL", "DMIC"
1963};
1964
1965static SOC_ENUM_SINGLE_DECL(
1966 rt5665_mono_adc_l2_enum, RT5665_MONO_ADC_MIXER,
1967 RT5665_MONO_ADC_L2_SRC_SFT, rt5665_mono_adc_l2_src);
1968
1969static const struct snd_kcontrol_new rt5665_mono_adc_l2_mux =
1970 SOC_DAPM_ENUM("Mono ADC L2 Source", rt5665_mono_adc_l2_enum);
1971
1972
1973
1974
1975static const char * const rt5665_mono_adc_l1_src[] = {
1976 "DD Mux", "ADC"
1977};
1978
1979static SOC_ENUM_SINGLE_DECL(
1980 rt5665_mono_adc_l1_enum, RT5665_MONO_ADC_MIXER,
1981 RT5665_MONO_ADC_L1_SRC_SFT, rt5665_mono_adc_l1_src);
1982
1983static const struct snd_kcontrol_new rt5665_mono_adc_l1_mux =
1984 SOC_DAPM_ENUM("Mono ADC L1 Source", rt5665_mono_adc_l1_enum);
1985
1986
1987static const char * const rt5665_mono_dd_src[] = {
1988 "STO2 DAC", "MONO DAC"
1989};
1990
1991static SOC_ENUM_SINGLE_DECL(
1992 rt5665_mono_dd_l_enum, RT5665_MONO_ADC_MIXER,
1993 RT5665_MONO_DD_L_SRC_SFT, rt5665_mono_dd_src);
1994
1995static const struct snd_kcontrol_new rt5665_mono_dd_l_mux =
1996 SOC_DAPM_ENUM("Mono DD L Source", rt5665_mono_dd_l_enum);
1997
1998static SOC_ENUM_SINGLE_DECL(
1999 rt5665_mono_dd_r_enum, RT5665_MONO_ADC_MIXER,
2000 RT5665_MONO_DD_R_SRC_SFT, rt5665_mono_dd_src);
2001
2002static const struct snd_kcontrol_new rt5665_mono_dd_r_mux =
2003 SOC_DAPM_ENUM("Mono DD R Source", rt5665_mono_dd_r_enum);
2004
2005
2006
2007static const char * const rt5665_mono_adc_src[] = {
2008 "ADC1 L", "ADC1 R", "ADC2 L", "ADC2 R"
2009};
2010
2011static SOC_ENUM_SINGLE_DECL(
2012 rt5665_mono_adc_l_enum, RT5665_MONO_ADC_MIXER,
2013 RT5665_MONO_ADC_L_SRC_SFT, rt5665_mono_adc_src);
2014
2015static const struct snd_kcontrol_new rt5665_mono_adc_l_mux =
2016 SOC_DAPM_ENUM("Mono ADC L Source", rt5665_mono_adc_l_enum);
2017
2018static SOC_ENUM_SINGLE_DECL(
2019 rt5665_mono_adcr_enum, RT5665_MONO_ADC_MIXER,
2020 RT5665_MONO_ADC_R_SRC_SFT, rt5665_mono_adc_src);
2021
2022static const struct snd_kcontrol_new rt5665_mono_adc_r_mux =
2023 SOC_DAPM_ENUM("Mono ADC R Source", rt5665_mono_adcr_enum);
2024
2025
2026
2027static const char * const rt5665_mono_dmic_l_src[] = {
2028 "DMIC1 L", "DMIC2 L"
2029};
2030
2031static SOC_ENUM_SINGLE_DECL(
2032 rt5665_mono_dmic_l_enum, RT5665_MONO_ADC_MIXER,
2033 RT5665_MONO_DMIC_L_SRC_SFT, rt5665_mono_dmic_l_src);
2034
2035static const struct snd_kcontrol_new rt5665_mono_dmic_l_mux =
2036 SOC_DAPM_ENUM("Mono DMIC L Source", rt5665_mono_dmic_l_enum);
2037
2038
2039
2040static const char * const rt5665_mono_adc_r2_src[] = {
2041 "DAC MIXR", "DMIC"
2042};
2043
2044static SOC_ENUM_SINGLE_DECL(
2045 rt5665_mono_adc_r2_enum, RT5665_MONO_ADC_MIXER,
2046 RT5665_MONO_ADC_R2_SRC_SFT, rt5665_mono_adc_r2_src);
2047
2048static const struct snd_kcontrol_new rt5665_mono_adc_r2_mux =
2049 SOC_DAPM_ENUM("Mono ADC R2 Source", rt5665_mono_adc_r2_enum);
2050
2051
2052
2053static const char * const rt5665_mono_adc_r1_src[] = {
2054 "DD Mux", "ADC"
2055};
2056
2057static SOC_ENUM_SINGLE_DECL(
2058 rt5665_mono_adc_r1_enum, RT5665_MONO_ADC_MIXER,
2059 RT5665_MONO_ADC_R1_SRC_SFT, rt5665_mono_adc_r1_src);
2060
2061static const struct snd_kcontrol_new rt5665_mono_adc_r1_mux =
2062 SOC_DAPM_ENUM("Mono ADC R1 Source", rt5665_mono_adc_r1_enum);
2063
2064
2065
2066static const char * const rt5665_mono_dmic_r_src[] = {
2067 "DMIC1 R", "DMIC2 R"
2068};
2069
2070static SOC_ENUM_SINGLE_DECL(
2071 rt5665_mono_dmic_r_enum, RT5665_MONO_ADC_MIXER,
2072 RT5665_MONO_DMIC_R_SRC_SFT, rt5665_mono_dmic_r_src);
2073
2074static const struct snd_kcontrol_new rt5665_mono_dmic_r_mux =
2075 SOC_DAPM_ENUM("Mono DMIC R Source", rt5665_mono_dmic_r_enum);
2076
2077
2078
2079
2080static const char * const rt5665_sto2_adc1_src[] = {
2081 "DD Mux", "ADC"
2082};
2083
2084static SOC_ENUM_SINGLE_DECL(
2085 rt5665_sto2_adc1l_enum, RT5665_STO2_ADC_MIXER,
2086 RT5665_STO2_ADC1L_SRC_SFT, rt5665_sto2_adc1_src);
2087
2088static const struct snd_kcontrol_new rt5665_sto2_adc1l_mux =
2089 SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1l_enum);
2090
2091static SOC_ENUM_SINGLE_DECL(
2092 rt5665_sto2_adc1r_enum, RT5665_STO2_ADC_MIXER,
2093 RT5665_STO2_ADC1R_SRC_SFT, rt5665_sto2_adc1_src);
2094
2095static const struct snd_kcontrol_new rt5665_sto2_adc1r_mux =
2096 SOC_DAPM_ENUM("Stereo2 ADC1L Source", rt5665_sto2_adc1r_enum);
2097
2098
2099
2100static const char * const rt5665_sto2_adc_src[] = {
2101 "ADC1 L", "ADC1 R", "ADC2 L"
2102};
2103
2104static SOC_ENUM_SINGLE_DECL(
2105 rt5665_sto2_adcl_enum, RT5665_STO2_ADC_MIXER,
2106 RT5665_STO2_ADCL_SRC_SFT, rt5665_sto2_adc_src);
2107
2108static const struct snd_kcontrol_new rt5665_sto2_adcl_mux =
2109 SOC_DAPM_ENUM("Stereo2 ADCL Source", rt5665_sto2_adcl_enum);
2110
2111static SOC_ENUM_SINGLE_DECL(
2112 rt5665_sto2_adcr_enum, RT5665_STO2_ADC_MIXER,
2113 RT5665_STO2_ADCR_SRC_SFT, rt5665_sto2_adc_src);
2114
2115static const struct snd_kcontrol_new rt5665_sto2_adcr_mux =
2116 SOC_DAPM_ENUM("Stereo2 ADCR Source", rt5665_sto2_adcr_enum);
2117
2118
2119
2120static const char * const rt5665_sto2_adc2_src[] = {
2121 "DAC MIX", "DMIC"
2122};
2123
2124static SOC_ENUM_SINGLE_DECL(
2125 rt5665_sto2_adc2l_enum, RT5665_STO2_ADC_MIXER,
2126 RT5665_STO2_ADC2L_SRC_SFT, rt5665_sto2_adc2_src);
2127
2128static const struct snd_kcontrol_new rt5665_sto2_adc2l_mux =
2129 SOC_DAPM_ENUM("Stereo2 ADC2L Source", rt5665_sto2_adc2l_enum);
2130
2131static SOC_ENUM_SINGLE_DECL(
2132 rt5665_sto2_adc2r_enum, RT5665_STO2_ADC_MIXER,
2133 RT5665_STO2_ADC2R_SRC_SFT, rt5665_sto2_adc2_src);
2134
2135static const struct snd_kcontrol_new rt5665_sto2_adc2r_mux =
2136 SOC_DAPM_ENUM("Stereo2 ADC2R Source", rt5665_sto2_adc2r_enum);
2137
2138
2139
2140static const char * const rt5665_sto2_dmic_src[] = {
2141 "DMIC1", "DMIC2"
2142};
2143
2144static SOC_ENUM_SINGLE_DECL(
2145 rt5665_sto2_dmic_enum, RT5665_STO2_ADC_MIXER,
2146 RT5665_STO2_DMIC_SRC_SFT, rt5665_sto2_dmic_src);
2147
2148static const struct snd_kcontrol_new rt5665_sto2_dmic_mux =
2149 SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5665_sto2_dmic_enum);
2150
2151
2152static const char * const rt5665_sto2_dd_l_src[] = {
2153 "STO2 DAC", "MONO DAC"
2154};
2155
2156static SOC_ENUM_SINGLE_DECL(
2157 rt5665_sto2_dd_l_enum, RT5665_STO2_ADC_MIXER,
2158 RT5665_STO2_DD_L_SRC_SFT, rt5665_sto2_dd_l_src);
2159
2160static const struct snd_kcontrol_new rt5665_sto2_dd_l_mux =
2161 SOC_DAPM_ENUM("Stereo2 DD L Source", rt5665_sto2_dd_l_enum);
2162
2163
2164static const char * const rt5665_sto2_dd_r_src[] = {
2165 "STO2 DAC", "MONO DAC"
2166};
2167
2168static SOC_ENUM_SINGLE_DECL(
2169 rt5665_sto2_dd_r_enum, RT5665_STO2_ADC_MIXER,
2170 RT5665_STO2_DD_R_SRC_SFT, rt5665_sto2_dd_r_src);
2171
2172static const struct snd_kcontrol_new rt5665_sto2_dd_r_mux =
2173 SOC_DAPM_ENUM("Stereo2 DD R Source", rt5665_sto2_dd_r_enum);
2174
2175
2176
2177static const char * const rt5665_dac1_src[] = {
2178 "IF1 DAC1", "IF2_1 DAC", "IF2_2 DAC", "IF3 DAC"
2179};
2180
2181static SOC_ENUM_SINGLE_DECL(
2182 rt5665_dac_r1_enum, RT5665_AD_DA_MIXER,
2183 RT5665_DAC1_R_SEL_SFT, rt5665_dac1_src);
2184
2185static const struct snd_kcontrol_new rt5665_dac_r1_mux =
2186 SOC_DAPM_ENUM("DAC R1 Source", rt5665_dac_r1_enum);
2187
2188static SOC_ENUM_SINGLE_DECL(
2189 rt5665_dac_l1_enum, RT5665_AD_DA_MIXER,
2190 RT5665_DAC1_L_SEL_SFT, rt5665_dac1_src);
2191
2192static const struct snd_kcontrol_new rt5665_dac_l1_mux =
2193 SOC_DAPM_ENUM("DAC L1 Source", rt5665_dac_l1_enum);
2194
2195
2196
2197static const char * const rt5665_dig_dac_mix_src[] = {
2198 "Stereo1 DAC Mixer", "Stereo2 DAC Mixer", "Mono DAC Mixer"
2199};
2200
2201static SOC_ENUM_SINGLE_DECL(
2202 rt5665_dig_dac_mixl_enum, RT5665_A_DAC1_MUX,
2203 RT5665_DAC_MIX_L_SFT, rt5665_dig_dac_mix_src);
2204
2205static const struct snd_kcontrol_new rt5665_dig_dac_mixl_mux =
2206 SOC_DAPM_ENUM("DAC Digital Mixer L Source", rt5665_dig_dac_mixl_enum);
2207
2208static SOC_ENUM_SINGLE_DECL(
2209 rt5665_dig_dac_mixr_enum, RT5665_A_DAC1_MUX,
2210 RT5665_DAC_MIX_R_SFT, rt5665_dig_dac_mix_src);
2211
2212static const struct snd_kcontrol_new rt5665_dig_dac_mixr_mux =
2213 SOC_DAPM_ENUM("DAC Digital Mixer R Source", rt5665_dig_dac_mixr_enum);
2214
2215
2216
2217static const char * const rt5665_alg_dac1_src[] = {
2218 "Stereo1 DAC Mixer", "DAC1", "DMIC1"
2219};
2220
2221static SOC_ENUM_SINGLE_DECL(
2222 rt5665_alg_dac_l1_enum, RT5665_A_DAC1_MUX,
2223 RT5665_A_DACL1_SFT, rt5665_alg_dac1_src);
2224
2225static const struct snd_kcontrol_new rt5665_alg_dac_l1_mux =
2226 SOC_DAPM_ENUM("Analog DAC L1 Source", rt5665_alg_dac_l1_enum);
2227
2228static SOC_ENUM_SINGLE_DECL(
2229 rt5665_alg_dac_r1_enum, RT5665_A_DAC1_MUX,
2230 RT5665_A_DACR1_SFT, rt5665_alg_dac1_src);
2231
2232static const struct snd_kcontrol_new rt5665_alg_dac_r1_mux =
2233 SOC_DAPM_ENUM("Analog DAC R1 Source", rt5665_alg_dac_r1_enum);
2234
2235
2236
2237static const char * const rt5665_alg_dac2_src[] = {
2238 "Mono DAC Mixer", "DAC2"
2239};
2240
2241static SOC_ENUM_SINGLE_DECL(
2242 rt5665_alg_dac_l2_enum, RT5665_A_DAC2_MUX,
2243 RT5665_A_DACL2_SFT, rt5665_alg_dac2_src);
2244
2245static const struct snd_kcontrol_new rt5665_alg_dac_l2_mux =
2246 SOC_DAPM_ENUM("Analog DAC L2 Source", rt5665_alg_dac_l2_enum);
2247
2248static SOC_ENUM_SINGLE_DECL(
2249 rt5665_alg_dac_r2_enum, RT5665_A_DAC2_MUX,
2250 RT5665_A_DACR2_SFT, rt5665_alg_dac2_src);
2251
2252static const struct snd_kcontrol_new rt5665_alg_dac_r2_mux =
2253 SOC_DAPM_ENUM("Analog DAC R2 Source", rt5665_alg_dac_r2_enum);
2254
2255
2256
2257static const char * const rt5665_if2_1_adc_in_src[] = {
2258 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2259 "IF1 DAC2", "IF2_2 DAC", "IF3 DAC", "DAC1 MIX"
2260};
2261
2262static SOC_ENUM_SINGLE_DECL(
2263 rt5665_if2_1_adc_in_enum, RT5665_DIG_INF2_DATA,
2264 RT5665_IF2_1_ADC_IN_SFT, rt5665_if2_1_adc_in_src);
2265
2266static const struct snd_kcontrol_new rt5665_if2_1_adc_in_mux =
2267 SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_1_adc_in_enum);
2268
2269
2270static const char * const rt5665_if2_2_adc_in_src[] = {
2271 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2272 "IF1 DAC2", "IF2_1 DAC", "IF3 DAC", "DAC1 MIX"
2273};
2274
2275static SOC_ENUM_SINGLE_DECL(
2276 rt5665_if2_2_adc_in_enum, RT5665_DIG_INF2_DATA,
2277 RT5665_IF2_2_ADC_IN_SFT, rt5665_if2_2_adc_in_src);
2278
2279static const struct snd_kcontrol_new rt5665_if2_2_adc_in_mux =
2280 SOC_DAPM_ENUM("IF2_1 ADC IN Source", rt5665_if2_2_adc_in_enum);
2281
2282
2283
2284static const char * const rt5665_if3_adc_in_src[] = {
2285 "STO1 ADC", "STO2 ADC", "MONO ADC", "IF1 DAC1",
2286 "IF1 DAC2", "IF2_1 DAC", "IF2_2 DAC", "DAC1 MIX"
2287};
2288
2289static SOC_ENUM_SINGLE_DECL(
2290 rt5665_if3_adc_in_enum, RT5665_DIG_INF3_DATA,
2291 RT5665_IF3_ADC_IN_SFT, rt5665_if3_adc_in_src);
2292
2293static const struct snd_kcontrol_new rt5665_if3_adc_in_mux =
2294 SOC_DAPM_ENUM("IF3 ADC IN Source", rt5665_if3_adc_in_enum);
2295
2296
2297
2298static const char * const rt5665_pdm_src[] = {
2299 "Stereo1 DAC", "Stereo2 DAC", "Mono DAC"
2300};
2301
2302static SOC_ENUM_SINGLE_DECL(
2303 rt5665_pdm_l_enum, RT5665_PDM_OUT_CTRL,
2304 RT5665_PDM1_L_SFT, rt5665_pdm_src);
2305
2306static const struct snd_kcontrol_new rt5665_pdm_l_mux =
2307 SOC_DAPM_ENUM("PDM L Source", rt5665_pdm_l_enum);
2308
2309static SOC_ENUM_SINGLE_DECL(
2310 rt5665_pdm_r_enum, RT5665_PDM_OUT_CTRL,
2311 RT5665_PDM1_R_SFT, rt5665_pdm_src);
2312
2313static const struct snd_kcontrol_new rt5665_pdm_r_mux =
2314 SOC_DAPM_ENUM("PDM R Source", rt5665_pdm_r_enum);
2315
2316
2317
2318
2319static const char * const rt5665_if1_1_adc1_data_src[] = {
2320 "STO1 ADC", "IF2_1 DAC",
2321};
2322
2323static SOC_ENUM_SINGLE_DECL(
2324 rt5665_if1_1_adc1_data_enum, RT5665_TDM_CTRL_3,
2325 RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_1_adc1_data_src);
2326
2327static const struct snd_kcontrol_new rt5665_if1_1_adc1_mux =
2328 SOC_DAPM_ENUM("IF1_1 ADC1 Source", rt5665_if1_1_adc1_data_enum);
2329
2330
2331static const char * const rt5665_if1_1_adc2_data_src[] = {
2332 "STO2 ADC", "IF2_2 DAC",
2333};
2334
2335static SOC_ENUM_SINGLE_DECL(
2336 rt5665_if1_1_adc2_data_enum, RT5665_TDM_CTRL_3,
2337 RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_1_adc2_data_src);
2338
2339static const struct snd_kcontrol_new rt5665_if1_1_adc2_mux =
2340 SOC_DAPM_ENUM("IF1_1 ADC2 Source", rt5665_if1_1_adc2_data_enum);
2341
2342
2343static const char * const rt5665_if1_1_adc3_data_src[] = {
2344 "MONO ADC", "IF3 DAC",
2345};
2346
2347static SOC_ENUM_SINGLE_DECL(
2348 rt5665_if1_1_adc3_data_enum, RT5665_TDM_CTRL_3,
2349 RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_1_adc3_data_src);
2350
2351static const struct snd_kcontrol_new rt5665_if1_1_adc3_mux =
2352 SOC_DAPM_ENUM("IF1_1 ADC3 Source", rt5665_if1_1_adc3_data_enum);
2353
2354
2355static const char * const rt5665_if1_2_adc1_data_src[] = {
2356 "STO1 ADC", "IF1 DAC",
2357};
2358
2359static SOC_ENUM_SINGLE_DECL(
2360 rt5665_if1_2_adc1_data_enum, RT5665_TDM_CTRL_4,
2361 RT5665_IF1_ADC1_SEL_SFT, rt5665_if1_2_adc1_data_src);
2362
2363static const struct snd_kcontrol_new rt5665_if1_2_adc1_mux =
2364 SOC_DAPM_ENUM("IF1_2 ADC1 Source", rt5665_if1_2_adc1_data_enum);
2365
2366
2367static const char * const rt5665_if1_2_adc2_data_src[] = {
2368 "STO2 ADC", "IF2_1 DAC",
2369};
2370
2371static SOC_ENUM_SINGLE_DECL(
2372 rt5665_if1_2_adc2_data_enum, RT5665_TDM_CTRL_4,
2373 RT5665_IF1_ADC2_SEL_SFT, rt5665_if1_2_adc2_data_src);
2374
2375static const struct snd_kcontrol_new rt5665_if1_2_adc2_mux =
2376 SOC_DAPM_ENUM("IF1_2 ADC2 Source", rt5665_if1_2_adc2_data_enum);
2377
2378
2379static const char * const rt5665_if1_2_adc3_data_src[] = {
2380 "MONO ADC", "IF2_2 DAC",
2381};
2382
2383static SOC_ENUM_SINGLE_DECL(
2384 rt5665_if1_2_adc3_data_enum, RT5665_TDM_CTRL_4,
2385 RT5665_IF1_ADC3_SEL_SFT, rt5665_if1_2_adc3_data_src);
2386
2387static const struct snd_kcontrol_new rt5665_if1_2_adc3_mux =
2388 SOC_DAPM_ENUM("IF1_2 ADC3 Source", rt5665_if1_2_adc3_data_enum);
2389
2390
2391static const char * const rt5665_if1_2_adc4_data_src[] = {
2392 "DAC1", "IF3 DAC",
2393};
2394
2395static SOC_ENUM_SINGLE_DECL(
2396 rt5665_if1_2_adc4_data_enum, RT5665_TDM_CTRL_4,
2397 RT5665_IF1_ADC4_SEL_SFT, rt5665_if1_2_adc4_data_src);
2398
2399static const struct snd_kcontrol_new rt5665_if1_2_adc4_mux =
2400 SOC_DAPM_ENUM("IF1_2 ADC4 Source", rt5665_if1_2_adc4_data_enum);
2401
2402
2403static const char * const rt5665_tdm_adc_data_src[] = {
2404 "1234", "1243", "1324", "1342", "1432", "1423",
2405 "2134", "2143", "2314", "2341", "2431", "2413",
2406 "3124", "3142", "3214", "3241", "3412", "3421",
2407 "4123", "4132", "4213", "4231", "4312", "4321"
2408};
2409
2410static SOC_ENUM_SINGLE_DECL(
2411 rt5665_tdm1_adc_data_enum, RT5665_TDM_CTRL_3,
2412 RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
2413
2414static const struct snd_kcontrol_new rt5665_tdm1_adc_mux =
2415 SOC_DAPM_ENUM("TDM1 ADC Mux", rt5665_tdm1_adc_data_enum);
2416
2417static SOC_ENUM_SINGLE_DECL(
2418 rt5665_tdm2_adc_data_enum, RT5665_TDM_CTRL_4,
2419 RT5665_TDM_ADC_SEL_SFT, rt5665_tdm_adc_data_src);
2420
2421static const struct snd_kcontrol_new rt5665_tdm2_adc_mux =
2422 SOC_DAPM_ENUM("TDM2 ADCDAT Source", rt5665_tdm2_adc_data_enum);
2423
2424
2425static const struct snd_kcontrol_new monovol_switch =
2426 SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_VOL_L_SFT, 1, 1);
2427
2428static const struct snd_kcontrol_new outvol_l_switch =
2429 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_L_SFT, 1, 1);
2430
2431static const struct snd_kcontrol_new outvol_r_switch =
2432 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_VOL_R_SFT, 1, 1);
2433
2434
2435static const struct snd_kcontrol_new mono_switch =
2436 SOC_DAPM_SINGLE("Switch", RT5665_MONO_OUT, RT5665_L_MUTE_SFT, 1, 1);
2437
2438static const struct snd_kcontrol_new hpo_switch =
2439 SOC_DAPM_SINGLE_AUTODISABLE("Switch", RT5665_HP_CTRL_2,
2440 RT5665_VOL_L_SFT, 1, 0);
2441
2442static const struct snd_kcontrol_new lout_l_switch =
2443 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_L_MUTE_SFT, 1, 1);
2444
2445static const struct snd_kcontrol_new lout_r_switch =
2446 SOC_DAPM_SINGLE("Switch", RT5665_LOUT, RT5665_R_MUTE_SFT, 1, 1);
2447
2448static const struct snd_kcontrol_new pdm_l_switch =
2449 SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
2450 RT5665_M_PDM1_L_SFT, 1, 1);
2451
2452static const struct snd_kcontrol_new pdm_r_switch =
2453 SOC_DAPM_SINGLE("Switch", RT5665_PDM_OUT_CTRL,
2454 RT5665_M_PDM1_R_SFT, 1, 1);
2455
2456static int rt5665_mono_event(struct snd_soc_dapm_widget *w,
2457 struct snd_kcontrol *kcontrol, int event)
2458{
2459 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2460
2461 switch (event) {
2462 case SND_SOC_DAPM_PRE_PMU:
2463 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
2464 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
2465 snd_soc_update_bits(codec, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
2466 0x0);
2467 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x10, 0x10);
2468 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x20, 0x20);
2469 break;
2470
2471 case SND_SOC_DAPM_POST_PMD:
2472 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x20, 0);
2473 snd_soc_update_bits(codec, RT5665_MONO_OUT, 0x10, 0);
2474 snd_soc_update_bits(codec, RT5665_MONO_AMP_CALIB_CTRL_1, 0x40,
2475 0x40);
2476 snd_soc_update_bits(codec, RT5665_MONO_NG2_CTRL_1,
2477 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
2478 break;
2479
2480 default:
2481 return 0;
2482 }
2483
2484 return 0;
2485
2486}
2487
2488static int rt5665_hp_event(struct snd_soc_dapm_widget *w,
2489 struct snd_kcontrol *kcontrol, int event)
2490{
2491 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2492
2493 switch (event) {
2494 case SND_SOC_DAPM_PRE_PMU:
2495 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
2496 RT5665_NG2_EN_MASK, RT5665_NG2_EN);
2497 snd_soc_write(codec, RT5665_HP_LOGIC_CTRL_2, 0x0003);
2498 break;
2499
2500 case SND_SOC_DAPM_POST_PMD:
2501 snd_soc_write(codec, RT5665_HP_LOGIC_CTRL_2, 0x0002);
2502 snd_soc_update_bits(codec, RT5665_STO_NG2_CTRL_1,
2503 RT5665_NG2_EN_MASK, RT5665_NG2_DIS);
2504 break;
2505
2506 default:
2507 return 0;
2508 }
2509
2510 return 0;
2511
2512}
2513
2514static int rt5665_lout_event(struct snd_soc_dapm_widget *w,
2515 struct snd_kcontrol *kcontrol, int event)
2516{
2517 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2518
2519 switch (event) {
2520 case SND_SOC_DAPM_POST_PMU:
2521 snd_soc_update_bits(codec, RT5665_DEPOP_1,
2522 RT5665_PUMP_EN, RT5665_PUMP_EN);
2523 break;
2524
2525 case SND_SOC_DAPM_PRE_PMD:
2526 snd_soc_update_bits(codec, RT5665_DEPOP_1,
2527 RT5665_PUMP_EN, 0);
2528 break;
2529
2530 default:
2531 return 0;
2532 }
2533
2534 return 0;
2535
2536}
2537
2538static int set_dmic_power(struct snd_soc_dapm_widget *w,
2539 struct snd_kcontrol *kcontrol, int event)
2540{
2541 switch (event) {
2542 case SND_SOC_DAPM_POST_PMU:
2543
2544 msleep(150);
2545 break;
2546
2547 default:
2548 return 0;
2549 }
2550
2551 return 0;
2552}
2553
2554static int rt5655_set_verf(struct snd_soc_dapm_widget *w,
2555 struct snd_kcontrol *kcontrol, int event)
2556{
2557 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2558
2559 switch (event) {
2560 case SND_SOC_DAPM_PRE_PMU:
2561 switch (w->shift) {
2562 case RT5665_PWR_VREF1_BIT:
2563 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2564 RT5665_PWR_FV1, 0);
2565 break;
2566
2567 case RT5665_PWR_VREF2_BIT:
2568 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2569 RT5665_PWR_FV2, 0);
2570 break;
2571
2572 case RT5665_PWR_VREF3_BIT:
2573 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2574 RT5665_PWR_FV3, 0);
2575 break;
2576
2577 default:
2578 break;
2579 }
2580 break;
2581
2582 case SND_SOC_DAPM_POST_PMU:
2583 usleep_range(15000, 20000);
2584 switch (w->shift) {
2585 case RT5665_PWR_VREF1_BIT:
2586 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2587 RT5665_PWR_FV1, RT5665_PWR_FV1);
2588 break;
2589
2590 case RT5665_PWR_VREF2_BIT:
2591 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2592 RT5665_PWR_FV2, RT5665_PWR_FV2);
2593 break;
2594
2595 case RT5665_PWR_VREF3_BIT:
2596 snd_soc_update_bits(codec, RT5665_PWR_ANLG_1,
2597 RT5665_PWR_FV3, RT5665_PWR_FV3);
2598 break;
2599
2600 default:
2601 break;
2602 }
2603 break;
2604
2605 default:
2606 return 0;
2607 }
2608
2609 return 0;
2610}
2611
2612static int rt5665_i2s_pin_event(struct snd_soc_dapm_widget *w,
2613 struct snd_kcontrol *kcontrol, int event)
2614{
2615 struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
2616 unsigned int val1, val2, mask1 = 0, mask2 = 0;
2617
2618 switch (w->shift) {
2619 case RT5665_PWR_I2S2_1_BIT:
2620 mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK |
2621 RT5665_GP4_PIN_MASK | RT5665_GP5_PIN_MASK;
2622 val1 = RT5665_GP2_PIN_BCLK2 | RT5665_GP3_PIN_LRCK2 |
2623 RT5665_GP4_PIN_DACDAT2_1 | RT5665_GP5_PIN_ADCDAT2_1;
2624 break;
2625 case RT5665_PWR_I2S2_2_BIT:
2626 mask1 = RT5665_GP2_PIN_MASK | RT5665_GP3_PIN_MASK |
2627 RT5665_GP8_PIN_MASK;
2628 val1 = RT5665_GP2_PIN_BCLK2 | RT5665_GP3_PIN_LRCK2 |
2629 RT5665_GP8_PIN_DACDAT2_2;
2630 mask2 = RT5665_GP9_PIN_MASK;
2631 val2 = RT5665_GP9_PIN_ADCDAT2_2;
2632 break;
2633 case RT5665_PWR_I2S3_BIT:
2634 mask1 = RT5665_GP6_PIN_MASK | RT5665_GP7_PIN_MASK |
2635 RT5665_GP8_PIN_MASK;
2636 val1 = RT5665_GP6_PIN_BCLK3 | RT5665_GP7_PIN_LRCK3 |
2637 RT5665_GP8_PIN_DACDAT3;
2638 mask2 = RT5665_GP9_PIN_MASK;
2639 val2 = RT5665_GP9_PIN_ADCDAT3;
2640 break;
2641 }
2642 switch (event) {
2643 case SND_SOC_DAPM_PRE_PMU:
2644 if (mask1)
2645 snd_soc_update_bits(codec, RT5665_GPIO_CTRL_1,
2646 mask1, val1);
2647 if (mask2)
2648 snd_soc_update_bits(codec, RT5665_GPIO_CTRL_2,
2649 mask2, val2);
2650 break;
2651 case SND_SOC_DAPM_POST_PMD:
2652 if (mask1)
2653 snd_soc_update_bits(codec, RT5665_GPIO_CTRL_1,
2654 mask1, 0);
2655 if (mask2)
2656 snd_soc_update_bits(codec, RT5665_GPIO_CTRL_2,
2657 mask2, 0);
2658 break;
2659 default:
2660 return 0;
2661 }
2662
2663 return 0;
2664}
2665
2666static const struct snd_soc_dapm_widget rt5665_dapm_widgets[] = {
2667 SND_SOC_DAPM_SUPPLY("LDO2", RT5665_PWR_ANLG_3, RT5665_PWR_LDO2_BIT, 0,
2668 NULL, 0),
2669 SND_SOC_DAPM_SUPPLY("PLL", RT5665_PWR_ANLG_3, RT5665_PWR_PLL_BIT, 0,
2670 NULL, 0),
2671 SND_SOC_DAPM_SUPPLY("Mic Det Power", RT5665_PWR_VOL,
2672 RT5665_PWR_MIC_DET_BIT, 0, NULL, 0),
2673 SND_SOC_DAPM_SUPPLY("Vref1", RT5665_PWR_ANLG_1, RT5665_PWR_VREF1_BIT, 0,
2674 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2675 SND_SOC_DAPM_SUPPLY("Vref2", RT5665_PWR_ANLG_1, RT5665_PWR_VREF2_BIT, 0,
2676 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2677 SND_SOC_DAPM_SUPPLY("Vref3", RT5665_PWR_ANLG_1, RT5665_PWR_VREF3_BIT, 0,
2678 rt5655_set_verf, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU),
2679
2680
2681 SND_SOC_DAPM_SUPPLY_S("I2S1 ASRC", 1, RT5665_ASRC_1,
2682 RT5665_I2S1_ASRC_SFT, 0, NULL, 0),
2683 SND_SOC_DAPM_SUPPLY_S("I2S2 ASRC", 1, RT5665_ASRC_1,
2684 RT5665_I2S2_ASRC_SFT, 0, NULL, 0),
2685 SND_SOC_DAPM_SUPPLY_S("I2S3 ASRC", 1, RT5665_ASRC_1,
2686 RT5665_I2S3_ASRC_SFT, 0, NULL, 0),
2687 SND_SOC_DAPM_SUPPLY_S("DAC STO1 ASRC", 1, RT5665_ASRC_1,
2688 RT5665_DAC_STO1_ASRC_SFT, 0, NULL, 0),
2689 SND_SOC_DAPM_SUPPLY_S("DAC STO2 ASRC", 1, RT5665_ASRC_1,
2690 RT5665_DAC_STO2_ASRC_SFT, 0, NULL, 0),
2691 SND_SOC_DAPM_SUPPLY_S("DAC Mono L ASRC", 1, RT5665_ASRC_1,
2692 RT5665_DAC_MONO_L_ASRC_SFT, 0, NULL, 0),
2693 SND_SOC_DAPM_SUPPLY_S("DAC Mono R ASRC", 1, RT5665_ASRC_1,
2694 RT5665_DAC_MONO_R_ASRC_SFT, 0, NULL, 0),
2695 SND_SOC_DAPM_SUPPLY_S("ADC STO1 ASRC", 1, RT5665_ASRC_1,
2696 RT5665_ADC_STO1_ASRC_SFT, 0, NULL, 0),
2697 SND_SOC_DAPM_SUPPLY_S("ADC STO2 ASRC", 1, RT5665_ASRC_1,
2698 RT5665_ADC_STO2_ASRC_SFT, 0, NULL, 0),
2699 SND_SOC_DAPM_SUPPLY_S("ADC Mono L ASRC", 1, RT5665_ASRC_1,
2700 RT5665_ADC_MONO_L_ASRC_SFT, 0, NULL, 0),
2701 SND_SOC_DAPM_SUPPLY_S("ADC Mono R ASRC", 1, RT5665_ASRC_1,
2702 RT5665_ADC_MONO_R_ASRC_SFT, 0, NULL, 0),
2703 SND_SOC_DAPM_SUPPLY_S("DMIC STO1 ASRC", 1, RT5665_ASRC_1,
2704 RT5665_DMIC_STO1_ASRC_SFT, 0, NULL, 0),
2705 SND_SOC_DAPM_SUPPLY_S("DMIC STO2 ASRC", 1, RT5665_ASRC_1,
2706 RT5665_DMIC_STO2_ASRC_SFT, 0, NULL, 0),
2707 SND_SOC_DAPM_SUPPLY_S("DMIC MONO L ASRC", 1, RT5665_ASRC_1,
2708 RT5665_DMIC_MONO_L_ASRC_SFT, 0, NULL, 0),
2709 SND_SOC_DAPM_SUPPLY_S("DMIC MONO R ASRC", 1, RT5665_ASRC_1,
2710 RT5665_DMIC_MONO_R_ASRC_SFT, 0, NULL, 0),
2711
2712
2713 SND_SOC_DAPM_SUPPLY("MICBIAS1", RT5665_PWR_ANLG_2, RT5665_PWR_MB1_BIT,
2714 0, NULL, 0),
2715 SND_SOC_DAPM_SUPPLY("MICBIAS2", RT5665_PWR_ANLG_2, RT5665_PWR_MB2_BIT,
2716 0, NULL, 0),
2717 SND_SOC_DAPM_SUPPLY("MICBIAS3", RT5665_PWR_ANLG_2, RT5665_PWR_MB3_BIT,
2718 0, NULL, 0),
2719
2720
2721 SND_SOC_DAPM_INPUT("DMIC L1"),
2722 SND_SOC_DAPM_INPUT("DMIC R1"),
2723 SND_SOC_DAPM_INPUT("DMIC L2"),
2724 SND_SOC_DAPM_INPUT("DMIC R2"),
2725
2726 SND_SOC_DAPM_INPUT("IN1P"),
2727 SND_SOC_DAPM_INPUT("IN1N"),
2728 SND_SOC_DAPM_INPUT("IN2P"),
2729 SND_SOC_DAPM_INPUT("IN2N"),
2730 SND_SOC_DAPM_INPUT("IN3P"),
2731 SND_SOC_DAPM_INPUT("IN3N"),
2732 SND_SOC_DAPM_INPUT("IN4P"),
2733 SND_SOC_DAPM_INPUT("IN4N"),
2734
2735 SND_SOC_DAPM_PGA("DMIC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2736 SND_SOC_DAPM_PGA("DMIC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2737
2738 SND_SOC_DAPM_SUPPLY("DMIC CLK", SND_SOC_NOPM, 0, 0,
2739 set_dmic_clk, SND_SOC_DAPM_PRE_PMU),
2740 SND_SOC_DAPM_SUPPLY("DMIC1 Power", RT5665_DMIC_CTRL_1,
2741 RT5665_DMIC_1_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2742 SND_SOC_DAPM_SUPPLY("DMIC2 Power", RT5665_DMIC_CTRL_1,
2743 RT5665_DMIC_2_EN_SFT, 0, set_dmic_power, SND_SOC_DAPM_POST_PMU),
2744
2745
2746 SND_SOC_DAPM_PGA("BST1", SND_SOC_NOPM,
2747 0, 0, NULL, 0),
2748 SND_SOC_DAPM_PGA("BST2", SND_SOC_NOPM,
2749 0, 0, NULL, 0),
2750 SND_SOC_DAPM_PGA("BST3", SND_SOC_NOPM,
2751 0, 0, NULL, 0),
2752 SND_SOC_DAPM_PGA("BST4", SND_SOC_NOPM,
2753 0, 0, NULL, 0),
2754 SND_SOC_DAPM_PGA("BST1 CBJ", SND_SOC_NOPM,
2755 0, 0, NULL, 0),
2756 SND_SOC_DAPM_SUPPLY("BST1 Power", RT5665_PWR_ANLG_2,
2757 RT5665_PWR_BST1_BIT, 0, NULL, 0),
2758 SND_SOC_DAPM_SUPPLY("BST2 Power", RT5665_PWR_ANLG_2,
2759 RT5665_PWR_BST2_BIT, 0, NULL, 0),
2760 SND_SOC_DAPM_SUPPLY("BST3 Power", RT5665_PWR_ANLG_2,
2761 RT5665_PWR_BST3_BIT, 0, NULL, 0),
2762 SND_SOC_DAPM_SUPPLY("BST4 Power", RT5665_PWR_ANLG_2,
2763 RT5665_PWR_BST4_BIT, 0, NULL, 0),
2764 SND_SOC_DAPM_SUPPLY("BST1P Power", RT5665_PWR_ANLG_2,
2765 RT5665_PWR_BST1_P_BIT, 0, NULL, 0),
2766 SND_SOC_DAPM_SUPPLY("BST2P Power", RT5665_PWR_ANLG_2,
2767 RT5665_PWR_BST2_P_BIT, 0, NULL, 0),
2768 SND_SOC_DAPM_SUPPLY("BST3P Power", RT5665_PWR_ANLG_2,
2769 RT5665_PWR_BST3_P_BIT, 0, NULL, 0),
2770 SND_SOC_DAPM_SUPPLY("BST4P Power", RT5665_PWR_ANLG_2,
2771 RT5665_PWR_BST4_P_BIT, 0, NULL, 0),
2772 SND_SOC_DAPM_SUPPLY("CBJ Power", RT5665_PWR_ANLG_3,
2773 RT5665_PWR_CBJ_BIT, 0, NULL, 0),
2774
2775
2776
2777 SND_SOC_DAPM_PGA("INL VOL", RT5665_PWR_VOL, RT5665_PWR_IN_L_BIT,
2778 0, NULL, 0),
2779 SND_SOC_DAPM_PGA("INR VOL", RT5665_PWR_VOL, RT5665_PWR_IN_R_BIT,
2780 0, NULL, 0),
2781
2782
2783 SND_SOC_DAPM_MIXER("RECMIX1L", SND_SOC_NOPM, 0, 0, rt5665_rec1_l_mix,
2784 ARRAY_SIZE(rt5665_rec1_l_mix)),
2785 SND_SOC_DAPM_MIXER("RECMIX1R", SND_SOC_NOPM, 0, 0, rt5665_rec1_r_mix,
2786 ARRAY_SIZE(rt5665_rec1_r_mix)),
2787 SND_SOC_DAPM_MIXER("RECMIX2L", SND_SOC_NOPM, 0, 0, rt5665_rec2_l_mix,
2788 ARRAY_SIZE(rt5665_rec2_l_mix)),
2789 SND_SOC_DAPM_MIXER("RECMIX2R", SND_SOC_NOPM, 0, 0, rt5665_rec2_r_mix,
2790 ARRAY_SIZE(rt5665_rec2_r_mix)),
2791 SND_SOC_DAPM_SUPPLY("RECMIX1L Power", RT5665_PWR_ANLG_2,
2792 RT5665_PWR_RM1_L_BIT, 0, NULL, 0),
2793 SND_SOC_DAPM_SUPPLY("RECMIX1R Power", RT5665_PWR_ANLG_2,
2794 RT5665_PWR_RM1_R_BIT, 0, NULL, 0),
2795 SND_SOC_DAPM_SUPPLY("RECMIX2L Power", RT5665_PWR_MIXER,
2796 RT5665_PWR_RM2_L_BIT, 0, NULL, 0),
2797 SND_SOC_DAPM_SUPPLY("RECMIX2R Power", RT5665_PWR_MIXER,
2798 RT5665_PWR_RM2_R_BIT, 0, NULL, 0),
2799
2800
2801 SND_SOC_DAPM_ADC("ADC1 L", NULL, SND_SOC_NOPM, 0, 0),
2802 SND_SOC_DAPM_ADC("ADC1 R", NULL, SND_SOC_NOPM, 0, 0),
2803 SND_SOC_DAPM_ADC("ADC2 L", NULL, SND_SOC_NOPM, 0, 0),
2804 SND_SOC_DAPM_ADC("ADC2 R", NULL, SND_SOC_NOPM, 0, 0),
2805
2806 SND_SOC_DAPM_SUPPLY("ADC1 L Power", RT5665_PWR_DIG_1,
2807 RT5665_PWR_ADC_L1_BIT, 0, NULL, 0),
2808 SND_SOC_DAPM_SUPPLY("ADC1 R Power", RT5665_PWR_DIG_1,
2809 RT5665_PWR_ADC_R1_BIT, 0, NULL, 0),
2810 SND_SOC_DAPM_SUPPLY("ADC2 L Power", RT5665_PWR_DIG_1,
2811 RT5665_PWR_ADC_L2_BIT, 0, NULL, 0),
2812 SND_SOC_DAPM_SUPPLY("ADC2 R Power", RT5665_PWR_DIG_1,
2813 RT5665_PWR_ADC_R2_BIT, 0, NULL, 0),
2814 SND_SOC_DAPM_SUPPLY("ADC1 clock", RT5665_CHOP_ADC,
2815 RT5665_CKGEN_ADC1_SFT, 0, NULL, 0),
2816 SND_SOC_DAPM_SUPPLY("ADC2 clock", RT5665_CHOP_ADC,
2817 RT5665_CKGEN_ADC2_SFT, 0, NULL, 0),
2818
2819
2820 SND_SOC_DAPM_MUX("Stereo1 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2821 &rt5665_sto1_dmic_mux),
2822 SND_SOC_DAPM_MUX("Stereo1 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2823 &rt5665_sto1_dmic_mux),
2824 SND_SOC_DAPM_MUX("Stereo1 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2825 &rt5665_sto1_adc1l_mux),
2826 SND_SOC_DAPM_MUX("Stereo1 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2827 &rt5665_sto1_adc1r_mux),
2828 SND_SOC_DAPM_MUX("Stereo1 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2829 &rt5665_sto1_adc2l_mux),
2830 SND_SOC_DAPM_MUX("Stereo1 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2831 &rt5665_sto1_adc2r_mux),
2832 SND_SOC_DAPM_MUX("Stereo1 ADC L Mux", SND_SOC_NOPM, 0, 0,
2833 &rt5665_sto1_adcl_mux),
2834 SND_SOC_DAPM_MUX("Stereo1 ADC R Mux", SND_SOC_NOPM, 0, 0,
2835 &rt5665_sto1_adcr_mux),
2836 SND_SOC_DAPM_MUX("Stereo1 DD L Mux", SND_SOC_NOPM, 0, 0,
2837 &rt5665_sto1_dd_l_mux),
2838 SND_SOC_DAPM_MUX("Stereo1 DD R Mux", SND_SOC_NOPM, 0, 0,
2839 &rt5665_sto1_dd_r_mux),
2840 SND_SOC_DAPM_MUX("Mono ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2841 &rt5665_mono_adc_l2_mux),
2842 SND_SOC_DAPM_MUX("Mono ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2843 &rt5665_mono_adc_r2_mux),
2844 SND_SOC_DAPM_MUX("Mono ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2845 &rt5665_mono_adc_l1_mux),
2846 SND_SOC_DAPM_MUX("Mono ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2847 &rt5665_mono_adc_r1_mux),
2848 SND_SOC_DAPM_MUX("Mono DMIC L Mux", SND_SOC_NOPM, 0, 0,
2849 &rt5665_mono_dmic_l_mux),
2850 SND_SOC_DAPM_MUX("Mono DMIC R Mux", SND_SOC_NOPM, 0, 0,
2851 &rt5665_mono_dmic_r_mux),
2852 SND_SOC_DAPM_MUX("Mono ADC L Mux", SND_SOC_NOPM, 0, 0,
2853 &rt5665_mono_adc_l_mux),
2854 SND_SOC_DAPM_MUX("Mono ADC R Mux", SND_SOC_NOPM, 0, 0,
2855 &rt5665_mono_adc_r_mux),
2856 SND_SOC_DAPM_MUX("Mono DD L Mux", SND_SOC_NOPM, 0, 0,
2857 &rt5665_mono_dd_l_mux),
2858 SND_SOC_DAPM_MUX("Mono DD R Mux", SND_SOC_NOPM, 0, 0,
2859 &rt5665_mono_dd_r_mux),
2860 SND_SOC_DAPM_MUX("Stereo2 DMIC L Mux", SND_SOC_NOPM, 0, 0,
2861 &rt5665_sto2_dmic_mux),
2862 SND_SOC_DAPM_MUX("Stereo2 DMIC R Mux", SND_SOC_NOPM, 0, 0,
2863 &rt5665_sto2_dmic_mux),
2864 SND_SOC_DAPM_MUX("Stereo2 ADC L1 Mux", SND_SOC_NOPM, 0, 0,
2865 &rt5665_sto2_adc1l_mux),
2866 SND_SOC_DAPM_MUX("Stereo2 ADC R1 Mux", SND_SOC_NOPM, 0, 0,
2867 &rt5665_sto2_adc1r_mux),
2868 SND_SOC_DAPM_MUX("Stereo2 ADC L2 Mux", SND_SOC_NOPM, 0, 0,
2869 &rt5665_sto2_adc2l_mux),
2870 SND_SOC_DAPM_MUX("Stereo2 ADC R2 Mux", SND_SOC_NOPM, 0, 0,
2871 &rt5665_sto2_adc2r_mux),
2872 SND_SOC_DAPM_MUX("Stereo2 ADC L Mux", SND_SOC_NOPM, 0, 0,
2873 &rt5665_sto2_adcl_mux),
2874 SND_SOC_DAPM_MUX("Stereo2 ADC R Mux", SND_SOC_NOPM, 0, 0,
2875 &rt5665_sto2_adcr_mux),
2876 SND_SOC_DAPM_MUX("Stereo2 DD L Mux", SND_SOC_NOPM, 0, 0,
2877 &rt5665_sto2_dd_l_mux),
2878 SND_SOC_DAPM_MUX("Stereo2 DD R Mux", SND_SOC_NOPM, 0, 0,
2879 &rt5665_sto2_dd_r_mux),
2880
2881 SND_SOC_DAPM_SUPPLY("ADC Stereo1 Filter", RT5665_PWR_DIG_2,
2882 RT5665_PWR_ADC_S1F_BIT, 0, NULL, 0),
2883 SND_SOC_DAPM_SUPPLY("ADC Stereo2 Filter", RT5665_PWR_DIG_2,
2884 RT5665_PWR_ADC_S2F_BIT, 0, NULL, 0),
2885 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXL", RT5665_STO1_ADC_DIG_VOL,
2886 RT5665_L_MUTE_SFT, 1, rt5665_sto1_adc_l_mix,
2887 ARRAY_SIZE(rt5665_sto1_adc_l_mix)),
2888 SND_SOC_DAPM_MIXER("Stereo1 ADC MIXR", RT5665_STO1_ADC_DIG_VOL,
2889 RT5665_R_MUTE_SFT, 1, rt5665_sto1_adc_r_mix,
2890 ARRAY_SIZE(rt5665_sto1_adc_r_mix)),
2891 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXL", RT5665_STO2_ADC_DIG_VOL,
2892 RT5665_L_MUTE_SFT, 1, rt5665_sto2_adc_l_mix,
2893 ARRAY_SIZE(rt5665_sto2_adc_l_mix)),
2894 SND_SOC_DAPM_MIXER("Stereo2 ADC MIXR", RT5665_STO2_ADC_DIG_VOL,
2895 RT5665_R_MUTE_SFT, 1, rt5665_sto2_adc_r_mix,
2896 ARRAY_SIZE(rt5665_sto2_adc_r_mix)),
2897 SND_SOC_DAPM_SUPPLY("ADC Mono Left Filter", RT5665_PWR_DIG_2,
2898 RT5665_PWR_ADC_MF_L_BIT, 0, NULL, 0),
2899 SND_SOC_DAPM_MIXER("Mono ADC MIXL", RT5665_MONO_ADC_DIG_VOL,
2900 RT5665_L_MUTE_SFT, 1, rt5665_mono_adc_l_mix,
2901 ARRAY_SIZE(rt5665_mono_adc_l_mix)),
2902 SND_SOC_DAPM_SUPPLY("ADC Mono Right Filter", RT5665_PWR_DIG_2,
2903 RT5665_PWR_ADC_MF_R_BIT, 0, NULL, 0),
2904 SND_SOC_DAPM_MIXER("Mono ADC MIXR", RT5665_MONO_ADC_DIG_VOL,
2905 RT5665_R_MUTE_SFT, 1, rt5665_mono_adc_r_mix,
2906 ARRAY_SIZE(rt5665_mono_adc_r_mix)),
2907
2908
2909 SND_SOC_DAPM_PGA("Stereo1 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2910 SND_SOC_DAPM_PGA("Stereo2 ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2911 SND_SOC_DAPM_PGA("Mono ADC MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
2912
2913
2914 SND_SOC_DAPM_SUPPLY("I2S1_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_1_BIT,
2915 0, NULL, 0),
2916 SND_SOC_DAPM_SUPPLY("I2S1_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S1_2_BIT,
2917 0, NULL, 0),
2918 SND_SOC_DAPM_SUPPLY("I2S2_1", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_1_BIT,
2919 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2920 SND_SOC_DAPM_POST_PMD),
2921 SND_SOC_DAPM_SUPPLY("I2S2_2", RT5665_PWR_DIG_1, RT5665_PWR_I2S2_2_BIT,
2922 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2923 SND_SOC_DAPM_POST_PMD),
2924 SND_SOC_DAPM_SUPPLY("I2S3", RT5665_PWR_DIG_1, RT5665_PWR_I2S3_BIT,
2925 0, rt5665_i2s_pin_event, SND_SOC_DAPM_PRE_PMU |
2926 SND_SOC_DAPM_POST_PMD),
2927 SND_SOC_DAPM_PGA("IF1 DAC1", SND_SOC_NOPM, 0, 0, NULL, 0),
2928 SND_SOC_DAPM_PGA("IF1 DAC2", SND_SOC_NOPM, 0, 0, NULL, 0),
2929 SND_SOC_DAPM_PGA("IF1 DAC3", SND_SOC_NOPM, 0, 0, NULL, 0),
2930 SND_SOC_DAPM_PGA("IF1 DAC1 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2931 SND_SOC_DAPM_PGA("IF1 DAC1 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2932 SND_SOC_DAPM_PGA("IF1 DAC2 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2933 SND_SOC_DAPM_PGA("IF1 DAC2 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2934 SND_SOC_DAPM_PGA("IF1 DAC3 L", SND_SOC_NOPM, 0, 0, NULL, 0),
2935 SND_SOC_DAPM_PGA("IF1 DAC3 R", SND_SOC_NOPM, 0, 0, NULL, 0),
2936
2937 SND_SOC_DAPM_PGA("IF2_1 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2938 SND_SOC_DAPM_PGA("IF2_2 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2939 SND_SOC_DAPM_PGA("IF2_1 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2940 SND_SOC_DAPM_PGA("IF2_1 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2941 SND_SOC_DAPM_PGA("IF2_2 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2942 SND_SOC_DAPM_PGA("IF2_2 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2943 SND_SOC_DAPM_PGA("IF2_1 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2944 SND_SOC_DAPM_PGA("IF2_2 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2945
2946 SND_SOC_DAPM_PGA("IF3 DAC", SND_SOC_NOPM, 0, 0, NULL, 0),
2947 SND_SOC_DAPM_PGA("IF3 DAC L", SND_SOC_NOPM, 0, 0, NULL, 0),
2948 SND_SOC_DAPM_PGA("IF3 DAC R", SND_SOC_NOPM, 0, 0, NULL, 0),
2949 SND_SOC_DAPM_PGA("IF3 ADC", SND_SOC_NOPM, 0, 0, NULL, 0),
2950
2951
2952 SND_SOC_DAPM_MUX("IF1_1_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2953 &rt5665_if1_1_adc1_mux),
2954 SND_SOC_DAPM_MUX("IF1_1_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2955 &rt5665_if1_1_adc2_mux),
2956 SND_SOC_DAPM_MUX("IF1_1_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2957 &rt5665_if1_1_adc3_mux),
2958 SND_SOC_DAPM_PGA("IF1_1_ADC4", SND_SOC_NOPM, 0, 0, NULL, 0),
2959 SND_SOC_DAPM_MUX("IF1_2_ADC1 Mux", SND_SOC_NOPM, 0, 0,
2960 &rt5665_if1_2_adc1_mux),
2961 SND_SOC_DAPM_MUX("IF1_2_ADC2 Mux", SND_SOC_NOPM, 0, 0,
2962 &rt5665_if1_2_adc2_mux),
2963 SND_SOC_DAPM_MUX("IF1_2_ADC3 Mux", SND_SOC_NOPM, 0, 0,
2964 &rt5665_if1_2_adc3_mux),
2965 SND_SOC_DAPM_MUX("IF1_2_ADC4 Mux", SND_SOC_NOPM, 0, 0,
2966 &rt5665_if1_2_adc4_mux),
2967 SND_SOC_DAPM_MUX("TDM1 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2968 &rt5665_tdm1_adc_mux),
2969 SND_SOC_DAPM_MUX("TDM1 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2970 &rt5665_tdm1_adc_mux),
2971 SND_SOC_DAPM_MUX("TDM1 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2972 &rt5665_tdm1_adc_mux),
2973 SND_SOC_DAPM_MUX("TDM1 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2974 &rt5665_tdm1_adc_mux),
2975 SND_SOC_DAPM_MUX("TDM2 slot 01 Data Mux", SND_SOC_NOPM, 0, 0,
2976 &rt5665_tdm2_adc_mux),
2977 SND_SOC_DAPM_MUX("TDM2 slot 23 Data Mux", SND_SOC_NOPM, 0, 0,
2978 &rt5665_tdm2_adc_mux),
2979 SND_SOC_DAPM_MUX("TDM2 slot 45 Data Mux", SND_SOC_NOPM, 0, 0,
2980 &rt5665_tdm2_adc_mux),
2981 SND_SOC_DAPM_MUX("TDM2 slot 67 Data Mux", SND_SOC_NOPM, 0, 0,
2982 &rt5665_tdm2_adc_mux),
2983 SND_SOC_DAPM_MUX("IF2_1 ADC Mux", SND_SOC_NOPM, 0, 0,
2984 &rt5665_if2_1_adc_in_mux),
2985 SND_SOC_DAPM_MUX("IF2_2 ADC Mux", SND_SOC_NOPM, 0, 0,
2986 &rt5665_if2_2_adc_in_mux),
2987 SND_SOC_DAPM_MUX("IF3 ADC Mux", SND_SOC_NOPM, 0, 0,
2988 &rt5665_if3_adc_in_mux),
2989 SND_SOC_DAPM_MUX("IF1_1 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2990 &rt5665_if1_1_01_adc_swap_mux),
2991 SND_SOC_DAPM_MUX("IF1_1 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2992 &rt5665_if1_1_01_adc_swap_mux),
2993 SND_SOC_DAPM_MUX("IF1_1 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2994 &rt5665_if1_1_23_adc_swap_mux),
2995 SND_SOC_DAPM_MUX("IF1_1 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2996 &rt5665_if1_1_23_adc_swap_mux),
2997 SND_SOC_DAPM_MUX("IF1_1 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
2998 &rt5665_if1_1_45_adc_swap_mux),
2999 SND_SOC_DAPM_MUX("IF1_1 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3000 &rt5665_if1_1_45_adc_swap_mux),
3001 SND_SOC_DAPM_MUX("IF1_1 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3002 &rt5665_if1_1_67_adc_swap_mux),
3003 SND_SOC_DAPM_MUX("IF1_1 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3004 &rt5665_if1_1_67_adc_swap_mux),
3005 SND_SOC_DAPM_MUX("IF1_2 0 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3006 &rt5665_if1_2_01_adc_swap_mux),
3007 SND_SOC_DAPM_MUX("IF1_2 1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3008 &rt5665_if1_2_01_adc_swap_mux),
3009 SND_SOC_DAPM_MUX("IF1_2 2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3010 &rt5665_if1_2_23_adc_swap_mux),
3011 SND_SOC_DAPM_MUX("IF1_2 3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3012 &rt5665_if1_2_23_adc_swap_mux),
3013 SND_SOC_DAPM_MUX("IF1_2 4 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3014 &rt5665_if1_2_45_adc_swap_mux),
3015 SND_SOC_DAPM_MUX("IF1_2 5 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3016 &rt5665_if1_2_45_adc_swap_mux),
3017 SND_SOC_DAPM_MUX("IF1_2 6 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3018 &rt5665_if1_2_67_adc_swap_mux),
3019 SND_SOC_DAPM_MUX("IF1_2 7 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3020 &rt5665_if1_2_67_adc_swap_mux),
3021 SND_SOC_DAPM_MUX("IF2_1 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3022 &rt5665_if2_1_dac_swap_mux),
3023 SND_SOC_DAPM_MUX("IF2_1 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3024 &rt5665_if2_1_adc_swap_mux),
3025 SND_SOC_DAPM_MUX("IF2_2 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3026 &rt5665_if2_2_dac_swap_mux),
3027 SND_SOC_DAPM_MUX("IF2_2 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3028 &rt5665_if2_2_adc_swap_mux),
3029 SND_SOC_DAPM_MUX("IF3 DAC Swap Mux", SND_SOC_NOPM, 0, 0,
3030 &rt5665_if3_dac_swap_mux),
3031 SND_SOC_DAPM_MUX("IF3 ADC Swap Mux", SND_SOC_NOPM, 0, 0,
3032 &rt5665_if3_adc_swap_mux),
3033
3034
3035 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 0", "AIF1_1 Capture",
3036 0, SND_SOC_NOPM, 0, 0),
3037 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 1", "AIF1_1 Capture",
3038 1, SND_SOC_NOPM, 0, 0),
3039 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 2", "AIF1_1 Capture",
3040 2, SND_SOC_NOPM, 0, 0),
3041 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 3", "AIF1_1 Capture",
3042 3, SND_SOC_NOPM, 0, 0),
3043 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 4", "AIF1_1 Capture",
3044 4, SND_SOC_NOPM, 0, 0),
3045 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 5", "AIF1_1 Capture",
3046 5, SND_SOC_NOPM, 0, 0),
3047 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 6", "AIF1_1 Capture",
3048 6, SND_SOC_NOPM, 0, 0),
3049 SND_SOC_DAPM_AIF_OUT("AIF1_1TX slot 7", "AIF1_1 Capture",
3050 7, SND_SOC_NOPM, 0, 0),
3051 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 0", "AIF1_2 Capture",
3052 0, SND_SOC_NOPM, 0, 0),
3053 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 1", "AIF1_2 Capture",
3054 1, SND_SOC_NOPM, 0, 0),
3055 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 2", "AIF1_2 Capture",
3056 2, SND_SOC_NOPM, 0, 0),
3057 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 3", "AIF1_2 Capture",
3058 3, SND_SOC_NOPM, 0, 0),
3059 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 4", "AIF1_2 Capture",
3060 4, SND_SOC_NOPM, 0, 0),
3061 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 5", "AIF1_2 Capture",
3062 5, SND_SOC_NOPM, 0, 0),
3063 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 6", "AIF1_2 Capture",
3064 6, SND_SOC_NOPM, 0, 0),
3065 SND_SOC_DAPM_AIF_OUT("AIF1_2TX slot 7", "AIF1_2 Capture",
3066 7, SND_SOC_NOPM, 0, 0),
3067 SND_SOC_DAPM_AIF_OUT("AIF2_1TX", "AIF2_1 Capture",
3068 0, SND_SOC_NOPM, 0, 0),
3069 SND_SOC_DAPM_AIF_OUT("AIF2_2TX", "AIF2_2 Capture",
3070 0, SND_SOC_NOPM, 0, 0),
3071 SND_SOC_DAPM_AIF_OUT("AIF3TX", "AIF3 Capture",
3072 0, SND_SOC_NOPM, 0, 0),
3073 SND_SOC_DAPM_AIF_IN("AIF1RX", "AIF1 Playback",
3074 0, SND_SOC_NOPM, 0, 0),
3075 SND_SOC_DAPM_AIF_IN("AIF2_1RX", "AIF2_1 Playback",
3076 0, SND_SOC_NOPM, 0, 0),
3077 SND_SOC_DAPM_AIF_IN("AIF2_2RX", "AIF2_2 Playback",
3078 0, SND_SOC_NOPM, 0, 0),
3079 SND_SOC_DAPM_AIF_IN("AIF3RX", "AIF3 Playback",
3080 0, SND_SOC_NOPM, 0, 0),
3081
3082
3083
3084 SND_SOC_DAPM_MIXER("DAC1 MIXL", SND_SOC_NOPM, 0, 0,
3085 rt5665_dac_l_mix, ARRAY_SIZE(rt5665_dac_l_mix)),
3086 SND_SOC_DAPM_MIXER("DAC1 MIXR", SND_SOC_NOPM, 0, 0,
3087 rt5665_dac_r_mix, ARRAY_SIZE(rt5665_dac_r_mix)),
3088
3089
3090 SND_SOC_DAPM_MUX("DAC L1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l1_mux),
3091 SND_SOC_DAPM_MUX("DAC R1 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r1_mux),
3092 SND_SOC_DAPM_MUX("DAC L2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l2_mux),
3093 SND_SOC_DAPM_MUX("DAC R2 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r2_mux),
3094 SND_SOC_DAPM_MUX("DAC L3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_l3_mux),
3095 SND_SOC_DAPM_MUX("DAC R3 Mux", SND_SOC_NOPM, 0, 0, &rt5665_dac_r3_mux),
3096
3097 SND_SOC_DAPM_MUX("DAC L1 Source", SND_SOC_NOPM, 0, 0,
3098 &rt5665_alg_dac_l1_mux),
3099 SND_SOC_DAPM_MUX("DAC R1 Source", SND_SOC_NOPM, 0, 0,
3100 &rt5665_alg_dac_r1_mux),
3101 SND_SOC_DAPM_MUX("DAC L2 Source", SND_SOC_NOPM, 0, 0,
3102 &rt5665_alg_dac_l2_mux),
3103 SND_SOC_DAPM_MUX("DAC R2 Source", SND_SOC_NOPM, 0, 0,
3104 &rt5665_alg_dac_r2_mux),
3105
3106
3107 SND_SOC_DAPM_SUPPLY("DAC Stereo1 Filter", RT5665_PWR_DIG_2,
3108 RT5665_PWR_DAC_S1F_BIT, 0, NULL, 0),
3109 SND_SOC_DAPM_SUPPLY("DAC Stereo2 Filter", RT5665_PWR_DIG_2,
3110 RT5665_PWR_DAC_S2F_BIT, 0, NULL, 0),
3111 SND_SOC_DAPM_SUPPLY("DAC Mono Left Filter", RT5665_PWR_DIG_2,
3112 RT5665_PWR_DAC_MF_L_BIT, 0, NULL, 0),
3113 SND_SOC_DAPM_SUPPLY("DAC Mono Right Filter", RT5665_PWR_DIG_2,
3114 RT5665_PWR_DAC_MF_R_BIT, 0, NULL, 0),
3115 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXL", SND_SOC_NOPM, 0, 0,
3116 rt5665_sto1_dac_l_mix, ARRAY_SIZE(rt5665_sto1_dac_l_mix)),
3117 SND_SOC_DAPM_MIXER("Stereo1 DAC MIXR", SND_SOC_NOPM, 0, 0,
3118 rt5665_sto1_dac_r_mix, ARRAY_SIZE(rt5665_sto1_dac_r_mix)),
3119 SND_SOC_DAPM_MIXER("Stereo2 DAC MIXL", SND_SOC_NOPM, 0, 0,
3120 rt5665_sto2_dac_l_mix, ARRAY_SIZE(rt5665_sto2_dac_l_mix)),
3121 SND_SOC_DAPM_MIXER("Stereo2 DAC MIXR", SND_SOC_NOPM, 0, 0,
3122 rt5665_sto2_dac_r_mix, ARRAY_SIZE(rt5665_sto2_dac_r_mix)),
3123 SND_SOC_DAPM_MIXER("Mono DAC MIXL", SND_SOC_NOPM, 0, 0,
3124 rt5665_mono_dac_l_mix, ARRAY_SIZE(rt5665_mono_dac_l_mix)),
3125 SND_SOC_DAPM_MIXER("Mono DAC MIXR", SND_SOC_NOPM, 0, 0,
3126 rt5665_mono_dac_r_mix, ARRAY_SIZE(rt5665_mono_dac_r_mix)),
3127 SND_SOC_DAPM_MUX("DAC MIXL", SND_SOC_NOPM, 0, 0,
3128 &rt5665_dig_dac_mixl_mux),
3129 SND_SOC_DAPM_MUX("DAC MIXR", SND_SOC_NOPM, 0, 0,
3130 &rt5665_dig_dac_mixr_mux),
3131
3132
3133 SND_SOC_DAPM_DAC("DAC L1", NULL, SND_SOC_NOPM, 0, 0),
3134 SND_SOC_DAPM_DAC("DAC R1", NULL, SND_SOC_NOPM, 0, 0),
3135
3136 SND_SOC_DAPM_SUPPLY("DAC L2 Power", RT5665_PWR_DIG_1,
3137 RT5665_PWR_DAC_L2_BIT, 0, NULL, 0),
3138 SND_SOC_DAPM_SUPPLY("DAC R2 Power", RT5665_PWR_DIG_1,
3139 RT5665_PWR_DAC_R2_BIT, 0, NULL, 0),
3140 SND_SOC_DAPM_DAC("DAC L2", NULL, SND_SOC_NOPM, 0, 0),
3141 SND_SOC_DAPM_DAC("DAC R2", NULL, SND_SOC_NOPM, 0, 0),
3142 SND_SOC_DAPM_PGA("DAC1 MIX", SND_SOC_NOPM, 0, 0, NULL, 0),
3143
3144 SND_SOC_DAPM_SUPPLY_S("DAC 1 Clock", 1, RT5665_CHOP_DAC,
3145 RT5665_CKGEN_DAC1_SFT, 0, NULL, 0),
3146 SND_SOC_DAPM_SUPPLY_S("DAC 2 Clock", 1, RT5665_CHOP_DAC,
3147 RT5665_CKGEN_DAC2_SFT, 0, NULL, 0),
3148
3149
3150 SND_SOC_DAPM_MIXER("MONOVOL MIX", RT5665_PWR_MIXER, RT5665_PWR_MM_BIT,
3151 0, rt5665_monovol_mix, ARRAY_SIZE(rt5665_monovol_mix)),
3152 SND_SOC_DAPM_MIXER("OUT MIXL", RT5665_PWR_MIXER, RT5665_PWR_OM_L_BIT,
3153 0, rt5665_out_l_mix, ARRAY_SIZE(rt5665_out_l_mix)),
3154 SND_SOC_DAPM_MIXER("OUT MIXR", RT5665_PWR_MIXER, RT5665_PWR_OM_R_BIT,
3155 0, rt5665_out_r_mix, ARRAY_SIZE(rt5665_out_r_mix)),
3156
3157
3158 SND_SOC_DAPM_SWITCH("MONOVOL", RT5665_PWR_VOL, RT5665_PWR_MV_BIT, 0,
3159 &monovol_switch),
3160 SND_SOC_DAPM_SWITCH("OUTVOL L", RT5665_PWR_VOL, RT5665_PWR_OV_L_BIT, 0,
3161 &outvol_l_switch),
3162 SND_SOC_DAPM_SWITCH("OUTVOL R", RT5665_PWR_VOL, RT5665_PWR_OV_R_BIT, 0,
3163 &outvol_r_switch),
3164
3165
3166 SND_SOC_DAPM_MIXER("Mono MIX", SND_SOC_NOPM, 0, 0, rt5665_mono_mix,
3167 ARRAY_SIZE(rt5665_mono_mix)),
3168 SND_SOC_DAPM_MIXER("LOUT L MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_l_mix,
3169 ARRAY_SIZE(rt5665_lout_l_mix)),
3170 SND_SOC_DAPM_MIXER("LOUT R MIX", SND_SOC_NOPM, 0, 0, rt5665_lout_r_mix,
3171 ARRAY_SIZE(rt5665_lout_r_mix)),
3172 SND_SOC_DAPM_PGA_S("Mono Amp", 1, RT5665_PWR_ANLG_1, RT5665_PWR_MA_BIT,
3173 0, rt5665_mono_event, SND_SOC_DAPM_POST_PMD |
3174 SND_SOC_DAPM_PRE_PMU),
3175 SND_SOC_DAPM_PGA_S("HP Amp", 1, SND_SOC_NOPM, 0, 0, rt5665_hp_event,
3176 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
3177 SND_SOC_DAPM_PGA_S("LOUT Amp", 1, RT5665_PWR_ANLG_1,
3178 RT5665_PWR_LM_BIT, 0, rt5665_lout_event,
3179 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD |
3180 SND_SOC_DAPM_POST_PMD | SND_SOC_DAPM_PRE_PMU),
3181
3182 SND_SOC_DAPM_SUPPLY("Charge Pump", SND_SOC_NOPM, 0, 0,
3183 rt5665_charge_pump_event, SND_SOC_DAPM_PRE_PMU |
3184 SND_SOC_DAPM_POST_PMD),
3185
3186 SND_SOC_DAPM_SWITCH("Mono Playback", SND_SOC_NOPM, 0, 0,
3187 &mono_switch),
3188 SND_SOC_DAPM_SWITCH("HPO Playback", SND_SOC_NOPM, 0, 0,
3189 &hpo_switch),
3190 SND_SOC_DAPM_SWITCH("LOUT L Playback", SND_SOC_NOPM, 0, 0,
3191 &lout_l_switch),
3192 SND_SOC_DAPM_SWITCH("LOUT R Playback", SND_SOC_NOPM, 0, 0,
3193 &lout_r_switch),
3194 SND_SOC_DAPM_SWITCH("PDM L Playback", SND_SOC_NOPM, 0, 0,
3195 &pdm_l_switch),
3196 SND_SOC_DAPM_SWITCH("PDM R Playback", SND_SOC_NOPM, 0, 0,
3197 &pdm_r_switch),
3198
3199
3200 SND_SOC_DAPM_SUPPLY("PDM Power", RT5665_PWR_DIG_2,
3201 RT5665_PWR_PDM1_BIT, 0, NULL, 0),
3202 SND_SOC_DAPM_MUX("PDM L Mux", SND_SOC_NOPM,
3203 0, 1, &rt5665_pdm_l_mux),
3204 SND_SOC_DAPM_MUX("PDM R Mux", SND_SOC_NOPM,
3205 0, 1, &rt5665_pdm_r_mux),
3206
3207
3208 SND_SOC_DAPM_SUPPLY("CLKDET SYS", RT5665_CLK_DET, RT5665_SYS_CLK_DET,
3209 0, NULL, 0),
3210 SND_SOC_DAPM_SUPPLY("CLKDET HP", RT5665_CLK_DET, RT5665_HP_CLK_DET,
3211 0, NULL, 0),
3212 SND_SOC_DAPM_SUPPLY("CLKDET MONO", RT5665_CLK_DET, RT5665_MONO_CLK_DET,
3213 0, NULL, 0),
3214 SND_SOC_DAPM_SUPPLY("CLKDET LOUT", RT5665_CLK_DET, RT5665_LOUT_CLK_DET,
3215 0, NULL, 0),
3216 SND_SOC_DAPM_SUPPLY("CLKDET", RT5665_CLK_DET, RT5665_POW_CLK_DET,
3217 0, NULL, 0),
3218
3219
3220 SND_SOC_DAPM_OUTPUT("HPOL"),
3221 SND_SOC_DAPM_OUTPUT("HPOR"),
3222 SND_SOC_DAPM_OUTPUT("LOUTL"),
3223 SND_SOC_DAPM_OUTPUT("LOUTR"),
3224 SND_SOC_DAPM_OUTPUT("MONOOUT"),
3225 SND_SOC_DAPM_OUTPUT("PDML"),
3226 SND_SOC_DAPM_OUTPUT("PDMR"),
3227};
3228
3229static const struct snd_soc_dapm_route rt5665_dapm_routes[] = {
3230
3231 {"ADC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
3232 {"ADC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
3233 {"ADC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
3234 {"ADC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
3235 {"DAC Stereo1 Filter", NULL, "PLL", is_sys_clk_from_pll},
3236 {"DAC Stereo2 Filter", NULL, "PLL", is_sys_clk_from_pll},
3237 {"DAC Mono Left Filter", NULL, "PLL", is_sys_clk_from_pll},
3238 {"DAC Mono Right Filter", NULL, "PLL", is_sys_clk_from_pll},
3239
3240
3241 {"ADC Stereo1 Filter", NULL, "ADC STO1 ASRC", is_using_asrc},
3242 {"ADC Stereo2 Filter", NULL, "ADC STO2 ASRC", is_using_asrc},
3243 {"ADC Mono Left Filter", NULL, "ADC Mono L ASRC", is_using_asrc},
3244 {"ADC Mono Right Filter", NULL, "ADC Mono R ASRC", is_using_asrc},
3245 {"DAC Mono Left Filter", NULL, "DAC Mono L ASRC", is_using_asrc},
3246 {"DAC Mono Right Filter", NULL, "DAC Mono R ASRC", is_using_asrc},
3247 {"DAC Stereo1 Filter", NULL, "DAC STO1 ASRC", is_using_asrc},
3248 {"DAC Stereo2 Filter", NULL, "DAC STO2 ASRC", is_using_asrc},
3249 {"I2S1 ASRC", NULL, "CLKDET"},
3250 {"I2S2 ASRC", NULL, "CLKDET"},
3251 {"I2S3 ASRC", NULL, "CLKDET"},
3252
3253
3254 {"Mic Det Power", NULL, "Vref2"},
3255 {"MICBIAS1", NULL, "Vref1"},
3256 {"MICBIAS1", NULL, "Vref2"},
3257 {"MICBIAS2", NULL, "Vref1"},
3258 {"MICBIAS2", NULL, "Vref2"},
3259 {"MICBIAS3", NULL, "Vref1"},
3260 {"MICBIAS3", NULL, "Vref2"},
3261
3262 {"Stereo1 DMIC L Mux", NULL, "DMIC STO1 ASRC"},
3263 {"Stereo1 DMIC R Mux", NULL, "DMIC STO1 ASRC"},
3264 {"Stereo2 DMIC L Mux", NULL, "DMIC STO2 ASRC"},
3265 {"Stereo2 DMIC R Mux", NULL, "DMIC STO2 ASRC"},
3266 {"Mono DMIC L Mux", NULL, "DMIC MONO L ASRC"},
3267 {"Mono DMIC R Mux", NULL, "DMIC MONO R ASRC"},
3268
3269 {"I2S1_1", NULL, "I2S1 ASRC"},
3270 {"I2S1_2", NULL, "I2S1 ASRC"},
3271 {"I2S2_1", NULL, "I2S2 ASRC"},
3272 {"I2S2_2", NULL, "I2S2 ASRC"},
3273 {"I2S3", NULL, "I2S3 ASRC"},
3274
3275 {"CLKDET SYS", NULL, "CLKDET"},
3276 {"CLKDET HP", NULL, "CLKDET"},
3277 {"CLKDET MONO", NULL, "CLKDET"},
3278 {"CLKDET LOUT", NULL, "CLKDET"},
3279
3280 {"IN1P", NULL, "LDO2"},
3281 {"IN2P", NULL, "LDO2"},
3282 {"IN3P", NULL, "LDO2"},
3283 {"IN4P", NULL, "LDO2"},
3284
3285 {"DMIC1", NULL, "DMIC L1"},
3286 {"DMIC1", NULL, "DMIC R1"},
3287 {"DMIC2", NULL, "DMIC L2"},
3288 {"DMIC2", NULL, "DMIC R2"},
3289
3290 {"BST1", NULL, "IN1P"},
3291 {"BST1", NULL, "IN1N"},
3292 {"BST1", NULL, "BST1 Power"},
3293 {"BST1", NULL, "BST1P Power"},
3294 {"BST2", NULL, "IN2P"},
3295 {"BST2", NULL, "IN2N"},
3296 {"BST2", NULL, "BST2 Power"},
3297 {"BST2", NULL, "BST2P Power"},
3298 {"BST3", NULL, "IN3P"},
3299 {"BST3", NULL, "IN3N"},
3300 {"BST3", NULL, "BST3 Power"},
3301 {"BST3", NULL, "BST3P Power"},
3302 {"BST4", NULL, "IN4P"},
3303 {"BST4", NULL, "IN4N"},
3304 {"BST4", NULL, "BST4 Power"},
3305 {"BST4", NULL, "BST4P Power"},
3306 {"BST1 CBJ", NULL, "IN1P"},
3307 {"BST1 CBJ", NULL, "IN1N"},
3308 {"BST1 CBJ", NULL, "CBJ Power"},
3309 {"CBJ Power", NULL, "Vref2"},
3310
3311 {"INL VOL", NULL, "IN3P"},
3312 {"INR VOL", NULL, "IN3N"},
3313
3314 {"RECMIX1L", "CBJ Switch", "BST1 CBJ"},
3315 {"RECMIX1L", "INL Switch", "INL VOL"},
3316 {"RECMIX1L", "INR Switch", "INR VOL"},
3317 {"RECMIX1L", "BST4 Switch", "BST4"},
3318 {"RECMIX1L", "BST3 Switch", "BST3"},
3319 {"RECMIX1L", "BST2 Switch", "BST2"},
3320 {"RECMIX1L", "BST1 Switch", "BST1"},
3321 {"RECMIX1L", NULL, "RECMIX1L Power"},
3322
3323 {"RECMIX1R", "MONOVOL Switch", "MONOVOL"},
3324 {"RECMIX1R", "INR Switch", "INR VOL"},
3325 {"RECMIX1R", "BST4 Switch", "BST4"},
3326 {"RECMIX1R", "BST3 Switch", "BST3"},
3327 {"RECMIX1R", "BST2 Switch", "BST2"},
3328 {"RECMIX1R", "BST1 Switch", "BST1"},
3329 {"RECMIX1R", NULL, "RECMIX1R Power"},
3330
3331 {"RECMIX2L", "CBJ Switch", "BST1 CBJ"},
3332 {"RECMIX2L", "INL Switch", "INL VOL"},
3333 {"RECMIX2L", "INR Switch", "INR VOL"},
3334 {"RECMIX2L", "BST4 Switch", "BST4"},
3335 {"RECMIX2L", "BST3 Switch", "BST3"},
3336 {"RECMIX2L", "BST2 Switch", "BST2"},
3337 {"RECMIX2L", "BST1 Switch", "BST1"},
3338 {"RECMIX2L", NULL, "RECMIX2L Power"},
3339
3340 {"RECMIX2R", "MONOVOL Switch", "MONOVOL"},
3341 {"RECMIX2R", "INL Switch", "INL VOL"},
3342 {"RECMIX2R", "INR Switch", "INR VOL"},
3343 {"RECMIX2R", "BST4 Switch", "BST4"},
3344 {"RECMIX2R", "BST3 Switch", "BST3"},
3345 {"RECMIX2R", "BST2 Switch", "BST2"},
3346 {"RECMIX2R", "BST1 Switch", "BST1"},
3347 {"RECMIX2R", NULL, "RECMIX2R Power"},
3348
3349 {"ADC1 L", NULL, "RECMIX1L"},
3350 {"ADC1 L", NULL, "ADC1 L Power"},
3351 {"ADC1 L", NULL, "ADC1 clock"},
3352 {"ADC1 R", NULL, "RECMIX1R"},
3353 {"ADC1 R", NULL, "ADC1 R Power"},
3354 {"ADC1 R", NULL, "ADC1 clock"},
3355
3356 {"ADC2 L", NULL, "RECMIX2L"},
3357 {"ADC2 L", NULL, "ADC2 L Power"},
3358 {"ADC2 L", NULL, "ADC2 clock"},
3359 {"ADC2 R", NULL, "RECMIX2R"},
3360 {"ADC2 R", NULL, "ADC2 R Power"},
3361 {"ADC2 R", NULL, "ADC2 clock"},
3362
3363 {"DMIC L1", NULL, "DMIC CLK"},
3364 {"DMIC L1", NULL, "DMIC1 Power"},
3365 {"DMIC R1", NULL, "DMIC CLK"},
3366 {"DMIC R1", NULL, "DMIC1 Power"},
3367 {"DMIC L2", NULL, "DMIC CLK"},
3368 {"DMIC L2", NULL, "DMIC2 Power"},
3369 {"DMIC R2", NULL, "DMIC CLK"},
3370 {"DMIC R2", NULL, "DMIC2 Power"},
3371
3372 {"Stereo1 DMIC L Mux", "DMIC1", "DMIC L1"},
3373 {"Stereo1 DMIC L Mux", "DMIC2", "DMIC L2"},
3374
3375 {"Stereo1 DMIC R Mux", "DMIC1", "DMIC R1"},
3376 {"Stereo1 DMIC R Mux", "DMIC2", "DMIC R2"},
3377
3378 {"Mono DMIC L Mux", "DMIC1 L", "DMIC L1"},
3379 {"Mono DMIC L Mux", "DMIC2 L", "DMIC L2"},
3380
3381 {"Mono DMIC R Mux", "DMIC1 R", "DMIC R1"},
3382 {"Mono DMIC R Mux", "DMIC2 R", "DMIC R2"},
3383
3384 {"Stereo2 DMIC L Mux", "DMIC1", "DMIC L1"},
3385 {"Stereo2 DMIC L Mux", "DMIC2", "DMIC L2"},
3386
3387 {"Stereo2 DMIC R Mux", "DMIC1", "DMIC R1"},
3388 {"Stereo2 DMIC R Mux", "DMIC2", "DMIC R2"},
3389
3390 {"Stereo1 ADC L Mux", "ADC1 L", "ADC1 L"},
3391 {"Stereo1 ADC L Mux", "ADC1 R", "ADC1 R"},
3392 {"Stereo1 ADC L Mux", "ADC2 L", "ADC2 L"},
3393 {"Stereo1 ADC L Mux", "ADC2 R", "ADC2 R"},
3394 {"Stereo1 ADC R Mux", "ADC1 L", "ADC1 L"},
3395 {"Stereo1 ADC R Mux", "ADC1 R", "ADC1 R"},
3396 {"Stereo1 ADC R Mux", "ADC2 L", "ADC2 L"},
3397 {"Stereo1 ADC R Mux", "ADC2 R", "ADC2 R"},
3398
3399 {"Stereo1 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3400 {"Stereo1 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3401
3402 {"Stereo1 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3403 {"Stereo1 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3404
3405 {"Stereo1 ADC L1 Mux", "ADC", "Stereo1 ADC L Mux"},
3406 {"Stereo1 ADC L1 Mux", "DD Mux", "Stereo1 DD L Mux"},
3407 {"Stereo1 ADC L2 Mux", "DMIC", "Stereo1 DMIC L Mux"},
3408 {"Stereo1 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3409
3410 {"Stereo1 ADC R1 Mux", "ADC", "Stereo1 ADC R Mux"},
3411 {"Stereo1 ADC R1 Mux", "DD Mux", "Stereo1 DD R Mux"},
3412 {"Stereo1 ADC R2 Mux", "DMIC", "Stereo1 DMIC R Mux"},
3413 {"Stereo1 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3414
3415 {"Mono ADC L Mux", "ADC1 L", "ADC1 L"},
3416 {"Mono ADC L Mux", "ADC1 R", "ADC1 R"},
3417 {"Mono ADC L Mux", "ADC2 L", "ADC2 L"},
3418 {"Mono ADC L Mux", "ADC2 R", "ADC2 R"},
3419
3420 {"Mono ADC R Mux", "ADC1 L", "ADC1 L"},
3421 {"Mono ADC R Mux", "ADC1 R", "ADC1 R"},
3422 {"Mono ADC R Mux", "ADC2 L", "ADC2 L"},
3423 {"Mono ADC R Mux", "ADC2 R", "ADC2 R"},
3424
3425 {"Mono DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3426 {"Mono DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3427
3428 {"Mono DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3429 {"Mono DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3430
3431 {"Mono ADC L2 Mux", "DMIC", "Mono DMIC L Mux"},
3432 {"Mono ADC L2 Mux", "DAC MIXL", "DAC MIXL"},
3433 {"Mono ADC L1 Mux", "DD Mux", "Mono DD L Mux"},
3434 {"Mono ADC L1 Mux", "ADC", "Mono ADC L Mux"},
3435
3436 {"Mono ADC R1 Mux", "DD Mux", "Mono DD R Mux"},
3437 {"Mono ADC R1 Mux", "ADC", "Mono ADC R Mux"},
3438 {"Mono ADC R2 Mux", "DMIC", "Mono DMIC R Mux"},
3439 {"Mono ADC R2 Mux", "DAC MIXR", "DAC MIXR"},
3440
3441 {"Stereo2 ADC L Mux", "ADC1 L", "ADC1 L"},
3442 {"Stereo2 ADC L Mux", "ADC2 L", "ADC2 L"},
3443 {"Stereo2 ADC L Mux", "ADC1 R", "ADC1 R"},
3444 {"Stereo2 ADC R Mux", "ADC1 L", "ADC1 L"},
3445 {"Stereo2 ADC R Mux", "ADC2 L", "ADC2 L"},
3446 {"Stereo2 ADC R Mux", "ADC1 R", "ADC1 R"},
3447
3448 {"Stereo2 DD L Mux", "STO2 DAC", "Stereo2 DAC MIXL"},
3449 {"Stereo2 DD L Mux", "MONO DAC", "Mono DAC MIXL"},
3450
3451 {"Stereo2 DD R Mux", "STO2 DAC", "Stereo2 DAC MIXR"},
3452 {"Stereo2 DD R Mux", "MONO DAC", "Mono DAC MIXR"},
3453
3454 {"Stereo2 ADC L1 Mux", "ADC", "Stereo2 ADC L Mux"},
3455 {"Stereo2 ADC L1 Mux", "DD Mux", "Stereo2 DD L Mux"},
3456 {"Stereo2 ADC L2 Mux", "DMIC", "Stereo2 DMIC L Mux"},
3457 {"Stereo2 ADC L2 Mux", "DAC MIX", "DAC MIXL"},
3458
3459 {"Stereo2 ADC R1 Mux", "ADC", "Stereo2 ADC R Mux"},
3460 {"Stereo2 ADC R1 Mux", "DD Mux", "Stereo2 DD R Mux"},
3461 {"Stereo2 ADC R2 Mux", "DMIC", "Stereo2 DMIC R Mux"},
3462 {"Stereo2 ADC R2 Mux", "DAC MIX", "DAC MIXR"},
3463
3464 {"Stereo1 ADC MIXL", "ADC1 Switch", "Stereo1 ADC L1 Mux"},
3465 {"Stereo1 ADC MIXL", "ADC2 Switch", "Stereo1 ADC L2 Mux"},
3466 {"Stereo1 ADC MIXL", NULL, "ADC Stereo1 Filter"},
3467
3468 {"Stereo1 ADC MIXR", "ADC1 Switch", "Stereo1 ADC R1 Mux"},
3469 {"Stereo1 ADC MIXR", "ADC2 Switch", "Stereo1 ADC R2 Mux"},
3470 {"Stereo1 ADC MIXR", NULL, "ADC Stereo1 Filter"},
3471
3472 {"Mono ADC MIXL", "ADC1 Switch", "Mono ADC L1 Mux"},
3473 {"Mono ADC MIXL", "ADC2 Switch", "Mono ADC L2 Mux"},
3474 {"Mono ADC MIXL", NULL, "ADC Mono Left Filter"},
3475
3476 {"Mono ADC MIXR", "ADC1 Switch", "Mono ADC R1 Mux"},
3477 {"Mono ADC MIXR", "ADC2 Switch", "Mono ADC R2 Mux"},
3478 {"Mono ADC MIXR", NULL, "ADC Mono Right Filter"},
3479
3480 {"Stereo2 ADC MIXL", "ADC1 Switch", "Stereo2 ADC L1 Mux"},
3481 {"Stereo2 ADC MIXL", "ADC2 Switch", "Stereo2 ADC L2 Mux"},
3482 {"Stereo2 ADC MIXL", NULL, "ADC Stereo2 Filter"},
3483
3484 {"Stereo2 ADC MIXR", "ADC1 Switch", "Stereo2 ADC R1 Mux"},
3485 {"Stereo2 ADC MIXR", "ADC2 Switch", "Stereo2 ADC R2 Mux"},
3486 {"Stereo2 ADC MIXR", NULL, "ADC Stereo2 Filter"},
3487
3488 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXL"},
3489 {"Stereo1 ADC MIX", NULL, "Stereo1 ADC MIXR"},
3490 {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXL"},
3491 {"Stereo2 ADC MIX", NULL, "Stereo2 ADC MIXR"},
3492 {"Mono ADC MIX", NULL, "Mono ADC MIXL"},
3493 {"Mono ADC MIX", NULL, "Mono ADC MIXR"},
3494
3495 {"IF1_1_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3496 {"IF1_1_ADC1 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3497 {"IF1_1_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3498 {"IF1_1_ADC2 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3499 {"IF1_1_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3500 {"IF1_1_ADC3 Mux", "IF3 DAC", "IF3 DAC"},
3501 {"IF1_1_ADC4", NULL, "DAC1 MIX"},
3502
3503 {"IF1_2_ADC1 Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3504 {"IF1_2_ADC1 Mux", "IF1 DAC", "IF1 DAC1"},
3505 {"IF1_2_ADC2 Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3506 {"IF1_2_ADC2 Mux", "IF2_1 DAC", "IF2_1 DAC"},
3507 {"IF1_2_ADC3 Mux", "MONO ADC", "Mono ADC MIX"},
3508 {"IF1_2_ADC3 Mux", "IF2_2 DAC", "IF2_2 DAC"},
3509 {"IF1_2_ADC4 Mux", "DAC1", "DAC1 MIX"},
3510 {"IF1_2_ADC4 Mux", "IF3 DAC", "IF3 DAC"},
3511
3512 {"TDM1 slot 01 Data Mux", "1234", "IF1_1_ADC1 Mux"},
3513 {"TDM1 slot 01 Data Mux", "1243", "IF1_1_ADC1 Mux"},
3514 {"TDM1 slot 01 Data Mux", "1324", "IF1_1_ADC1 Mux"},
3515 {"TDM1 slot 01 Data Mux", "1342", "IF1_1_ADC1 Mux"},
3516 {"TDM1 slot 01 Data Mux", "1432", "IF1_1_ADC1 Mux"},
3517 {"TDM1 slot 01 Data Mux", "1423", "IF1_1_ADC1 Mux"},
3518 {"TDM1 slot 01 Data Mux", "2134", "IF1_1_ADC2 Mux"},
3519 {"TDM1 slot 01 Data Mux", "2143", "IF1_1_ADC2 Mux"},
3520 {"TDM1 slot 01 Data Mux", "2314", "IF1_1_ADC2 Mux"},
3521 {"TDM1 slot 01 Data Mux", "2341", "IF1_1_ADC2 Mux"},
3522 {"TDM1 slot 01 Data Mux", "2431", "IF1_1_ADC2 Mux"},
3523 {"TDM1 slot 01 Data Mux", "2413", "IF1_1_ADC2 Mux"},
3524 {"TDM1 slot 01 Data Mux", "3124", "IF1_1_ADC3 Mux"},
3525 {"TDM1 slot 01 Data Mux", "3142", "IF1_1_ADC3 Mux"},
3526 {"TDM1 slot 01 Data Mux", "3214", "IF1_1_ADC3 Mux"},
3527 {"TDM1 slot 01 Data Mux", "3241", "IF1_1_ADC3 Mux"},
3528 {"TDM1 slot 01 Data Mux", "3412", "IF1_1_ADC3 Mux"},
3529 {"TDM1 slot 01 Data Mux", "3421", "IF1_1_ADC3 Mux"},
3530 {"TDM1 slot 01 Data Mux", "4123", "IF1_1_ADC4"},
3531 {"TDM1 slot 01 Data Mux", "4132", "IF1_1_ADC4"},
3532 {"TDM1 slot 01 Data Mux", "4213", "IF1_1_ADC4"},
3533 {"TDM1 slot 01 Data Mux", "4231", "IF1_1_ADC4"},
3534 {"TDM1 slot 01 Data Mux", "4312", "IF1_1_ADC4"},
3535 {"TDM1 slot 01 Data Mux", "4321", "IF1_1_ADC4"},
3536 {"TDM1 slot 01 Data Mux", NULL, "I2S1_1"},
3537
3538 {"TDM1 slot 23 Data Mux", "1234", "IF1_1_ADC2 Mux"},
3539 {"TDM1 slot 23 Data Mux", "1243", "IF1_1_ADC2 Mux"},
3540 {"TDM1 slot 23 Data Mux", "1324", "IF1_1_ADC3 Mux"},
3541 {"TDM1 slot 23 Data Mux", "1342", "IF1_1_ADC3 Mux"},
3542 {"TDM1 slot 23 Data Mux", "1432", "IF1_1_ADC4"},
3543 {"TDM1 slot 23 Data Mux", "1423", "IF1_1_ADC4"},
3544 {"TDM1 slot 23 Data Mux", "2134", "IF1_1_ADC1 Mux"},
3545 {"TDM1 slot 23 Data Mux", "2143", "IF1_1_ADC1 Mux"},
3546 {"TDM1 slot 23 Data Mux", "2314", "IF1_1_ADC3 Mux"},
3547 {"TDM1 slot 23 Data Mux", "2341", "IF1_1_ADC3 Mux"},
3548 {"TDM1 slot 23 Data Mux", "2431", "IF1_1_ADC4"},
3549 {"TDM1 slot 23 Data Mux", "2413", "IF1_1_ADC4"},
3550 {"TDM1 slot 23 Data Mux", "3124", "IF1_1_ADC1 Mux"},
3551 {"TDM1 slot 23 Data Mux", "3142", "IF1_1_ADC1 Mux"},
3552 {"TDM1 slot 23 Data Mux", "3214", "IF1_1_ADC2 Mux"},
3553 {"TDM1 slot 23 Data Mux", "3241", "IF1_1_ADC2 Mux"},
3554 {"TDM1 slot 23 Data Mux", "3412", "IF1_1_ADC4"},
3555 {"TDM1 slot 23 Data Mux", "3421", "IF1_1_ADC4"},
3556 {"TDM1 slot 23 Data Mux", "4123", "IF1_1_ADC1 Mux"},
3557 {"TDM1 slot 23 Data Mux", "4132", "IF1_1_ADC1 Mux"},
3558 {"TDM1 slot 23 Data Mux", "4213", "IF1_1_ADC2 Mux"},
3559 {"TDM1 slot 23 Data Mux", "4231", "IF1_1_ADC2 Mux"},
3560 {"TDM1 slot 23 Data Mux", "4312", "IF1_1_ADC3 Mux"},
3561 {"TDM1 slot 23 Data Mux", "4321", "IF1_1_ADC3 Mux"},
3562 {"TDM1 slot 23 Data Mux", NULL, "I2S1_1"},
3563
3564 {"TDM1 slot 45 Data Mux", "1234", "IF1_1_ADC3 Mux"},
3565 {"TDM1 slot 45 Data Mux", "1243", "IF1_1_ADC4"},
3566 {"TDM1 slot 45 Data Mux", "1324", "IF1_1_ADC2 Mux"},
3567 {"TDM1 slot 45 Data Mux", "1342", "IF1_1_ADC4"},
3568 {"TDM1 slot 45 Data Mux", "1432", "IF1_1_ADC3 Mux"},
3569 {"TDM1 slot 45 Data Mux", "1423", "IF1_1_ADC2 Mux"},
3570 {"TDM1 slot 45 Data Mux", "2134", "IF1_1_ADC3 Mux"},
3571 {"TDM1 slot 45 Data Mux", "2143", "IF1_1_ADC4"},
3572 {"TDM1 slot 45 Data Mux", "2314", "IF1_1_ADC1 Mux"},
3573 {"TDM1 slot 45 Data Mux", "2341", "IF1_1_ADC4"},
3574 {"TDM1 slot 45 Data Mux", "2431", "IF1_1_ADC3 Mux"},
3575 {"TDM1 slot 45 Data Mux", "2413", "IF1_1_ADC1 Mux"},
3576 {"TDM1 slot 45 Data Mux", "3124", "IF1_1_ADC2 Mux"},
3577 {"TDM1 slot 45 Data Mux", "3142", "IF1_1_ADC4"},
3578 {"TDM1 slot 45 Data Mux", "3214", "IF1_1_ADC1 Mux"},
3579 {"TDM1 slot 45 Data Mux", "3241", "IF1_1_ADC4"},
3580 {"TDM1 slot 45 Data Mux", "3412", "IF1_1_ADC1 Mux"},
3581 {"TDM1 slot 45 Data Mux", "3421", "IF1_1_ADC2 Mux"},
3582 {"TDM1 slot 45 Data Mux", "4123", "IF1_1_ADC2 Mux"},
3583 {"TDM1 slot 45 Data Mux", "4132", "IF1_1_ADC3 Mux"},
3584 {"TDM1 slot 45 Data Mux", "4213", "IF1_1_ADC1 Mux"},
3585 {"TDM1 slot 45 Data Mux", "4231", "IF1_1_ADC3 Mux"},
3586 {"TDM1 slot 45 Data Mux", "4312", "IF1_1_ADC1 Mux"},
3587 {"TDM1 slot 45 Data Mux", "4321", "IF1_1_ADC2 Mux"},
3588 {"TDM1 slot 45 Data Mux", NULL, "I2S1_1"},
3589
3590 {"TDM1 slot 67 Data Mux", "1234", "IF1_1_ADC4"},
3591 {"TDM1 slot 67 Data Mux", "1243", "IF1_1_ADC3 Mux"},
3592 {"TDM1 slot 67 Data Mux", "1324", "IF1_1_ADC4"},
3593 {"TDM1 slot 67 Data Mux", "1342", "IF1_1_ADC2 Mux"},
3594 {"TDM1 slot 67 Data Mux", "1432", "IF1_1_ADC2 Mux"},
3595 {"TDM1 slot 67 Data Mux", "1423", "IF1_1_ADC3 Mux"},
3596 {"TDM1 slot 67 Data Mux", "2134", "IF1_1_ADC4"},
3597 {"TDM1 slot 67 Data Mux", "2143", "IF1_1_ADC3 Mux"},
3598 {"TDM1 slot 67 Data Mux", "2314", "IF1_1_ADC4"},
3599 {"TDM1 slot 67 Data Mux", "2341", "IF1_1_ADC1 Mux"},
3600 {"TDM1 slot 67 Data Mux", "2431", "IF1_1_ADC1 Mux"},
3601 {"TDM1 slot 67 Data Mux", "2413", "IF1_1_ADC3 Mux"},
3602 {"TDM1 slot 67 Data Mux", "3124", "IF1_1_ADC4"},
3603 {"TDM1 slot 67 Data Mux", "3142", "IF1_1_ADC2 Mux"},
3604 {"TDM1 slot 67 Data Mux", "3214", "IF1_1_ADC4"},
3605 {"TDM1 slot 67 Data Mux", "3241", "IF1_1_ADC1 Mux"},
3606 {"TDM1 slot 67 Data Mux", "3412", "IF1_1_ADC2 Mux"},
3607 {"TDM1 slot 67 Data Mux", "3421", "IF1_1_ADC1 Mux"},
3608 {"TDM1 slot 67 Data Mux", "4123", "IF1_1_ADC3 Mux"},
3609 {"TDM1 slot 67 Data Mux", "4132", "IF1_1_ADC2 Mux"},
3610 {"TDM1 slot 67 Data Mux", "4213", "IF1_1_ADC3 Mux"},
3611 {"TDM1 slot 67 Data Mux", "4231", "IF1_1_ADC1 Mux"},
3612 {"TDM1 slot 67 Data Mux", "4312", "IF1_1_ADC2 Mux"},
3613 {"TDM1 slot 67 Data Mux", "4321", "IF1_1_ADC1 Mux"},
3614 {"TDM1 slot 67 Data Mux", NULL, "I2S1_1"},
3615
3616
3617 {"TDM2 slot 01 Data Mux", "1234", "IF1_2_ADC1 Mux"},
3618 {"TDM2 slot 01 Data Mux", "1243", "IF1_2_ADC1 Mux"},
3619 {"TDM2 slot 01 Data Mux", "1324", "IF1_2_ADC1 Mux"},
3620 {"TDM2 slot 01 Data Mux", "1342", "IF1_2_ADC1 Mux"},
3621 {"TDM2 slot 01 Data Mux", "1432", "IF1_2_ADC1 Mux"},
3622 {"TDM2 slot 01 Data Mux", "1423", "IF1_2_ADC1 Mux"},
3623 {"TDM2 slot 01 Data Mux", "2134", "IF1_2_ADC2 Mux"},
3624 {"TDM2 slot 01 Data Mux", "2143", "IF1_2_ADC2 Mux"},
3625 {"TDM2 slot 01 Data Mux", "2314", "IF1_2_ADC2 Mux"},
3626 {"TDM2 slot 01 Data Mux", "2341", "IF1_2_ADC2 Mux"},
3627 {"TDM2 slot 01 Data Mux", "2431", "IF1_2_ADC2 Mux"},
3628 {"TDM2 slot 01 Data Mux", "2413", "IF1_2_ADC2 Mux"},
3629 {"TDM2 slot 01 Data Mux", "3124", "IF1_2_ADC3 Mux"},
3630 {"TDM2 slot 01 Data Mux", "3142", "IF1_2_ADC3 Mux"},
3631 {"TDM2 slot 01 Data Mux", "3214", "IF1_2_ADC3 Mux"},
3632 {"TDM2 slot 01 Data Mux", "3241", "IF1_2_ADC3 Mux"},
3633 {"TDM2 slot 01 Data Mux", "3412", "IF1_2_ADC3 Mux"},
3634 {"TDM2 slot 01 Data Mux", "3421", "IF1_2_ADC3 Mux"},
3635 {"TDM2 slot 01 Data Mux", "4123", "IF1_2_ADC4 Mux"},
3636 {"TDM2 slot 01 Data Mux", "4132", "IF1_2_ADC4 Mux"},
3637 {"TDM2 slot 01 Data Mux", "4213", "IF1_2_ADC4 Mux"},
3638 {"TDM2 slot 01 Data Mux", "4231", "IF1_2_ADC4 Mux"},
3639 {"TDM2 slot 01 Data Mux", "4312", "IF1_2_ADC4 Mux"},
3640 {"TDM2 slot 01 Data Mux", "4321", "IF1_2_ADC4 Mux"},
3641 {"TDM2 slot 01 Data Mux", NULL, "I2S1_2"},
3642
3643 {"TDM2 slot 23 Data Mux", "1234", "IF1_2_ADC2 Mux"},
3644 {"TDM2 slot 23 Data Mux", "1243", "IF1_2_ADC2 Mux"},
3645 {"TDM2 slot 23 Data Mux", "1324", "IF1_2_ADC3 Mux"},
3646 {"TDM2 slot 23 Data Mux", "1342", "IF1_2_ADC3 Mux"},
3647 {"TDM2 slot 23 Data Mux", "1432", "IF1_2_ADC4 Mux"},
3648 {"TDM2 slot 23 Data Mux", "1423", "IF1_2_ADC4 Mux"},
3649 {"TDM2 slot 23 Data Mux", "2134", "IF1_2_ADC1 Mux"},
3650 {"TDM2 slot 23 Data Mux", "2143", "IF1_2_ADC1 Mux"},
3651 {"TDM2 slot 23 Data Mux", "2314", "IF1_2_ADC3 Mux"},
3652 {"TDM2 slot 23 Data Mux", "2341", "IF1_2_ADC3 Mux"},
3653 {"TDM2 slot 23 Data Mux", "2431", "IF1_2_ADC4 Mux"},
3654 {"TDM2 slot 23 Data Mux", "2413", "IF1_2_ADC4 Mux"},
3655 {"TDM2 slot 23 Data Mux", "3124", "IF1_2_ADC1 Mux"},
3656 {"TDM2 slot 23 Data Mux", "3142", "IF1_2_ADC1 Mux"},
3657 {"TDM2 slot 23 Data Mux", "3214", "IF1_2_ADC2 Mux"},
3658 {"TDM2 slot 23 Data Mux", "3241", "IF1_2_ADC2 Mux"},
3659 {"TDM2 slot 23 Data Mux", "3412", "IF1_2_ADC4 Mux"},
3660 {"TDM2 slot 23 Data Mux", "3421", "IF1_2_ADC4 Mux"},
3661 {"TDM2 slot 23 Data Mux", "4123", "IF1_2_ADC1 Mux"},
3662 {"TDM2 slot 23 Data Mux", "4132", "IF1_2_ADC1 Mux"},
3663 {"TDM2 slot 23 Data Mux", "4213", "IF1_2_ADC2 Mux"},
3664 {"TDM2 slot 23 Data Mux", "4231", "IF1_2_ADC2 Mux"},
3665 {"TDM2 slot 23 Data Mux", "4312", "IF1_2_ADC3 Mux"},
3666 {"TDM2 slot 23 Data Mux", "4321", "IF1_2_ADC3 Mux"},
3667 {"TDM2 slot 23 Data Mux", NULL, "I2S1_2"},
3668
3669 {"TDM2 slot 45 Data Mux", "1234", "IF1_2_ADC3 Mux"},
3670 {"TDM2 slot 45 Data Mux", "1243", "IF1_2_ADC4 Mux"},
3671 {"TDM2 slot 45 Data Mux", "1324", "IF1_2_ADC2 Mux"},
3672 {"TDM2 slot 45 Data Mux", "1342", "IF1_2_ADC4 Mux"},
3673 {"TDM2 slot 45 Data Mux", "1432", "IF1_2_ADC3 Mux"},
3674 {"TDM2 slot 45 Data Mux", "1423", "IF1_2_ADC2 Mux"},
3675 {"TDM2 slot 45 Data Mux", "2134", "IF1_2_ADC3 Mux"},
3676 {"TDM2 slot 45 Data Mux", "2143", "IF1_2_ADC4 Mux"},
3677 {"TDM2 slot 45 Data Mux", "2314", "IF1_2_ADC1 Mux"},
3678 {"TDM2 slot 45 Data Mux", "2341", "IF1_2_ADC4 Mux"},
3679 {"TDM2 slot 45 Data Mux", "2431", "IF1_2_ADC3 Mux"},
3680 {"TDM2 slot 45 Data Mux", "2413", "IF1_2_ADC1 Mux"},
3681 {"TDM2 slot 45 Data Mux", "3124", "IF1_2_ADC2 Mux"},
3682 {"TDM2 slot 45 Data Mux", "3142", "IF1_2_ADC4 Mux"},
3683 {"TDM2 slot 45 Data Mux", "3214", "IF1_2_ADC1 Mux"},
3684 {"TDM2 slot 45 Data Mux", "3241", "IF1_2_ADC4 Mux"},
3685 {"TDM2 slot 45 Data Mux", "3412", "IF1_2_ADC1 Mux"},
3686 {"TDM2 slot 45 Data Mux", "3421", "IF1_2_ADC2 Mux"},
3687 {"TDM2 slot 45 Data Mux", "4123", "IF1_2_ADC2 Mux"},
3688 {"TDM2 slot 45 Data Mux", "4132", "IF1_2_ADC3 Mux"},
3689 {"TDM2 slot 45 Data Mux", "4213", "IF1_2_ADC1 Mux"},
3690 {"TDM2 slot 45 Data Mux", "4231", "IF1_2_ADC3 Mux"},
3691 {"TDM2 slot 45 Data Mux", "4312", "IF1_2_ADC1 Mux"},
3692 {"TDM2 slot 45 Data Mux", "4321", "IF1_2_ADC2 Mux"},
3693 {"TDM2 slot 45 Data Mux", NULL, "I2S1_2"},
3694
3695 {"TDM2 slot 67 Data Mux", "1234", "IF1_2_ADC4 Mux"},
3696 {"TDM2 slot 67 Data Mux", "1243", "IF1_2_ADC3 Mux"},
3697 {"TDM2 slot 67 Data Mux", "1324", "IF1_2_ADC4 Mux"},
3698 {"TDM2 slot 67 Data Mux", "1342", "IF1_2_ADC2 Mux"},
3699 {"TDM2 slot 67 Data Mux", "1432", "IF1_2_ADC2 Mux"},
3700 {"TDM2 slot 67 Data Mux", "1423", "IF1_2_ADC3 Mux"},
3701 {"TDM2 slot 67 Data Mux", "2134", "IF1_2_ADC4 Mux"},
3702 {"TDM2 slot 67 Data Mux", "2143", "IF1_2_ADC3 Mux"},
3703 {"TDM2 slot 67 Data Mux", "2314", "IF1_2_ADC4 Mux"},
3704 {"TDM2 slot 67 Data Mux", "2341", "IF1_2_ADC1 Mux"},
3705 {"TDM2 slot 67 Data Mux", "2431", "IF1_2_ADC1 Mux"},
3706 {"TDM2 slot 67 Data Mux", "2413", "IF1_2_ADC3 Mux"},
3707 {"TDM2 slot 67 Data Mux", "3124", "IF1_2_ADC4 Mux"},
3708 {"TDM2 slot 67 Data Mux", "3142", "IF1_2_ADC2 Mux"},
3709 {"TDM2 slot 67 Data Mux", "3214", "IF1_2_ADC4 Mux"},
3710 {"TDM2 slot 67 Data Mux", "3241", "IF1_2_ADC1 Mux"},
3711 {"TDM2 slot 67 Data Mux", "3412", "IF1_2_ADC2 Mux"},
3712 {"TDM2 slot 67 Data Mux", "3421", "IF1_2_ADC1 Mux"},
3713 {"TDM2 slot 67 Data Mux", "4123", "IF1_2_ADC3 Mux"},
3714 {"TDM2 slot 67 Data Mux", "4132", "IF1_2_ADC2 Mux"},
3715 {"TDM2 slot 67 Data Mux", "4213", "IF1_2_ADC3 Mux"},
3716 {"TDM2 slot 67 Data Mux", "4231", "IF1_2_ADC1 Mux"},
3717 {"TDM2 slot 67 Data Mux", "4312", "IF1_2_ADC2 Mux"},
3718 {"TDM2 slot 67 Data Mux", "4321", "IF1_2_ADC1 Mux"},
3719 {"TDM2 slot 67 Data Mux", NULL, "I2S1_2"},
3720
3721 {"IF1_1 0 ADC Swap Mux", "L/R", "TDM1 slot 01 Data Mux"},
3722 {"IF1_1 0 ADC Swap Mux", "L/L", "TDM1 slot 01 Data Mux"},
3723 {"IF1_1 1 ADC Swap Mux", "R/L", "TDM1 slot 01 Data Mux"},
3724 {"IF1_1 1 ADC Swap Mux", "R/R", "TDM1 slot 01 Data Mux"},
3725 {"IF1_1 2 ADC Swap Mux", "L/R", "TDM1 slot 23 Data Mux"},
3726 {"IF1_1 2 ADC Swap Mux", "R/L", "TDM1 slot 23 Data Mux"},
3727 {"IF1_1 3 ADC Swap Mux", "L/L", "TDM1 slot 23 Data Mux"},
3728 {"IF1_1 3 ADC Swap Mux", "R/R", "TDM1 slot 23 Data Mux"},
3729 {"IF1_1 4 ADC Swap Mux", "L/R", "TDM1 slot 45 Data Mux"},
3730 {"IF1_1 4 ADC Swap Mux", "R/L", "TDM1 slot 45 Data Mux"},
3731 {"IF1_1 5 ADC Swap Mux", "L/L", "TDM1 slot 45 Data Mux"},
3732 {"IF1_1 5 ADC Swap Mux", "R/R", "TDM1 slot 45 Data Mux"},
3733 {"IF1_1 6 ADC Swap Mux", "L/R", "TDM1 slot 67 Data Mux"},
3734 {"IF1_1 6 ADC Swap Mux", "R/L", "TDM1 slot 67 Data Mux"},
3735 {"IF1_1 7 ADC Swap Mux", "L/L", "TDM1 slot 67 Data Mux"},
3736 {"IF1_1 7 ADC Swap Mux", "R/R", "TDM1 slot 67 Data Mux"},
3737 {"IF1_2 0 ADC Swap Mux", "L/R", "TDM2 slot 01 Data Mux"},
3738 {"IF1_2 0 ADC Swap Mux", "R/L", "TDM2 slot 01 Data Mux"},
3739 {"IF1_2 1 ADC Swap Mux", "L/L", "TDM2 slot 01 Data Mux"},
3740 {"IF1_2 1 ADC Swap Mux", "R/R", "TDM2 slot 01 Data Mux"},
3741 {"IF1_2 2 ADC Swap Mux", "L/R", "TDM2 slot 23 Data Mux"},
3742 {"IF1_2 2 ADC Swap Mux", "R/L", "TDM2 slot 23 Data Mux"},
3743 {"IF1_2 3 ADC Swap Mux", "L/L", "TDM2 slot 23 Data Mux"},
3744 {"IF1_2 3 ADC Swap Mux", "R/R", "TDM2 slot 23 Data Mux"},
3745 {"IF1_2 4 ADC Swap Mux", "L/R", "TDM2 slot 45 Data Mux"},
3746 {"IF1_2 4 ADC Swap Mux", "R/L", "TDM2 slot 45 Data Mux"},
3747 {"IF1_2 5 ADC Swap Mux", "L/L", "TDM2 slot 45 Data Mux"},
3748 {"IF1_2 5 ADC Swap Mux", "R/R", "TDM2 slot 45 Data Mux"},
3749 {"IF1_2 6 ADC Swap Mux", "L/R", "TDM2 slot 67 Data Mux"},
3750 {"IF1_2 6 ADC Swap Mux", "R/L", "TDM2 slot 67 Data Mux"},
3751 {"IF1_2 7 ADC Swap Mux", "L/L", "TDM2 slot 67 Data Mux"},
3752 {"IF1_2 7 ADC Swap Mux", "R/R", "TDM2 slot 67 Data Mux"},
3753
3754 {"IF2_1 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3755 {"IF2_1 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3756 {"IF2_1 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3757 {"IF2_1 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3758 {"IF2_1 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3759 {"IF2_1 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3760 {"IF2_1 ADC Mux", "IF3 DAC", "IF3 DAC"},
3761 {"IF2_1 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3762 {"IF2_1 ADC", NULL, "IF2_1 ADC Mux"},
3763 {"IF2_1 ADC", NULL, "I2S2_1"},
3764
3765 {"IF2_2 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3766 {"IF2_2 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3767 {"IF2_2 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3768 {"IF2_2 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3769 {"IF2_2 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3770 {"IF2_2 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3771 {"IF2_2 ADC Mux", "IF3 DAC", "IF3 DAC"},
3772 {"IF2_2 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3773 {"IF2_2 ADC", NULL, "IF2_2 ADC Mux"},
3774 {"IF2_2 ADC", NULL, "I2S2_2"},
3775
3776 {"IF3 ADC Mux", "STO1 ADC", "Stereo1 ADC MIX"},
3777 {"IF3 ADC Mux", "STO2 ADC", "Stereo2 ADC MIX"},
3778 {"IF3 ADC Mux", "MONO ADC", "Mono ADC MIX"},
3779 {"IF3 ADC Mux", "IF1 DAC1", "IF1 DAC1"},
3780 {"IF3 ADC Mux", "IF1 DAC2", "IF1 DAC2"},
3781 {"IF3 ADC Mux", "IF2_1 DAC", "IF2_1 DAC"},
3782 {"IF3 ADC Mux", "IF2_2 DAC", "IF2_2 DAC"},
3783 {"IF3 ADC Mux", "DAC1 MIX", "DAC1 MIX"},
3784 {"IF3 ADC", NULL, "IF3 ADC Mux"},
3785 {"IF3 ADC", NULL, "I2S3"},
3786
3787 {"AIF1_1TX slot 0", NULL, "IF1_1 0 ADC Swap Mux"},
3788 {"AIF1_1TX slot 1", NULL, "IF1_1 1 ADC Swap Mux"},
3789 {"AIF1_1TX slot 2", NULL, "IF1_1 2 ADC Swap Mux"},
3790 {"AIF1_1TX slot 3", NULL, "IF1_1 3 ADC Swap Mux"},
3791 {"AIF1_1TX slot 4", NULL, "IF1_1 4 ADC Swap Mux"},
3792 {"AIF1_1TX slot 5", NULL, "IF1_1 5 ADC Swap Mux"},
3793 {"AIF1_1TX slot 6", NULL, "IF1_1 6 ADC Swap Mux"},
3794 {"AIF1_1TX slot 7", NULL, "IF1_1 7 ADC Swap Mux"},
3795 {"AIF1_2TX slot 0", NULL, "IF1_2 0 ADC Swap Mux"},
3796 {"AIF1_2TX slot 1", NULL, "IF1_2 1 ADC Swap Mux"},
3797 {"AIF1_2TX slot 2", NULL, "IF1_2 2 ADC Swap Mux"},
3798 {"AIF1_2TX slot 3", NULL, "IF1_2 3 ADC Swap Mux"},
3799 {"AIF1_2TX slot 4", NULL, "IF1_2 4 ADC Swap Mux"},
3800 {"AIF1_2TX slot 5", NULL, "IF1_2 5 ADC Swap Mux"},
3801 {"AIF1_2TX slot 6", NULL, "IF1_2 6 ADC Swap Mux"},
3802 {"AIF1_2TX slot 7", NULL, "IF1_2 7 ADC Swap Mux"},
3803 {"IF2_1 ADC Swap Mux", "L/R", "IF2_1 ADC"},
3804 {"IF2_1 ADC Swap Mux", "R/L", "IF2_1 ADC"},
3805 {"IF2_1 ADC Swap Mux", "L/L", "IF2_1 ADC"},
3806 {"IF2_1 ADC Swap Mux", "R/R", "IF2_1 ADC"},
3807 {"AIF2_1TX", NULL, "IF2_1 ADC Swap Mux"},
3808 {"IF2_2 ADC Swap Mux", "L/R", "IF2_2 ADC"},
3809 {"IF2_2 ADC Swap Mux", "R/L", "IF2_2 ADC"},
3810 {"IF2_2 ADC Swap Mux", "L/L", "IF2_2 ADC"},
3811 {"IF2_2 ADC Swap Mux", "R/R", "IF2_2 ADC"},
3812 {"AIF2_2TX", NULL, "IF2_2 ADC Swap Mux"},
3813 {"IF3 ADC Swap Mux", "L/R", "IF3 ADC"},
3814 {"IF3 ADC Swap Mux", "R/L", "IF3 ADC"},
3815 {"IF3 ADC Swap Mux", "L/L", "IF3 ADC"},
3816 {"IF3 ADC Swap Mux", "R/R", "IF3 ADC"},
3817 {"AIF3TX", NULL, "IF3 ADC Swap Mux"},
3818
3819 {"IF1 DAC1", NULL, "AIF1RX"},
3820 {"IF1 DAC2", NULL, "AIF1RX"},
3821 {"IF1 DAC3", NULL, "AIF1RX"},
3822 {"IF2_1 DAC Swap Mux", "L/R", "AIF2_1RX"},
3823 {"IF2_1 DAC Swap Mux", "R/L", "AIF2_1RX"},
3824 {"IF2_1 DAC Swap Mux", "L/L", "AIF2_1RX"},
3825 {"IF2_1 DAC Swap Mux", "R/R", "AIF2_1RX"},
3826 {"IF2_2 DAC Swap Mux", "L/R", "AIF2_2RX"},
3827 {"IF2_2 DAC Swap Mux", "R/L", "AIF2_2RX"},
3828 {"IF2_2 DAC Swap Mux", "L/L", "AIF2_2RX"},
3829 {"IF2_2 DAC Swap Mux", "R/R", "AIF2_2RX"},
3830 {"IF2_1 DAC", NULL, "IF2_1 DAC Swap Mux"},
3831 {"IF2_2 DAC", NULL, "IF2_2 DAC Swap Mux"},
3832 {"IF3 DAC Swap Mux", "L/R", "AIF3RX"},
3833 {"IF3 DAC Swap Mux", "R/L", "AIF3RX"},
3834 {"IF3 DAC Swap Mux", "L/L", "AIF3RX"},
3835 {"IF3 DAC Swap Mux", "R/R", "AIF3RX"},
3836 {"IF3 DAC", NULL, "IF3 DAC Swap Mux"},
3837
3838 {"IF1 DAC1", NULL, "I2S1_1"},
3839 {"IF1 DAC2", NULL, "I2S1_1"},
3840 {"IF1 DAC3", NULL, "I2S1_1"},
3841 {"IF2_1 DAC", NULL, "I2S2_1"},
3842 {"IF2_2 DAC", NULL, "I2S2_2"},
3843 {"IF3 DAC", NULL, "I2S3"},
3844
3845 {"IF1 DAC1 L", NULL, "IF1 DAC1"},
3846 {"IF1 DAC1 R", NULL, "IF1 DAC1"},
3847 {"IF1 DAC2 L", NULL, "IF1 DAC2"},
3848 {"IF1 DAC2 R", NULL, "IF1 DAC2"},
3849 {"IF1 DAC3 L", NULL, "IF1 DAC3"},
3850 {"IF1 DAC3 R", NULL, "IF1 DAC3"},
3851 {"IF2_1 DAC L", NULL, "IF2_1 DAC"},
3852 {"IF2_1 DAC R", NULL, "IF2_1 DAC"},
3853 {"IF2_2 DAC L", NULL, "IF2_2 DAC"},
3854 {"IF2_2 DAC R", NULL, "IF2_2 DAC"},
3855 {"IF3 DAC L", NULL, "IF3 DAC"},
3856 {"IF3 DAC R", NULL, "IF3 DAC"},
3857
3858 {"DAC L1 Mux", "IF1 DAC1", "IF1 DAC1 L"},
3859 {"DAC L1 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3860 {"DAC L1 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3861 {"DAC L1 Mux", "IF3 DAC", "IF3 DAC L"},
3862 {"DAC L1 Mux", NULL, "DAC Stereo1 Filter"},
3863
3864 {"DAC R1 Mux", "IF1 DAC1", "IF1 DAC1 R"},
3865 {"DAC R1 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3866 {"DAC R1 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3867 {"DAC R1 Mux", "IF3 DAC", "IF3 DAC R"},
3868 {"DAC R1 Mux", NULL, "DAC Stereo1 Filter"},
3869
3870 {"DAC1 MIXL", "Stereo ADC Switch", "Stereo1 ADC MIXL"},
3871 {"DAC1 MIXL", "DAC1 Switch", "DAC L1 Mux"},
3872 {"DAC1 MIXR", "Stereo ADC Switch", "Stereo1 ADC MIXR"},
3873 {"DAC1 MIXR", "DAC1 Switch", "DAC R1 Mux"},
3874
3875 {"DAC1 MIX", NULL, "DAC1 MIXL"},
3876 {"DAC1 MIX", NULL, "DAC1 MIXR"},
3877
3878 {"DAC L2 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3879 {"DAC L2 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3880 {"DAC L2 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3881 {"DAC L2 Mux", "IF3 DAC", "IF3 DAC L"},
3882 {"DAC L2 Mux", "Mono ADC MIX", "Mono ADC MIXL"},
3883 {"DAC L2 Mux", NULL, "DAC Mono Left Filter"},
3884
3885 {"DAC R2 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3886 {"DAC R2 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3887 {"DAC R2 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3888 {"DAC R2 Mux", "IF3 DAC", "IF3 DAC R"},
3889 {"DAC R2 Mux", "Mono ADC MIX", "Mono ADC MIXR"},
3890 {"DAC R2 Mux", NULL, "DAC Mono Right Filter"},
3891
3892 {"DAC L3 Mux", "IF1 DAC2", "IF1 DAC2 L"},
3893 {"DAC L3 Mux", "IF2_1 DAC", "IF2_1 DAC L"},
3894 {"DAC L3 Mux", "IF2_2 DAC", "IF2_2 DAC L"},
3895 {"DAC L3 Mux", "IF3 DAC", "IF3 DAC L"},
3896 {"DAC L3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXL"},
3897 {"DAC L3 Mux", NULL, "DAC Stereo2 Filter"},
3898
3899 {"DAC R3 Mux", "IF1 DAC2", "IF1 DAC2 R"},
3900 {"DAC R3 Mux", "IF2_1 DAC", "IF2_1 DAC R"},
3901 {"DAC R3 Mux", "IF2_2 DAC", "IF2_2 DAC R"},
3902 {"DAC R3 Mux", "IF3 DAC", "IF3 DAC R"},
3903 {"DAC R3 Mux", "STO2 ADC MIX", "Stereo2 ADC MIXR"},
3904 {"DAC R3 Mux", NULL, "DAC Stereo2 Filter"},
3905
3906 {"Stereo1 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3907 {"Stereo1 DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
3908 {"Stereo1 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3909 {"Stereo1 DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3910
3911 {"Stereo1 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3912 {"Stereo1 DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
3913 {"Stereo1 DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3914 {"Stereo1 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3915
3916 {"Stereo2 DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3917 {"Stereo2 DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3918 {"Stereo2 DAC MIXL", "DAC L3 Switch", "DAC L3 Mux"},
3919
3920 {"Stereo2 DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3921 {"Stereo2 DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3922 {"Stereo2 DAC MIXR", "DAC R3 Switch", "DAC R3 Mux"},
3923
3924 {"Mono DAC MIXL", "DAC L1 Switch", "DAC1 MIXL"},
3925 {"Mono DAC MIXL", "DAC R1 Switch", "DAC1 MIXR"},
3926 {"Mono DAC MIXL", "DAC L2 Switch", "DAC L2 Mux"},
3927 {"Mono DAC MIXL", "DAC R2 Switch", "DAC R2 Mux"},
3928 {"Mono DAC MIXR", "DAC L1 Switch", "DAC1 MIXL"},
3929 {"Mono DAC MIXR", "DAC R1 Switch", "DAC1 MIXR"},
3930 {"Mono DAC MIXR", "DAC L2 Switch", "DAC L2 Mux"},
3931 {"Mono DAC MIXR", "DAC R2 Switch", "DAC R2 Mux"},
3932
3933 {"DAC MIXL", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
3934 {"DAC MIXL", "Stereo2 DAC Mixer", "Stereo2 DAC MIXL"},
3935 {"DAC MIXL", "Mono DAC Mixer", "Mono DAC MIXL"},
3936 {"DAC MIXR", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
3937 {"DAC MIXR", "Stereo2 DAC Mixer", "Stereo2 DAC MIXR"},
3938 {"DAC MIXR", "Mono DAC Mixer", "Mono DAC MIXR"},
3939
3940 {"DAC L1 Source", "DAC1", "DAC1 MIXL"},
3941 {"DAC L1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXL"},
3942 {"DAC L1 Source", "DMIC1", "DMIC L1"},
3943 {"DAC R1 Source", "DAC1", "DAC1 MIXR"},
3944 {"DAC R1 Source", "Stereo1 DAC Mixer", "Stereo1 DAC MIXR"},
3945 {"DAC R1 Source", "DMIC1", "DMIC R1"},
3946
3947 {"DAC L2 Source", "DAC2", "DAC L2 Mux"},
3948 {"DAC L2 Source", "Mono DAC Mixer", "Mono DAC MIXL"},
3949 {"DAC L2 Source", NULL, "DAC L2 Power"},
3950 {"DAC R2 Source", "DAC2", "DAC R2 Mux"},
3951 {"DAC R2 Source", "Mono DAC Mixer", "Mono DAC MIXR"},
3952 {"DAC R2 Source", NULL, "DAC R2 Power"},
3953
3954 {"DAC L1", NULL, "DAC L1 Source"},
3955 {"DAC R1", NULL, "DAC R1 Source"},
3956 {"DAC L2", NULL, "DAC L2 Source"},
3957 {"DAC R2", NULL, "DAC R2 Source"},
3958
3959 {"DAC L1", NULL, "DAC 1 Clock"},
3960 {"DAC R1", NULL, "DAC 1 Clock"},
3961 {"DAC L2", NULL, "DAC 2 Clock"},
3962 {"DAC R2", NULL, "DAC 2 Clock"},
3963
3964 {"MONOVOL MIX", "DAC L2 Switch", "DAC L2"},
3965 {"MONOVOL MIX", "RECMIX2L Switch", "RECMIX2L"},
3966 {"MONOVOL MIX", "BST1 Switch", "BST1"},
3967 {"MONOVOL MIX", "BST2 Switch", "BST2"},
3968 {"MONOVOL MIX", "BST3 Switch", "BST3"},
3969
3970 {"OUT MIXL", "DAC L2 Switch", "DAC L2"},
3971 {"OUT MIXL", "INL Switch", "INL VOL"},
3972 {"OUT MIXL", "BST1 Switch", "BST1"},
3973 {"OUT MIXL", "BST2 Switch", "BST2"},
3974 {"OUT MIXL", "BST3 Switch", "BST3"},
3975 {"OUT MIXR", "DAC R2 Switch", "DAC R2"},
3976 {"OUT MIXR", "INR Switch", "INR VOL"},
3977 {"OUT MIXR", "BST2 Switch", "BST2"},
3978 {"OUT MIXR", "BST3 Switch", "BST3"},
3979 {"OUT MIXR", "BST4 Switch", "BST4"},
3980
3981 {"MONOVOL", "Switch", "MONOVOL MIX"},
3982 {"Mono MIX", "DAC L2 Switch", "DAC L2"},
3983 {"Mono MIX", "MONOVOL Switch", "MONOVOL"},
3984 {"Mono Amp", NULL, "Mono MIX"},
3985 {"Mono Amp", NULL, "Vref2"},
3986 {"Mono Amp", NULL, "Vref3"},
3987 {"Mono Amp", NULL, "CLKDET SYS"},
3988 {"Mono Amp", NULL, "CLKDET MONO"},
3989 {"Mono Playback", "Switch", "Mono Amp"},
3990 {"MONOOUT", NULL, "Mono Playback"},
3991
3992 {"HP Amp", NULL, "DAC L1"},
3993 {"HP Amp", NULL, "DAC R1"},
3994 {"HP Amp", NULL, "Charge Pump"},
3995 {"HP Amp", NULL, "CLKDET SYS"},
3996 {"HP Amp", NULL, "CLKDET HP"},
3997 {"HP Amp", NULL, "CBJ Power"},
3998 {"HP Amp", NULL, "Vref2"},
3999 {"HPO Playback", "Switch", "HP Amp"},
4000 {"HPOL", NULL, "HPO Playback"},
4001 {"HPOR", NULL, "HPO Playback"},
4002
4003 {"OUTVOL L", "Switch", "OUT MIXL"},
4004 {"OUTVOL R", "Switch", "OUT MIXR"},
4005 {"LOUT L MIX", "DAC L2 Switch", "DAC L2"},
4006 {"LOUT L MIX", "OUTVOL L Switch", "OUTVOL L"},
4007 {"LOUT R MIX", "DAC R2 Switch", "DAC R2"},
4008 {"LOUT R MIX", "OUTVOL R Switch", "OUTVOL R"},
4009 {"LOUT Amp", NULL, "LOUT L MIX"},
4010 {"LOUT Amp", NULL, "LOUT R MIX"},
4011 {"LOUT Amp", NULL, "Vref1"},
4012 {"LOUT Amp", NULL, "Vref2"},
4013 {"LOUT Amp", NULL, "CLKDET SYS"},
4014 {"LOUT Amp", NULL, "CLKDET LOUT"},
4015 {"LOUT L Playback", "Switch", "LOUT Amp"},
4016 {"LOUT R Playback", "Switch", "LOUT Amp"},
4017 {"LOUTL", NULL, "LOUT L Playback"},
4018 {"LOUTR", NULL, "LOUT R Playback"},
4019
4020 {"PDM L Mux", "Mono DAC", "Mono DAC MIXL"},
4021 {"PDM L Mux", "Stereo1 DAC", "Stereo1 DAC MIXL"},
4022 {"PDM L Mux", "Stereo2 DAC", "Stereo2 DAC MIXL"},
4023 {"PDM L Mux", NULL, "PDM Power"},
4024 {"PDM R Mux", "Mono DAC", "Mono DAC MIXR"},
4025 {"PDM R Mux", "Stereo1 DAC", "Stereo1 DAC MIXR"},
4026 {"PDM R Mux", "Stereo2 DAC", "Stereo2 DAC MIXR"},
4027 {"PDM R Mux", NULL, "PDM Power"},
4028 {"PDM L Playback", "Switch", "PDM L Mux"},
4029 {"PDM R Playback", "Switch", "PDM R Mux"},
4030 {"PDML", NULL, "PDM L Playback"},
4031 {"PDMR", NULL, "PDM R Playback"},
4032};
4033
4034static int rt5665_set_tdm_slot(struct snd_soc_dai *dai, unsigned int tx_mask,
4035 unsigned int rx_mask, int slots, int slot_width)
4036{
4037 struct snd_soc_codec *codec = dai->codec;
4038 unsigned int val = 0;
4039
4040 if (rx_mask || tx_mask)
4041 val |= RT5665_I2S1_MODE_TDM;
4042
4043 switch (slots) {
4044 case 4:
4045 val |= RT5665_TDM_IN_CH_4;
4046 val |= RT5665_TDM_OUT_CH_4;
4047 break;
4048 case 6:
4049 val |= RT5665_TDM_IN_CH_6;
4050 val |= RT5665_TDM_OUT_CH_6;
4051 break;
4052 case 8:
4053 val |= RT5665_TDM_IN_CH_8;
4054 val |= RT5665_TDM_OUT_CH_8;
4055 break;
4056 case 2:
4057 break;
4058 default:
4059 return -EINVAL;
4060 }
4061
4062 switch (slot_width) {
4063 case 20:
4064 val |= RT5665_TDM_IN_LEN_20;
4065 val |= RT5665_TDM_OUT_LEN_20;
4066 break;
4067 case 24:
4068 val |= RT5665_TDM_IN_LEN_24;
4069 val |= RT5665_TDM_OUT_LEN_24;
4070 break;
4071 case 32:
4072 val |= RT5665_TDM_IN_LEN_32;
4073 val |= RT5665_TDM_OUT_LEN_32;
4074 break;
4075 case 16:
4076 break;
4077 default:
4078 return -EINVAL;
4079 }
4080
4081 snd_soc_update_bits(codec, RT5665_TDM_CTRL_1,
4082 RT5665_I2S1_MODE_MASK | RT5665_TDM_IN_CH_MASK |
4083 RT5665_TDM_OUT_CH_MASK | RT5665_TDM_IN_LEN_MASK |
4084 RT5665_TDM_OUT_LEN_MASK, val);
4085
4086 return 0;
4087}
4088
4089
4090static int rt5665_hw_params(struct snd_pcm_substream *substream,
4091 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
4092{
4093 struct snd_soc_codec *codec = dai->codec;
4094 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4095 unsigned int val_len = 0, val_clk, reg_clk, mask_clk, val_bits = 0x0100;
4096 int pre_div, frame_size;
4097
4098 rt5665->lrck[dai->id] = params_rate(params);
4099 pre_div = rl6231_get_clk_info(rt5665->sysclk, rt5665->lrck[dai->id]);
4100 if (pre_div < 0) {
4101 dev_err(codec->dev, "Unsupported clock setting %d for DAI %d\n",
4102 rt5665->lrck[dai->id], dai->id);
4103 return -EINVAL;
4104 }
4105 frame_size = snd_soc_params_to_frame_size(params);
4106 if (frame_size < 0) {
4107 dev_err(codec->dev, "Unsupported frame size: %d\n", frame_size);
4108 return -EINVAL;
4109 }
4110
4111 dev_dbg(dai->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
4112 rt5665->lrck[dai->id], pre_div, dai->id);
4113
4114 switch (params_width(params)) {
4115 case 16:
4116 val_bits = 0x0100;
4117 break;
4118 case 20:
4119 val_len |= RT5665_I2S_DL_20;
4120 val_bits = 0x1300;
4121 break;
4122 case 24:
4123 val_len |= RT5665_I2S_DL_24;
4124 val_bits = 0x2500;
4125 break;
4126 case 8:
4127 val_len |= RT5665_I2S_DL_8;
4128 break;
4129 default:
4130 return -EINVAL;
4131 }
4132
4133 switch (dai->id) {
4134 case RT5665_AIF1_1:
4135 case RT5665_AIF1_2:
4136 if (params_channels(params) > 2)
4137 rt5665_set_tdm_slot(dai, 0xf, 0xf,
4138 params_channels(params), params_width(params));
4139 reg_clk = RT5665_ADDA_CLK_1;
4140 mask_clk = RT5665_I2S_PD1_MASK;
4141 val_clk = pre_div << RT5665_I2S_PD1_SFT;
4142 snd_soc_update_bits(codec, RT5665_I2S1_SDP,
4143 RT5665_I2S_DL_MASK, val_len);
4144 break;
4145 case RT5665_AIF2_1:
4146 case RT5665_AIF2_2:
4147 reg_clk = RT5665_ADDA_CLK_2;
4148 mask_clk = RT5665_I2S_PD2_MASK;
4149 val_clk = pre_div << RT5665_I2S_PD2_SFT;
4150 snd_soc_update_bits(codec, RT5665_I2S2_SDP,
4151 RT5665_I2S_DL_MASK, val_len);
4152 break;
4153 case RT5665_AIF3:
4154 reg_clk = RT5665_ADDA_CLK_2;
4155 mask_clk = RT5665_I2S_PD3_MASK;
4156 val_clk = pre_div << RT5665_I2S_PD3_SFT;
4157 snd_soc_update_bits(codec, RT5665_I2S3_SDP,
4158 RT5665_I2S_DL_MASK, val_len);
4159 break;
4160 default:
4161 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
4162 return -EINVAL;
4163 }
4164
4165 snd_soc_update_bits(codec, reg_clk, mask_clk, val_clk);
4166 snd_soc_update_bits(codec, RT5665_STO1_DAC_SIL_DET, 0x3700, val_bits);
4167
4168 switch (rt5665->lrck[dai->id]) {
4169 case 192000:
4170 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4171 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4172 RT5665_DAC_OSR_32 | RT5665_ADC_OSR_32);
4173 break;
4174 case 96000:
4175 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4176 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4177 RT5665_DAC_OSR_64 | RT5665_ADC_OSR_64);
4178 break;
4179 default:
4180 snd_soc_update_bits(codec, RT5665_ADDA_CLK_1,
4181 RT5665_DAC_OSR_MASK | RT5665_ADC_OSR_MASK,
4182 RT5665_DAC_OSR_128 | RT5665_ADC_OSR_128);
4183 break;
4184 }
4185
4186 return 0;
4187}
4188
4189static int rt5665_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
4190{
4191 struct snd_soc_codec *codec = dai->codec;
4192 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4193 unsigned int reg_val = 0;
4194
4195 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
4196 case SND_SOC_DAIFMT_CBM_CFM:
4197 rt5665->master[dai->id] = 1;
4198 break;
4199 case SND_SOC_DAIFMT_CBS_CFS:
4200 reg_val |= RT5665_I2S_MS_S;
4201 rt5665->master[dai->id] = 0;
4202 break;
4203 default:
4204 return -EINVAL;
4205 }
4206
4207 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
4208 case SND_SOC_DAIFMT_NB_NF:
4209 break;
4210 case SND_SOC_DAIFMT_IB_NF:
4211 reg_val |= RT5665_I2S_BP_INV;
4212 break;
4213 default:
4214 return -EINVAL;
4215 }
4216
4217 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
4218 case SND_SOC_DAIFMT_I2S:
4219 break;
4220 case SND_SOC_DAIFMT_LEFT_J:
4221 reg_val |= RT5665_I2S_DF_LEFT;
4222 break;
4223 case SND_SOC_DAIFMT_DSP_A:
4224 reg_val |= RT5665_I2S_DF_PCM_A;
4225 break;
4226 case SND_SOC_DAIFMT_DSP_B:
4227 reg_val |= RT5665_I2S_DF_PCM_B;
4228 break;
4229 default:
4230 return -EINVAL;
4231 }
4232
4233 switch (dai->id) {
4234 case RT5665_AIF1_1:
4235 case RT5665_AIF1_2:
4236 snd_soc_update_bits(codec, RT5665_I2S1_SDP,
4237 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4238 RT5665_I2S_DF_MASK, reg_val);
4239 break;
4240 case RT5665_AIF2_1:
4241 case RT5665_AIF2_2:
4242 snd_soc_update_bits(codec, RT5665_I2S2_SDP,
4243 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4244 RT5665_I2S_DF_MASK, reg_val);
4245 break;
4246 case RT5665_AIF3:
4247 snd_soc_update_bits(codec, RT5665_I2S3_SDP,
4248 RT5665_I2S_MS_MASK | RT5665_I2S_BP_MASK |
4249 RT5665_I2S_DF_MASK, reg_val);
4250 break;
4251 default:
4252 dev_err(codec->dev, "Invalid dai->id: %d\n", dai->id);
4253 return -EINVAL;
4254 }
4255 return 0;
4256}
4257
4258static int rt5665_set_codec_sysclk(struct snd_soc_codec *codec, int clk_id,
4259 int source, unsigned int freq, int dir)
4260{
4261 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4262 unsigned int reg_val = 0;
4263
4264 if (freq == rt5665->sysclk && clk_id == rt5665->sysclk_src)
4265 return 0;
4266
4267 switch (clk_id) {
4268 case RT5665_SCLK_S_MCLK:
4269 reg_val |= RT5665_SCLK_SRC_MCLK;
4270 break;
4271 case RT5665_SCLK_S_PLL1:
4272 reg_val |= RT5665_SCLK_SRC_PLL1;
4273 break;
4274 case RT5665_SCLK_S_RCCLK:
4275 reg_val |= RT5665_SCLK_SRC_RCCLK;
4276 break;
4277 default:
4278 dev_err(codec->dev, "Invalid clock id (%d)\n", clk_id);
4279 return -EINVAL;
4280 }
4281 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4282 RT5665_SCLK_SRC_MASK, reg_val);
4283 rt5665->sysclk = freq;
4284 rt5665->sysclk_src = clk_id;
4285
4286 dev_dbg(codec->dev, "Sysclk is %dHz and clock id is %d\n", freq, clk_id);
4287
4288 return 0;
4289}
4290
4291static int rt5665_set_codec_pll(struct snd_soc_codec *codec, int pll_id,
4292 int source, unsigned int freq_in,
4293 unsigned int freq_out)
4294{
4295 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4296 struct rl6231_pll_code pll_code;
4297 int ret;
4298
4299 if (source == rt5665->pll_src && freq_in == rt5665->pll_in &&
4300 freq_out == rt5665->pll_out)
4301 return 0;
4302
4303 if (!freq_in || !freq_out) {
4304 dev_dbg(codec->dev, "PLL disabled\n");
4305
4306 rt5665->pll_in = 0;
4307 rt5665->pll_out = 0;
4308 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4309 RT5665_SCLK_SRC_MASK, RT5665_SCLK_SRC_MCLK);
4310 return 0;
4311 }
4312
4313 switch (source) {
4314 case RT5665_PLL1_S_MCLK:
4315 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4316 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_MCLK);
4317 break;
4318 case RT5665_PLL1_S_BCLK1:
4319 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4320 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK1);
4321 break;
4322 case RT5665_PLL1_S_BCLK2:
4323 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4324 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK2);
4325 break;
4326 case RT5665_PLL1_S_BCLK3:
4327 snd_soc_update_bits(codec, RT5665_GLB_CLK,
4328 RT5665_PLL1_SRC_MASK, RT5665_PLL1_SRC_BCLK3);
4329 break;
4330 default:
4331 dev_err(codec->dev, "Unknown PLL Source %d\n", source);
4332 return -EINVAL;
4333 }
4334
4335 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
4336 if (ret < 0) {
4337 dev_err(codec->dev, "Unsupport input clock %d\n", freq_in);
4338 return ret;
4339 }
4340
4341 dev_dbg(codec->dev, "bypass=%d m=%d n=%d k=%d\n",
4342 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
4343 pll_code.n_code, pll_code.k_code);
4344
4345 snd_soc_write(codec, RT5665_PLL_CTRL_1,
4346 pll_code.n_code << RT5665_PLL_N_SFT | pll_code.k_code);
4347 snd_soc_write(codec, RT5665_PLL_CTRL_2,
4348 (pll_code.m_bp ? 0 : pll_code.m_code) << RT5665_PLL_M_SFT |
4349 pll_code.m_bp << RT5665_PLL_M_BP_SFT);
4350
4351 rt5665->pll_in = freq_in;
4352 rt5665->pll_out = freq_out;
4353 rt5665->pll_src = source;
4354
4355 return 0;
4356}
4357
4358static int rt5665_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
4359{
4360 struct snd_soc_codec *codec = dai->codec;
4361 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4362
4363 dev_dbg(codec->dev, "%s ratio=%d\n", __func__, ratio);
4364
4365 rt5665->bclk[dai->id] = ratio;
4366
4367 if (ratio == 64) {
4368 switch (dai->id) {
4369 case RT5665_AIF2_1:
4370 case RT5665_AIF2_2:
4371 snd_soc_update_bits(codec, RT5665_ADDA_CLK_2,
4372 RT5665_I2S_BCLK_MS2_MASK,
4373 RT5665_I2S_BCLK_MS2_64);
4374 break;
4375 case RT5665_AIF3:
4376 snd_soc_update_bits(codec, RT5665_ADDA_CLK_2,
4377 RT5665_I2S_BCLK_MS3_MASK,
4378 RT5665_I2S_BCLK_MS3_64);
4379 break;
4380 }
4381 }
4382
4383 return 0;
4384}
4385
4386static int rt5665_set_bias_level(struct snd_soc_codec *codec,
4387 enum snd_soc_bias_level level)
4388{
4389 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4390
4391 switch (level) {
4392 case SND_SOC_BIAS_PREPARE:
4393 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4394 RT5665_DIG_GATE_CTRL, RT5665_DIG_GATE_CTRL);
4395 break;
4396
4397 case SND_SOC_BIAS_STANDBY:
4398 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4399 RT5665_PWR_LDO, RT5665_PWR_LDO);
4400 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4401 RT5665_PWR_MB, RT5665_PWR_MB);
4402 regmap_update_bits(rt5665->regmap, RT5665_DIG_MISC,
4403 RT5665_DIG_GATE_CTRL, 0);
4404 break;
4405 case SND_SOC_BIAS_OFF:
4406 regmap_update_bits(rt5665->regmap, RT5665_PWR_DIG_1,
4407 RT5665_PWR_LDO, 0);
4408 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4409 RT5665_PWR_MB, 0);
4410 break;
4411
4412 default:
4413 break;
4414 }
4415
4416 return 0;
4417}
4418
4419static int rt5665_probe(struct snd_soc_codec *codec)
4420{
4421 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4422
4423 rt5665->codec = codec;
4424
4425 schedule_delayed_work(&rt5665->calibrate_work, msecs_to_jiffies(100));
4426
4427 return 0;
4428}
4429
4430static int rt5665_remove(struct snd_soc_codec *codec)
4431{
4432 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4433
4434 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4435
4436 return 0;
4437}
4438
4439#ifdef CONFIG_PM
4440static int rt5665_suspend(struct snd_soc_codec *codec)
4441{
4442 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4443
4444 regcache_cache_only(rt5665->regmap, true);
4445 regcache_mark_dirty(rt5665->regmap);
4446 return 0;
4447}
4448
4449static int rt5665_resume(struct snd_soc_codec *codec)
4450{
4451 struct rt5665_priv *rt5665 = snd_soc_codec_get_drvdata(codec);
4452
4453 regcache_cache_only(rt5665->regmap, false);
4454 regcache_sync(rt5665->regmap);
4455
4456 return 0;
4457}
4458#else
4459#define rt5665_suspend NULL
4460#define rt5665_resume NULL
4461#endif
4462
4463#define RT5665_STEREO_RATES SNDRV_PCM_RATE_8000_192000
4464#define RT5665_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
4465 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
4466
4467static const struct snd_soc_dai_ops rt5665_aif_dai_ops = {
4468 .hw_params = rt5665_hw_params,
4469 .set_fmt = rt5665_set_dai_fmt,
4470 .set_tdm_slot = rt5665_set_tdm_slot,
4471 .set_bclk_ratio = rt5665_set_bclk_ratio,
4472};
4473
4474static struct snd_soc_dai_driver rt5665_dai[] = {
4475 {
4476 .name = "rt5665-aif1_1",
4477 .id = RT5665_AIF1_1,
4478 .playback = {
4479 .stream_name = "AIF1 Playback",
4480 .channels_min = 1,
4481 .channels_max = 8,
4482 .rates = RT5665_STEREO_RATES,
4483 .formats = RT5665_FORMATS,
4484 },
4485 .capture = {
4486 .stream_name = "AIF1_1 Capture",
4487 .channels_min = 1,
4488 .channels_max = 8,
4489 .rates = RT5665_STEREO_RATES,
4490 .formats = RT5665_FORMATS,
4491 },
4492 .ops = &rt5665_aif_dai_ops,
4493 },
4494 {
4495 .name = "rt5665-aif1_2",
4496 .id = RT5665_AIF1_2,
4497 .capture = {
4498 .stream_name = "AIF1_2 Capture",
4499 .channels_min = 1,
4500 .channels_max = 8,
4501 .rates = RT5665_STEREO_RATES,
4502 .formats = RT5665_FORMATS,
4503 },
4504 .ops = &rt5665_aif_dai_ops,
4505 },
4506 {
4507 .name = "rt5665-aif2_1",
4508 .id = RT5665_AIF2_1,
4509 .playback = {
4510 .stream_name = "AIF2_1 Playback",
4511 .channels_min = 1,
4512 .channels_max = 2,
4513 .rates = RT5665_STEREO_RATES,
4514 .formats = RT5665_FORMATS,
4515 },
4516 .capture = {
4517 .stream_name = "AIF2_1 Capture",
4518 .channels_min = 1,
4519 .channels_max = 2,
4520 .rates = RT5665_STEREO_RATES,
4521 .formats = RT5665_FORMATS,
4522 },
4523 .ops = &rt5665_aif_dai_ops,
4524 },
4525 {
4526 .name = "rt5665-aif2_2",
4527 .id = RT5665_AIF2_2,
4528 .playback = {
4529 .stream_name = "AIF2_2 Playback",
4530 .channels_min = 1,
4531 .channels_max = 2,
4532 .rates = RT5665_STEREO_RATES,
4533 .formats = RT5665_FORMATS,
4534 },
4535 .capture = {
4536 .stream_name = "AIF2_2 Capture",
4537 .channels_min = 1,
4538 .channels_max = 2,
4539 .rates = RT5665_STEREO_RATES,
4540 .formats = RT5665_FORMATS,
4541 },
4542 .ops = &rt5665_aif_dai_ops,
4543 },
4544 {
4545 .name = "rt5665-aif3",
4546 .id = RT5665_AIF3,
4547 .playback = {
4548 .stream_name = "AIF3 Playback",
4549 .channels_min = 1,
4550 .channels_max = 2,
4551 .rates = RT5665_STEREO_RATES,
4552 .formats = RT5665_FORMATS,
4553 },
4554 .capture = {
4555 .stream_name = "AIF3 Capture",
4556 .channels_min = 1,
4557 .channels_max = 2,
4558 .rates = RT5665_STEREO_RATES,
4559 .formats = RT5665_FORMATS,
4560 },
4561 .ops = &rt5665_aif_dai_ops,
4562 },
4563};
4564
4565static struct snd_soc_codec_driver soc_codec_dev_rt5665 = {
4566 .probe = rt5665_probe,
4567 .remove = rt5665_remove,
4568 .suspend = rt5665_suspend,
4569 .resume = rt5665_resume,
4570 .set_bias_level = rt5665_set_bias_level,
4571 .idle_bias_off = true,
4572 .component_driver = {
4573 .controls = rt5665_snd_controls,
4574 .num_controls = ARRAY_SIZE(rt5665_snd_controls),
4575 .dapm_widgets = rt5665_dapm_widgets,
4576 .num_dapm_widgets = ARRAY_SIZE(rt5665_dapm_widgets),
4577 .dapm_routes = rt5665_dapm_routes,
4578 .num_dapm_routes = ARRAY_SIZE(rt5665_dapm_routes),
4579 },
4580 .set_sysclk = rt5665_set_codec_sysclk,
4581 .set_pll = rt5665_set_codec_pll,
4582 .set_jack = rt5665_set_jack_detect,
4583};
4584
4585
4586static const struct regmap_config rt5665_regmap = {
4587 .reg_bits = 16,
4588 .val_bits = 16,
4589 .max_register = 0x0400,
4590 .volatile_reg = rt5665_volatile_register,
4591 .readable_reg = rt5665_readable_register,
4592 .cache_type = REGCACHE_RBTREE,
4593 .reg_defaults = rt5665_reg,
4594 .num_reg_defaults = ARRAY_SIZE(rt5665_reg),
4595 .use_single_rw = true,
4596};
4597
4598static const struct i2c_device_id rt5665_i2c_id[] = {
4599 {"rt5665", 0},
4600 {}
4601};
4602MODULE_DEVICE_TABLE(i2c, rt5665_i2c_id);
4603
4604static int rt5665_parse_dt(struct rt5665_priv *rt5665, struct device *dev)
4605{
4606 rt5665->pdata.in1_diff = of_property_read_bool(dev->of_node,
4607 "realtek,in1-differential");
4608 rt5665->pdata.in2_diff = of_property_read_bool(dev->of_node,
4609 "realtek,in2-differential");
4610 rt5665->pdata.in3_diff = of_property_read_bool(dev->of_node,
4611 "realtek,in3-differential");
4612 rt5665->pdata.in4_diff = of_property_read_bool(dev->of_node,
4613 "realtek,in4-differential");
4614
4615 of_property_read_u32(dev->of_node, "realtek,dmic1-data-pin",
4616 &rt5665->pdata.dmic1_data_pin);
4617 of_property_read_u32(dev->of_node, "realtek,dmic2-data-pin",
4618 &rt5665->pdata.dmic2_data_pin);
4619 of_property_read_u32(dev->of_node, "realtek,jd-src",
4620 &rt5665->pdata.jd_src);
4621
4622 rt5665->pdata.ldo1_en = of_get_named_gpio(dev->of_node,
4623 "realtek,ldo1-en-gpios", 0);
4624
4625 return 0;
4626}
4627
4628static void rt5665_calibrate(struct rt5665_priv *rt5665)
4629{
4630 int value, count;
4631
4632 mutex_lock(&rt5665->calibrate_mutex);
4633
4634 regcache_cache_bypass(rt5665->regmap, true);
4635
4636 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4637 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4638 regmap_write(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1, 0x0c26);
4639 regmap_write(rt5665->regmap, RT5665_MONOMIX_IN_GAIN, 0x021f);
4640 regmap_write(rt5665->regmap, RT5665_MONO_OUT, 0x480a);
4641 regmap_write(rt5665->regmap, RT5665_PWR_MIXER, 0x083f);
4642 regmap_write(rt5665->regmap, RT5665_PWR_DIG_1, 0x0180);
4643 regmap_write(rt5665->regmap, RT5665_EJD_CTRL_1, 0x4040);
4644 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0000);
4645 regmap_write(rt5665->regmap, RT5665_DIG_MISC, 0x0001);
4646 regmap_write(rt5665->regmap, RT5665_MICBIAS_2, 0x0380);
4647 regmap_write(rt5665->regmap, RT5665_GLB_CLK, 0x8000);
4648 regmap_write(rt5665->regmap, RT5665_ADDA_CLK_1, 0x1000);
4649 regmap_write(rt5665->regmap, RT5665_CHOP_DAC, 0x3030);
4650 regmap_write(rt5665->regmap, RT5665_CALIB_ADC_CTRL, 0x3c05);
4651 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xaa3e);
4652 usleep_range(15000, 20000);
4653 regmap_write(rt5665->regmap, RT5665_PWR_ANLG_1, 0xfe7e);
4654 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_2, 0x0321);
4655
4656 regmap_write(rt5665->regmap, RT5665_HP_CALIB_CTRL_1, 0xfc00);
4657 count = 0;
4658 while (true) {
4659 regmap_read(rt5665->regmap, RT5665_HP_CALIB_STA_1, &value);
4660 if (value & 0x8000)
4661 usleep_range(10000, 10005);
4662 else
4663 break;
4664
4665 if (count > 60) {
4666 pr_err("HP Calibration Failure\n");
4667 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4668 regcache_cache_bypass(rt5665->regmap, false);
4669 goto out_unlock;
4670 }
4671
4672 count++;
4673 }
4674
4675 regmap_write(rt5665->regmap, RT5665_MONO_AMP_CALIB_CTRL_1, 0x9e24);
4676 count = 0;
4677 while (true) {
4678 regmap_read(rt5665->regmap, RT5665_MONO_AMP_CALIB_STA1, &value);
4679 if (value & 0x8000)
4680 usleep_range(10000, 10005);
4681 else
4682 break;
4683
4684 if (count > 60) {
4685 pr_err("MONO Calibration Failure\n");
4686 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4687 regcache_cache_bypass(rt5665->regmap, false);
4688 goto out_unlock;
4689 }
4690
4691 count++;
4692 }
4693
4694 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4695 regcache_cache_bypass(rt5665->regmap, false);
4696
4697 regcache_mark_dirty(rt5665->regmap);
4698 regcache_sync(rt5665->regmap);
4699
4700 regmap_write(rt5665->regmap, RT5665_BIAS_CUR_CTRL_8, 0xa602);
4701 regmap_write(rt5665->regmap, RT5665_ASRC_8, 0x0120);
4702
4703out_unlock:
4704 rt5665->calibration_done = true;
4705 mutex_unlock(&rt5665->calibrate_mutex);
4706}
4707
4708static void rt5665_calibrate_handler(struct work_struct *work)
4709{
4710 struct rt5665_priv *rt5665 = container_of(work, struct rt5665_priv,
4711 calibrate_work.work);
4712
4713 while (!rt5665->codec->component.card->instantiated) {
4714 pr_debug("%s\n", __func__);
4715 usleep_range(10000, 15000);
4716 }
4717
4718 rt5665_calibrate(rt5665);
4719}
4720
4721static int rt5665_i2c_probe(struct i2c_client *i2c,
4722 const struct i2c_device_id *id)
4723{
4724 struct rt5665_platform_data *pdata = dev_get_platdata(&i2c->dev);
4725 struct rt5665_priv *rt5665;
4726 int i, ret;
4727 unsigned int val;
4728
4729 rt5665 = devm_kzalloc(&i2c->dev, sizeof(struct rt5665_priv),
4730 GFP_KERNEL);
4731
4732 if (rt5665 == NULL)
4733 return -ENOMEM;
4734
4735 i2c_set_clientdata(i2c, rt5665);
4736
4737 if (pdata)
4738 rt5665->pdata = *pdata;
4739 else
4740 rt5665_parse_dt(rt5665, &i2c->dev);
4741
4742 for (i = 0; i < ARRAY_SIZE(rt5665->supplies); i++)
4743 rt5665->supplies[i].supply = rt5665_supply_names[i];
4744
4745 ret = devm_regulator_bulk_get(&i2c->dev, ARRAY_SIZE(rt5665->supplies),
4746 rt5665->supplies);
4747 if (ret != 0) {
4748 dev_err(&i2c->dev, "Failed to request supplies: %d\n", ret);
4749 return ret;
4750 }
4751
4752 ret = regulator_bulk_enable(ARRAY_SIZE(rt5665->supplies),
4753 rt5665->supplies);
4754 if (ret != 0) {
4755 dev_err(&i2c->dev, "Failed to enable supplies: %d\n", ret);
4756 return ret;
4757 }
4758
4759 if (gpio_is_valid(rt5665->pdata.ldo1_en)) {
4760 if (devm_gpio_request_one(&i2c->dev, rt5665->pdata.ldo1_en,
4761 GPIOF_OUT_INIT_HIGH, "rt5665"))
4762 dev_err(&i2c->dev, "Fail gpio_request gpio_ldo\n");
4763 }
4764
4765
4766 usleep_range(300000, 350000);
4767
4768 rt5665->regmap = devm_regmap_init_i2c(i2c, &rt5665_regmap);
4769 if (IS_ERR(rt5665->regmap)) {
4770 ret = PTR_ERR(rt5665->regmap);
4771 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
4772 ret);
4773 return ret;
4774 }
4775
4776 regmap_read(rt5665->regmap, RT5665_DEVICE_ID, &val);
4777 if (val != DEVICE_ID) {
4778 dev_err(&i2c->dev,
4779 "Device with ID register %x is not rt5665\n", val);
4780 return -ENODEV;
4781 }
4782
4783 regmap_read(rt5665->regmap, RT5665_RESET, &val);
4784 switch (val) {
4785 case 0x0:
4786 rt5665->id = CODEC_5666;
4787 break;
4788 case 0x6:
4789 rt5665->id = CODEC_5668;
4790 break;
4791 case 0x3:
4792 default:
4793 rt5665->id = CODEC_5665;
4794 break;
4795 }
4796
4797 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4798
4799
4800 if (rt5665->pdata.in1_diff)
4801 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4802 RT5665_IN1_DF_MASK, RT5665_IN1_DF_MASK);
4803 if (rt5665->pdata.in2_diff)
4804 regmap_update_bits(rt5665->regmap, RT5665_IN1_IN2,
4805 RT5665_IN2_DF_MASK, RT5665_IN2_DF_MASK);
4806 if (rt5665->pdata.in3_diff)
4807 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4808 RT5665_IN3_DF_MASK, RT5665_IN3_DF_MASK);
4809 if (rt5665->pdata.in4_diff)
4810 regmap_update_bits(rt5665->regmap, RT5665_IN3_IN4,
4811 RT5665_IN4_DF_MASK, RT5665_IN4_DF_MASK);
4812
4813
4814 if (rt5665->pdata.dmic1_data_pin != RT5665_DMIC1_NULL ||
4815 rt5665->pdata.dmic2_data_pin != RT5665_DMIC2_NULL) {
4816 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4817 RT5665_GP9_PIN_MASK, RT5665_GP9_PIN_DMIC1_SCL);
4818 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4819 RT5665_GP8_PIN_MASK, RT5665_GP8_PIN_DMIC2_SCL);
4820 switch (rt5665->pdata.dmic1_data_pin) {
4821 case RT5665_DMIC1_DATA_IN2N:
4822 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4823 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_IN2N);
4824 break;
4825
4826 case RT5665_DMIC1_DATA_GPIO4:
4827 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4828 RT5665_DMIC_1_DP_MASK, RT5665_DMIC_1_DP_GPIO4);
4829 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4830 RT5665_GP4_PIN_MASK, RT5665_GP4_PIN_DMIC1_SDA);
4831 break;
4832
4833 default:
4834 dev_dbg(&i2c->dev, "no DMIC1\n");
4835 break;
4836 }
4837
4838 switch (rt5665->pdata.dmic2_data_pin) {
4839 case RT5665_DMIC2_DATA_IN2P:
4840 regmap_update_bits(rt5665->regmap, RT5665_DMIC_CTRL_1,
4841 RT5665_DMIC_2_DP_MASK, RT5665_DMIC_2_DP_IN2P);
4842 break;
4843
4844 case RT5665_DMIC2_DATA_GPIO5:
4845 regmap_update_bits(rt5665->regmap,
4846 RT5665_DMIC_CTRL_1,
4847 RT5665_DMIC_2_DP_MASK,
4848 RT5665_DMIC_2_DP_GPIO5);
4849 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_1,
4850 RT5665_GP5_PIN_MASK, RT5665_GP5_PIN_DMIC2_SDA);
4851 break;
4852
4853 default:
4854 dev_dbg(&i2c->dev, "no DMIC2\n");
4855 break;
4856
4857 }
4858 }
4859
4860 regmap_write(rt5665->regmap, RT5665_HP_LOGIC_CTRL_2, 0x0002);
4861 regmap_update_bits(rt5665->regmap, RT5665_EJD_CTRL_1,
4862 0xf000 | RT5665_VREF_POW_MASK, 0xe000 | RT5665_VREF_POW_REG);
4863
4864 regmap_update_bits(rt5665->regmap, RT5665_STO1_DAC_SIL_DET,
4865 RT5665_DEB_STO_DAC_MASK, RT5665_DEB_80_MS);
4866
4867 regmap_update_bits(rt5665->regmap, RT5665_HP_CHARGE_PUMP_1,
4868 RT5665_PM_HP_MASK, RT5665_PM_HP_HV);
4869
4870
4871 if (rt5665->id == CODEC_5666) {
4872 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_2,
4873 RT5665_GP4_PF_MASK, RT5665_GP4_PF_IN);
4874 regmap_update_bits(rt5665->regmap, RT5665_GPIO_CTRL_3,
4875 RT5665_GP8_PF_MASK, RT5665_GP8_PF_IN);
4876 }
4877
4878
4879 regmap_update_bits(rt5665->regmap, RT5665_PWR_ANLG_1,
4880 RT5665_HP_DRIVER_MASK | RT5665_LDO1_DVO_MASK,
4881 RT5665_HP_DRIVER_5X | RT5665_LDO1_DVO_12);
4882
4883 INIT_DELAYED_WORK(&rt5665->jack_detect_work,
4884 rt5665_jack_detect_handler);
4885 INIT_DELAYED_WORK(&rt5665->calibrate_work,
4886 rt5665_calibrate_handler);
4887 INIT_DELAYED_WORK(&rt5665->jd_check_work,
4888 rt5665_jd_check_handler);
4889
4890 mutex_init(&rt5665->calibrate_mutex);
4891
4892 if (i2c->irq) {
4893 ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
4894 rt5665_irq, IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING
4895 | IRQF_ONESHOT, "rt5665", rt5665);
4896 if (ret)
4897 dev_err(&i2c->dev, "Failed to reguest IRQ: %d\n", ret);
4898
4899 }
4900
4901 return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_rt5665,
4902 rt5665_dai, ARRAY_SIZE(rt5665_dai));
4903}
4904
4905static int rt5665_i2c_remove(struct i2c_client *i2c)
4906{
4907 snd_soc_unregister_codec(&i2c->dev);
4908
4909 return 0;
4910}
4911
4912static void rt5665_i2c_shutdown(struct i2c_client *client)
4913{
4914 struct rt5665_priv *rt5665 = i2c_get_clientdata(client);
4915
4916 regmap_write(rt5665->regmap, RT5665_RESET, 0);
4917}
4918
4919#ifdef CONFIG_OF
4920static const struct of_device_id rt5665_of_match[] = {
4921 {.compatible = "realtek,rt5665"},
4922 {.compatible = "realtek,rt5666"},
4923 {.compatible = "realtek,rt5668"},
4924 {},
4925};
4926MODULE_DEVICE_TABLE(of, rt5665_of_match);
4927#endif
4928
4929#ifdef CONFIG_ACPI
4930static struct acpi_device_id rt5665_acpi_match[] = {
4931 {"10EC5665", 0,},
4932 {"10EC5666", 0,},
4933 {"10EC5668", 0,},
4934 {},
4935};
4936MODULE_DEVICE_TABLE(acpi, rt5665_acpi_match);
4937#endif
4938
4939static struct i2c_driver rt5665_i2c_driver = {
4940 .driver = {
4941 .name = "rt5665",
4942 .of_match_table = of_match_ptr(rt5665_of_match),
4943 .acpi_match_table = ACPI_PTR(rt5665_acpi_match),
4944 },
4945 .probe = rt5665_i2c_probe,
4946 .remove = rt5665_i2c_remove,
4947 .shutdown = rt5665_i2c_shutdown,
4948 .id_table = rt5665_i2c_id,
4949};
4950module_i2c_driver(rt5665_i2c_driver);
4951
4952MODULE_DESCRIPTION("ASoC RT5665 driver");
4953MODULE_AUTHOR("Bard Liao <bardliao@realtek.com>");
4954MODULE_LICENSE("GPL v2");
4955
