linux/sound/soc/codecs/wm8350.c
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   1/*
   2 * wm8350.c -- WM8350 ALSA SoC audio driver
   3 *
   4 * Copyright (C) 2007-12 Wolfson Microelectronics PLC.
   5 *
   6 * Author: Liam Girdwood <lrg@slimlogic.co.uk>
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License version 2 as
  10 * published by the Free Software Foundation.
  11 */
  12
  13#include <linux/module.h>
  14#include <linux/moduleparam.h>
  15#include <linux/init.h>
  16#include <linux/slab.h>
  17#include <linux/delay.h>
  18#include <linux/pm.h>
  19#include <linux/platform_device.h>
  20#include <linux/mfd/wm8350/audio.h>
  21#include <linux/mfd/wm8350/core.h>
  22#include <linux/regulator/consumer.h>
  23#include <sound/core.h>
  24#include <sound/pcm.h>
  25#include <sound/pcm_params.h>
  26#include <sound/soc.h>
  27#include <sound/initval.h>
  28#include <sound/tlv.h>
  29#include <trace/events/asoc.h>
  30
  31#include "wm8350.h"
  32
  33#define WM8350_OUTn_0dB 0x39
  34
  35#define WM8350_RAMP_NONE        0
  36#define WM8350_RAMP_UP          1
  37#define WM8350_RAMP_DOWN        2
  38
  39/* We only include the analogue supplies here; the digital supplies
  40 * need to be available well before this driver can be probed.
  41 */
  42static const char *supply_names[] = {
  43        "AVDD",
  44        "HPVDD",
  45};
  46
  47struct wm8350_output {
  48        u16 active;
  49        u16 left_vol;
  50        u16 right_vol;
  51        u16 ramp;
  52        u16 mute;
  53};
  54
  55struct wm8350_jack_data {
  56        struct snd_soc_jack *jack;
  57        struct delayed_work work;
  58        int report;
  59        int short_report;
  60};
  61
  62struct wm8350_data {
  63        struct wm8350 *wm8350;
  64        struct wm8350_output out1;
  65        struct wm8350_output out2;
  66        struct wm8350_jack_data hpl;
  67        struct wm8350_jack_data hpr;
  68        struct wm8350_jack_data mic;
  69        struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
  70        int fll_freq_out;
  71        int fll_freq_in;
  72        struct delayed_work pga_work;
  73};
  74
  75/*
  76 * Ramp OUT1 PGA volume to minimise pops at stream startup and shutdown.
  77 */
  78static inline int wm8350_out1_ramp_step(struct wm8350_data *wm8350_data)
  79{
  80        struct wm8350_output *out1 = &wm8350_data->out1;
  81        struct wm8350 *wm8350 = wm8350_data->wm8350;
  82        int left_complete = 0, right_complete = 0;
  83        u16 reg, val;
  84
  85        /* left channel */
  86        reg = wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME);
  87        val = (reg & WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
  88
  89        if (out1->ramp == WM8350_RAMP_UP) {
  90                /* ramp step up */
  91                if (val < out1->left_vol) {
  92                        val++;
  93                        reg &= ~WM8350_OUT1L_VOL_MASK;
  94                        wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
  95                                         reg | (val << WM8350_OUT1L_VOL_SHIFT));
  96                } else
  97                        left_complete = 1;
  98        } else if (out1->ramp == WM8350_RAMP_DOWN) {
  99                /* ramp step down */
 100                if (val > 0) {
 101                        val--;
 102                        reg &= ~WM8350_OUT1L_VOL_MASK;
 103                        wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME,
 104                                         reg | (val << WM8350_OUT1L_VOL_SHIFT));
 105                } else
 106                        left_complete = 1;
 107        } else
 108                return 1;
 109
 110        /* right channel */
 111        reg = wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME);
 112        val = (reg & WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
 113        if (out1->ramp == WM8350_RAMP_UP) {
 114                /* ramp step up */
 115                if (val < out1->right_vol) {
 116                        val++;
 117                        reg &= ~WM8350_OUT1R_VOL_MASK;
 118                        wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
 119                                         reg | (val << WM8350_OUT1R_VOL_SHIFT));
 120                } else
 121                        right_complete = 1;
 122        } else if (out1->ramp == WM8350_RAMP_DOWN) {
 123                /* ramp step down */
 124                if (val > 0) {
 125                        val--;
 126                        reg &= ~WM8350_OUT1R_VOL_MASK;
 127                        wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME,
 128                                         reg | (val << WM8350_OUT1R_VOL_SHIFT));
 129                } else
 130                        right_complete = 1;
 131        }
 132
 133        /* only hit the update bit if either volume has changed this step */
 134        if (!left_complete || !right_complete)
 135                wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME, WM8350_OUT1_VU);
 136
 137        return left_complete & right_complete;
 138}
 139
 140/*
 141 * Ramp OUT2 PGA volume to minimise pops at stream startup and shutdown.
 142 */
 143static inline int wm8350_out2_ramp_step(struct wm8350_data *wm8350_data)
 144{
 145        struct wm8350_output *out2 = &wm8350_data->out2;
 146        struct wm8350 *wm8350 = wm8350_data->wm8350;
 147        int left_complete = 0, right_complete = 0;
 148        u16 reg, val;
 149
 150        /* left channel */
 151        reg = wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME);
 152        val = (reg & WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
 153        if (out2->ramp == WM8350_RAMP_UP) {
 154                /* ramp step up */
 155                if (val < out2->left_vol) {
 156                        val++;
 157                        reg &= ~WM8350_OUT2L_VOL_MASK;
 158                        wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
 159                                         reg | (val << WM8350_OUT1L_VOL_SHIFT));
 160                } else
 161                        left_complete = 1;
 162        } else if (out2->ramp == WM8350_RAMP_DOWN) {
 163                /* ramp step down */
 164                if (val > 0) {
 165                        val--;
 166                        reg &= ~WM8350_OUT2L_VOL_MASK;
 167                        wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME,
 168                                         reg | (val << WM8350_OUT1L_VOL_SHIFT));
 169                } else
 170                        left_complete = 1;
 171        } else
 172                return 1;
 173
 174        /* right channel */
 175        reg = wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME);
 176        val = (reg & WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
 177        if (out2->ramp == WM8350_RAMP_UP) {
 178                /* ramp step up */
 179                if (val < out2->right_vol) {
 180                        val++;
 181                        reg &= ~WM8350_OUT2R_VOL_MASK;
 182                        wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
 183                                         reg | (val << WM8350_OUT1R_VOL_SHIFT));
 184                } else
 185                        right_complete = 1;
 186        } else if (out2->ramp == WM8350_RAMP_DOWN) {
 187                /* ramp step down */
 188                if (val > 0) {
 189                        val--;
 190                        reg &= ~WM8350_OUT2R_VOL_MASK;
 191                        wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME,
 192                                         reg | (val << WM8350_OUT1R_VOL_SHIFT));
 193                } else
 194                        right_complete = 1;
 195        }
 196
 197        /* only hit the update bit if either volume has changed this step */
 198        if (!left_complete || !right_complete)
 199                wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME, WM8350_OUT2_VU);
 200
 201        return left_complete & right_complete;
 202}
 203
 204/*
 205 * This work ramps both output PGAs at stream start/stop time to
 206 * minimise pop associated with DAPM power switching.
 207 * It's best to enable Zero Cross when ramping occurs to minimise any
 208 * zipper noises.
 209 */
 210static void wm8350_pga_work(struct work_struct *work)
 211{
 212        struct wm8350_data *wm8350_data =
 213                container_of(work, struct wm8350_data, pga_work.work);
 214        struct wm8350_output *out1 = &wm8350_data->out1,
 215            *out2 = &wm8350_data->out2;
 216        int i, out1_complete, out2_complete;
 217
 218        /* do we need to ramp at all ? */
 219        if (out1->ramp == WM8350_RAMP_NONE && out2->ramp == WM8350_RAMP_NONE)
 220                return;
 221
 222        /* PGA volumes have 6 bits of resolution to ramp */
 223        for (i = 0; i <= 63; i++) {
 224                out1_complete = 1, out2_complete = 1;
 225                if (out1->ramp != WM8350_RAMP_NONE)
 226                        out1_complete = wm8350_out1_ramp_step(wm8350_data);
 227                if (out2->ramp != WM8350_RAMP_NONE)
 228                        out2_complete = wm8350_out2_ramp_step(wm8350_data);
 229
 230                /* ramp finished ? */
 231                if (out1_complete && out2_complete)
 232                        break;
 233
 234                /* we need to delay longer on the up ramp */
 235                if (out1->ramp == WM8350_RAMP_UP ||
 236                    out2->ramp == WM8350_RAMP_UP) {
 237                        /* delay is longer over 0dB as increases are larger */
 238                        if (i >= WM8350_OUTn_0dB)
 239                                schedule_timeout_interruptible(msecs_to_jiffies
 240                                                               (2));
 241                        else
 242                                schedule_timeout_interruptible(msecs_to_jiffies
 243                                                               (1));
 244                } else
 245                        udelay(50);     /* doesn't matter if we delay longer */
 246        }
 247
 248        out1->ramp = WM8350_RAMP_NONE;
 249        out2->ramp = WM8350_RAMP_NONE;
 250}
 251
 252/*
 253 * WM8350 Controls
 254 */
 255
 256static int pga_event(struct snd_soc_dapm_widget *w,
 257                     struct snd_kcontrol *kcontrol, int event)
 258{
 259        struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
 260        struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
 261        struct wm8350_output *out;
 262
 263        switch (w->shift) {
 264        case 0:
 265        case 1:
 266                out = &wm8350_data->out1;
 267                break;
 268        case 2:
 269        case 3:
 270                out = &wm8350_data->out2;
 271                break;
 272
 273        default:
 274                WARN(1, "Invalid shift %d\n", w->shift);
 275                return -1;
 276        }
 277
 278        switch (event) {
 279        case SND_SOC_DAPM_POST_PMU:
 280                out->ramp = WM8350_RAMP_UP;
 281                out->active = 1;
 282
 283                schedule_delayed_work(&wm8350_data->pga_work,
 284                                      msecs_to_jiffies(1));
 285                break;
 286
 287        case SND_SOC_DAPM_PRE_PMD:
 288                out->ramp = WM8350_RAMP_DOWN;
 289                out->active = 0;
 290
 291                schedule_delayed_work(&wm8350_data->pga_work,
 292                                      msecs_to_jiffies(1));
 293                break;
 294        }
 295
 296        return 0;
 297}
 298
 299static int wm8350_put_volsw_2r_vu(struct snd_kcontrol *kcontrol,
 300                                  struct snd_ctl_elem_value *ucontrol)
 301{
 302        struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 303        struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec);
 304        struct wm8350_output *out = NULL;
 305        struct soc_mixer_control *mc =
 306                (struct soc_mixer_control *)kcontrol->private_value;
 307        int ret;
 308        unsigned int reg = mc->reg;
 309        u16 val;
 310
 311        /* For OUT1 and OUT2 we shadow the values and only actually write
 312         * them out when active in order to ensure the amplifier comes on
 313         * as quietly as possible. */
 314        switch (reg) {
 315        case WM8350_LOUT1_VOLUME:
 316                out = &wm8350_priv->out1;
 317                break;
 318        case WM8350_LOUT2_VOLUME:
 319                out = &wm8350_priv->out2;
 320                break;
 321        default:
 322                break;
 323        }
 324
 325        if (out) {
 326                out->left_vol = ucontrol->value.integer.value[0];
 327                out->right_vol = ucontrol->value.integer.value[1];
 328                if (!out->active)
 329                        return 1;
 330        }
 331
 332        ret = snd_soc_put_volsw(kcontrol, ucontrol);
 333        if (ret < 0)
 334                return ret;
 335
 336        /* now hit the volume update bits (always bit 8) */
 337        val = snd_soc_read(codec, reg);
 338        snd_soc_write(codec, reg, val | WM8350_OUT1_VU);
 339        return 1;
 340}
 341
 342static int wm8350_get_volsw_2r(struct snd_kcontrol *kcontrol,
 343                               struct snd_ctl_elem_value *ucontrol)
 344{
 345        struct snd_soc_codec *codec = snd_soc_kcontrol_codec(kcontrol);
 346        struct wm8350_data *wm8350_priv = snd_soc_codec_get_drvdata(codec);
 347        struct wm8350_output *out1 = &wm8350_priv->out1;
 348        struct wm8350_output *out2 = &wm8350_priv->out2;
 349        struct soc_mixer_control *mc =
 350                (struct soc_mixer_control *)kcontrol->private_value;
 351        unsigned int reg = mc->reg;
 352
 353        /* If these are cached registers use the cache */
 354        switch (reg) {
 355        case WM8350_LOUT1_VOLUME:
 356                ucontrol->value.integer.value[0] = out1->left_vol;
 357                ucontrol->value.integer.value[1] = out1->right_vol;
 358                return 0;
 359
 360        case WM8350_LOUT2_VOLUME:
 361                ucontrol->value.integer.value[0] = out2->left_vol;
 362                ucontrol->value.integer.value[1] = out2->right_vol;
 363                return 0;
 364
 365        default:
 366                break;
 367        }
 368
 369        return snd_soc_get_volsw(kcontrol, ucontrol);
 370}
 371
 372static const char *wm8350_deemp[] = { "None", "32kHz", "44.1kHz", "48kHz" };
 373static const char *wm8350_pol[] = { "Normal", "Inv R", "Inv L", "Inv L & R" };
 374static const char *wm8350_dacmutem[] = { "Normal", "Soft" };
 375static const char *wm8350_dacmutes[] = { "Fast", "Slow" };
 376static const char *wm8350_adcfilter[] = { "None", "High Pass" };
 377static const char *wm8350_adchp[] = { "44.1kHz", "8kHz", "16kHz", "32kHz" };
 378static const char *wm8350_lr[] = { "Left", "Right" };
 379
 380static const struct soc_enum wm8350_enum[] = {
 381        SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 4, 4, wm8350_deemp),
 382        SOC_ENUM_SINGLE(WM8350_DAC_CONTROL, 0, 4, wm8350_pol),
 383        SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 14, 2, wm8350_dacmutem),
 384        SOC_ENUM_SINGLE(WM8350_DAC_MUTE_VOLUME, 13, 2, wm8350_dacmutes),
 385        SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 15, 2, wm8350_adcfilter),
 386        SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 8, 4, wm8350_adchp),
 387        SOC_ENUM_SINGLE(WM8350_ADC_CONTROL, 0, 4, wm8350_pol),
 388        SOC_ENUM_SINGLE(WM8350_INPUT_MIXER_VOLUME, 15, 2, wm8350_lr),
 389};
 390
 391static DECLARE_TLV_DB_SCALE(pre_amp_tlv, -1200, 3525, 0);
 392static DECLARE_TLV_DB_SCALE(out_pga_tlv, -5700, 600, 0);
 393static DECLARE_TLV_DB_SCALE(dac_pcm_tlv, -7163, 36, 1);
 394static DECLARE_TLV_DB_SCALE(adc_pcm_tlv, -12700, 50, 1);
 395static DECLARE_TLV_DB_SCALE(out_mix_tlv, -1500, 300, 1);
 396
 397static const DECLARE_TLV_DB_RANGE(capture_sd_tlv,
 398        0, 12, TLV_DB_SCALE_ITEM(-3600, 300, 1),
 399        13, 15, TLV_DB_SCALE_ITEM(0, 0, 0)
 400);
 401
 402static const struct snd_kcontrol_new wm8350_snd_controls[] = {
 403        SOC_ENUM("Playback Deemphasis", wm8350_enum[0]),
 404        SOC_ENUM("Playback DAC Inversion", wm8350_enum[1]),
 405        SOC_DOUBLE_R_EXT_TLV("Playback PCM Volume",
 406                                WM8350_DAC_DIGITAL_VOLUME_L,
 407                                WM8350_DAC_DIGITAL_VOLUME_R,
 408                                0, 255, 0, wm8350_get_volsw_2r,
 409                                wm8350_put_volsw_2r_vu, dac_pcm_tlv),
 410        SOC_ENUM("Playback PCM Mute Function", wm8350_enum[2]),
 411        SOC_ENUM("Playback PCM Mute Speed", wm8350_enum[3]),
 412        SOC_ENUM("Capture PCM Filter", wm8350_enum[4]),
 413        SOC_ENUM("Capture PCM HP Filter", wm8350_enum[5]),
 414        SOC_ENUM("Capture ADC Inversion", wm8350_enum[6]),
 415        SOC_DOUBLE_R_EXT_TLV("Capture PCM Volume",
 416                                WM8350_ADC_DIGITAL_VOLUME_L,
 417                                WM8350_ADC_DIGITAL_VOLUME_R,
 418                                0, 255, 0, wm8350_get_volsw_2r,
 419                                wm8350_put_volsw_2r_vu, adc_pcm_tlv),
 420        SOC_DOUBLE_TLV("Capture Sidetone Volume",
 421                       WM8350_ADC_DIVIDER,
 422                       8, 4, 15, 1, capture_sd_tlv),
 423        SOC_DOUBLE_R_EXT_TLV("Capture Volume",
 424                                WM8350_LEFT_INPUT_VOLUME,
 425                                WM8350_RIGHT_INPUT_VOLUME,
 426                                2, 63, 0, wm8350_get_volsw_2r,
 427                                wm8350_put_volsw_2r_vu, pre_amp_tlv),
 428        SOC_DOUBLE_R("Capture ZC Switch",
 429                     WM8350_LEFT_INPUT_VOLUME,
 430                     WM8350_RIGHT_INPUT_VOLUME, 13, 1, 0),
 431        SOC_SINGLE_TLV("Left Input Left Sidetone Volume",
 432                       WM8350_OUTPUT_LEFT_MIXER_VOLUME, 1, 7, 0, out_mix_tlv),
 433        SOC_SINGLE_TLV("Left Input Right Sidetone Volume",
 434                       WM8350_OUTPUT_LEFT_MIXER_VOLUME,
 435                       5, 7, 0, out_mix_tlv),
 436        SOC_SINGLE_TLV("Left Input Bypass Volume",
 437                       WM8350_OUTPUT_LEFT_MIXER_VOLUME,
 438                       9, 7, 0, out_mix_tlv),
 439        SOC_SINGLE_TLV("Right Input Left Sidetone Volume",
 440                       WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
 441                       1, 7, 0, out_mix_tlv),
 442        SOC_SINGLE_TLV("Right Input Right Sidetone Volume",
 443                       WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
 444                       5, 7, 0, out_mix_tlv),
 445        SOC_SINGLE_TLV("Right Input Bypass Volume",
 446                       WM8350_OUTPUT_RIGHT_MIXER_VOLUME,
 447                       13, 7, 0, out_mix_tlv),
 448        SOC_SINGLE("Left Input Mixer +20dB Switch",
 449                   WM8350_INPUT_MIXER_VOLUME_L, 0, 1, 0),
 450        SOC_SINGLE("Right Input Mixer +20dB Switch",
 451                   WM8350_INPUT_MIXER_VOLUME_R, 0, 1, 0),
 452        SOC_SINGLE_TLV("Out4 Capture Volume",
 453                       WM8350_INPUT_MIXER_VOLUME,
 454                       1, 7, 0, out_mix_tlv),
 455        SOC_DOUBLE_R_EXT_TLV("Out1 Playback Volume",
 456                                WM8350_LOUT1_VOLUME,
 457                                WM8350_ROUT1_VOLUME,
 458                                2, 63, 0, wm8350_get_volsw_2r,
 459                                wm8350_put_volsw_2r_vu, out_pga_tlv),
 460        SOC_DOUBLE_R("Out1 Playback ZC Switch",
 461                     WM8350_LOUT1_VOLUME,
 462                     WM8350_ROUT1_VOLUME, 13, 1, 0),
 463        SOC_DOUBLE_R_EXT_TLV("Out2 Playback Volume",
 464                                WM8350_LOUT2_VOLUME,
 465                                WM8350_ROUT2_VOLUME,
 466                                2, 63, 0, wm8350_get_volsw_2r,
 467                                wm8350_put_volsw_2r_vu, out_pga_tlv),
 468        SOC_DOUBLE_R("Out2 Playback ZC Switch", WM8350_LOUT2_VOLUME,
 469                     WM8350_ROUT2_VOLUME, 13, 1, 0),
 470        SOC_SINGLE("Out2 Right Invert Switch", WM8350_ROUT2_VOLUME, 10, 1, 0),
 471        SOC_SINGLE_TLV("Out2 Beep Volume", WM8350_BEEP_VOLUME,
 472                       5, 7, 0, out_mix_tlv),
 473
 474        SOC_DOUBLE_R("Out1 Playback Switch",
 475                     WM8350_LOUT1_VOLUME,
 476                     WM8350_ROUT1_VOLUME,
 477                     14, 1, 1),
 478        SOC_DOUBLE_R("Out2 Playback Switch",
 479                     WM8350_LOUT2_VOLUME,
 480                     WM8350_ROUT2_VOLUME,
 481                     14, 1, 1),
 482};
 483
 484/*
 485 * DAPM Controls
 486 */
 487
 488/* Left Playback Mixer */
 489static const struct snd_kcontrol_new wm8350_left_play_mixer_controls[] = {
 490        SOC_DAPM_SINGLE("Playback Switch",
 491                        WM8350_LEFT_MIXER_CONTROL, 11, 1, 0),
 492        SOC_DAPM_SINGLE("Left Bypass Switch",
 493                        WM8350_LEFT_MIXER_CONTROL, 2, 1, 0),
 494        SOC_DAPM_SINGLE("Right Playback Switch",
 495                        WM8350_LEFT_MIXER_CONTROL, 12, 1, 0),
 496        SOC_DAPM_SINGLE("Left Sidetone Switch",
 497                        WM8350_LEFT_MIXER_CONTROL, 0, 1, 0),
 498        SOC_DAPM_SINGLE("Right Sidetone Switch",
 499                        WM8350_LEFT_MIXER_CONTROL, 1, 1, 0),
 500};
 501
 502/* Right Playback Mixer */
 503static const struct snd_kcontrol_new wm8350_right_play_mixer_controls[] = {
 504        SOC_DAPM_SINGLE("Playback Switch",
 505                        WM8350_RIGHT_MIXER_CONTROL, 12, 1, 0),
 506        SOC_DAPM_SINGLE("Right Bypass Switch",
 507                        WM8350_RIGHT_MIXER_CONTROL, 3, 1, 0),
 508        SOC_DAPM_SINGLE("Left Playback Switch",
 509                        WM8350_RIGHT_MIXER_CONTROL, 11, 1, 0),
 510        SOC_DAPM_SINGLE("Left Sidetone Switch",
 511                        WM8350_RIGHT_MIXER_CONTROL, 0, 1, 0),
 512        SOC_DAPM_SINGLE("Right Sidetone Switch",
 513                        WM8350_RIGHT_MIXER_CONTROL, 1, 1, 0),
 514};
 515
 516/* Out4 Mixer */
 517static const struct snd_kcontrol_new wm8350_out4_mixer_controls[] = {
 518        SOC_DAPM_SINGLE("Right Playback Switch",
 519                        WM8350_OUT4_MIXER_CONTROL, 12, 1, 0),
 520        SOC_DAPM_SINGLE("Left Playback Switch",
 521                        WM8350_OUT4_MIXER_CONTROL, 11, 1, 0),
 522        SOC_DAPM_SINGLE("Right Capture Switch",
 523                        WM8350_OUT4_MIXER_CONTROL, 9, 1, 0),
 524        SOC_DAPM_SINGLE("Out3 Playback Switch",
 525                        WM8350_OUT4_MIXER_CONTROL, 2, 1, 0),
 526        SOC_DAPM_SINGLE("Right Mixer Switch",
 527                        WM8350_OUT4_MIXER_CONTROL, 1, 1, 0),
 528        SOC_DAPM_SINGLE("Left Mixer Switch",
 529                        WM8350_OUT4_MIXER_CONTROL, 0, 1, 0),
 530};
 531
 532/* Out3 Mixer */
 533static const struct snd_kcontrol_new wm8350_out3_mixer_controls[] = {
 534        SOC_DAPM_SINGLE("Left Playback Switch",
 535                        WM8350_OUT3_MIXER_CONTROL, 11, 1, 0),
 536        SOC_DAPM_SINGLE("Left Capture Switch",
 537                        WM8350_OUT3_MIXER_CONTROL, 8, 1, 0),
 538        SOC_DAPM_SINGLE("Out4 Playback Switch",
 539                        WM8350_OUT3_MIXER_CONTROL, 3, 1, 0),
 540        SOC_DAPM_SINGLE("Left Mixer Switch",
 541                        WM8350_OUT3_MIXER_CONTROL, 0, 1, 0),
 542};
 543
 544/* Left Input Mixer */
 545static const struct snd_kcontrol_new wm8350_left_capt_mixer_controls[] = {
 546        SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
 547                            WM8350_INPUT_MIXER_VOLUME_L, 1, 7, 0, out_mix_tlv),
 548        SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
 549                            WM8350_INPUT_MIXER_VOLUME_L, 9, 7, 0, out_mix_tlv),
 550        SOC_DAPM_SINGLE("PGA Capture Switch",
 551                        WM8350_LEFT_INPUT_VOLUME, 14, 1, 1),
 552};
 553
 554/* Right Input Mixer */
 555static const struct snd_kcontrol_new wm8350_right_capt_mixer_controls[] = {
 556        SOC_DAPM_SINGLE_TLV("L2 Capture Volume",
 557                            WM8350_INPUT_MIXER_VOLUME_R, 5, 7, 0, out_mix_tlv),
 558        SOC_DAPM_SINGLE_TLV("L3 Capture Volume",
 559                            WM8350_INPUT_MIXER_VOLUME_R, 13, 7, 0, out_mix_tlv),
 560        SOC_DAPM_SINGLE("PGA Capture Switch",
 561                        WM8350_RIGHT_INPUT_VOLUME, 14, 1, 1),
 562};
 563
 564/* Left Mic Mixer */
 565static const struct snd_kcontrol_new wm8350_left_mic_mixer_controls[] = {
 566        SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 1, 1, 0),
 567        SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 0, 1, 0),
 568        SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 2, 1, 0),
 569};
 570
 571/* Right Mic Mixer */
 572static const struct snd_kcontrol_new wm8350_right_mic_mixer_controls[] = {
 573        SOC_DAPM_SINGLE("INN Capture Switch", WM8350_INPUT_CONTROL, 9, 1, 0),
 574        SOC_DAPM_SINGLE("INP Capture Switch", WM8350_INPUT_CONTROL, 8, 1, 0),
 575        SOC_DAPM_SINGLE("IN2 Capture Switch", WM8350_INPUT_CONTROL, 10, 1, 0),
 576};
 577
 578/* Beep Switch */
 579static const struct snd_kcontrol_new wm8350_beep_switch_controls =
 580SOC_DAPM_SINGLE("Switch", WM8350_BEEP_VOLUME, 15, 1, 1);
 581
 582/* Out4 Capture Mux */
 583static const struct snd_kcontrol_new wm8350_out4_capture_controls =
 584SOC_DAPM_ENUM("Route", wm8350_enum[7]);
 585
 586static const struct snd_soc_dapm_widget wm8350_dapm_widgets[] = {
 587
 588        SND_SOC_DAPM_PGA("IN3R PGA", WM8350_POWER_MGMT_2, 11, 0, NULL, 0),
 589        SND_SOC_DAPM_PGA("IN3L PGA", WM8350_POWER_MGMT_2, 10, 0, NULL, 0),
 590        SND_SOC_DAPM_PGA_E("Right Out2 PGA", WM8350_POWER_MGMT_3, 3, 0, NULL,
 591                           0, pga_event,
 592                           SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 593        SND_SOC_DAPM_PGA_E("Left Out2 PGA", WM8350_POWER_MGMT_3, 2, 0, NULL, 0,
 594                           pga_event,
 595                           SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 596        SND_SOC_DAPM_PGA_E("Right Out1 PGA", WM8350_POWER_MGMT_3, 1, 0, NULL,
 597                           0, pga_event,
 598                           SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 599        SND_SOC_DAPM_PGA_E("Left Out1 PGA", WM8350_POWER_MGMT_3, 0, 0, NULL, 0,
 600                           pga_event,
 601                           SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 602
 603        SND_SOC_DAPM_MIXER("Right Capture Mixer", WM8350_POWER_MGMT_2,
 604                           7, 0, &wm8350_right_capt_mixer_controls[0],
 605                           ARRAY_SIZE(wm8350_right_capt_mixer_controls)),
 606
 607        SND_SOC_DAPM_MIXER("Left Capture Mixer", WM8350_POWER_MGMT_2,
 608                           6, 0, &wm8350_left_capt_mixer_controls[0],
 609                           ARRAY_SIZE(wm8350_left_capt_mixer_controls)),
 610
 611        SND_SOC_DAPM_MIXER("Out4 Mixer", WM8350_POWER_MGMT_2, 5, 0,
 612                           &wm8350_out4_mixer_controls[0],
 613                           ARRAY_SIZE(wm8350_out4_mixer_controls)),
 614
 615        SND_SOC_DAPM_MIXER("Out3 Mixer", WM8350_POWER_MGMT_2, 4, 0,
 616                           &wm8350_out3_mixer_controls[0],
 617                           ARRAY_SIZE(wm8350_out3_mixer_controls)),
 618
 619        SND_SOC_DAPM_MIXER("Right Playback Mixer", WM8350_POWER_MGMT_2, 1, 0,
 620                           &wm8350_right_play_mixer_controls[0],
 621                           ARRAY_SIZE(wm8350_right_play_mixer_controls)),
 622
 623        SND_SOC_DAPM_MIXER("Left Playback Mixer", WM8350_POWER_MGMT_2, 0, 0,
 624                           &wm8350_left_play_mixer_controls[0],
 625                           ARRAY_SIZE(wm8350_left_play_mixer_controls)),
 626
 627        SND_SOC_DAPM_MIXER("Left Mic Mixer", WM8350_POWER_MGMT_2, 8, 0,
 628                           &wm8350_left_mic_mixer_controls[0],
 629                           ARRAY_SIZE(wm8350_left_mic_mixer_controls)),
 630
 631        SND_SOC_DAPM_MIXER("Right Mic Mixer", WM8350_POWER_MGMT_2, 9, 0,
 632                           &wm8350_right_mic_mixer_controls[0],
 633                           ARRAY_SIZE(wm8350_right_mic_mixer_controls)),
 634
 635        /* virtual mixer for Beep and Out2R */
 636        SND_SOC_DAPM_MIXER("Out2 Mixer", SND_SOC_NOPM, 0, 0, NULL, 0),
 637
 638        SND_SOC_DAPM_SWITCH("Beep", WM8350_POWER_MGMT_3, 7, 0,
 639                            &wm8350_beep_switch_controls),
 640
 641        SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
 642                         WM8350_POWER_MGMT_4, 3, 0),
 643        SND_SOC_DAPM_ADC("Left ADC", "Left Capture",
 644                         WM8350_POWER_MGMT_4, 2, 0),
 645        SND_SOC_DAPM_DAC("Right DAC", "Right Playback",
 646                         WM8350_POWER_MGMT_4, 5, 0),
 647        SND_SOC_DAPM_DAC("Left DAC", "Left Playback",
 648                         WM8350_POWER_MGMT_4, 4, 0),
 649
 650        SND_SOC_DAPM_MICBIAS("Mic Bias", WM8350_POWER_MGMT_1, 4, 0),
 651
 652        SND_SOC_DAPM_MUX("Out4 Capture Channel", SND_SOC_NOPM, 0, 0,
 653                         &wm8350_out4_capture_controls),
 654
 655        SND_SOC_DAPM_OUTPUT("OUT1R"),
 656        SND_SOC_DAPM_OUTPUT("OUT1L"),
 657        SND_SOC_DAPM_OUTPUT("OUT2R"),
 658        SND_SOC_DAPM_OUTPUT("OUT2L"),
 659        SND_SOC_DAPM_OUTPUT("OUT3"),
 660        SND_SOC_DAPM_OUTPUT("OUT4"),
 661
 662        SND_SOC_DAPM_INPUT("IN1RN"),
 663        SND_SOC_DAPM_INPUT("IN1RP"),
 664        SND_SOC_DAPM_INPUT("IN2R"),
 665        SND_SOC_DAPM_INPUT("IN1LP"),
 666        SND_SOC_DAPM_INPUT("IN1LN"),
 667        SND_SOC_DAPM_INPUT("IN2L"),
 668        SND_SOC_DAPM_INPUT("IN3R"),
 669        SND_SOC_DAPM_INPUT("IN3L"),
 670};
 671
 672static const struct snd_soc_dapm_route wm8350_dapm_routes[] = {
 673
 674        /* left playback mixer */
 675        {"Left Playback Mixer", "Playback Switch", "Left DAC"},
 676        {"Left Playback Mixer", "Left Bypass Switch", "IN3L PGA"},
 677        {"Left Playback Mixer", "Right Playback Switch", "Right DAC"},
 678        {"Left Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
 679        {"Left Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
 680
 681        /* right playback mixer */
 682        {"Right Playback Mixer", "Playback Switch", "Right DAC"},
 683        {"Right Playback Mixer", "Right Bypass Switch", "IN3R PGA"},
 684        {"Right Playback Mixer", "Left Playback Switch", "Left DAC"},
 685        {"Right Playback Mixer", "Left Sidetone Switch", "Left Mic Mixer"},
 686        {"Right Playback Mixer", "Right Sidetone Switch", "Right Mic Mixer"},
 687
 688        /* out4 playback mixer */
 689        {"Out4 Mixer", "Right Playback Switch", "Right DAC"},
 690        {"Out4 Mixer", "Left Playback Switch", "Left DAC"},
 691        {"Out4 Mixer", "Right Capture Switch", "Right Capture Mixer"},
 692        {"Out4 Mixer", "Out3 Playback Switch", "Out3 Mixer"},
 693        {"Out4 Mixer", "Right Mixer Switch", "Right Playback Mixer"},
 694        {"Out4 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
 695        {"OUT4", NULL, "Out4 Mixer"},
 696
 697        /* out3 playback mixer */
 698        {"Out3 Mixer", "Left Playback Switch", "Left DAC"},
 699        {"Out3 Mixer", "Left Capture Switch", "Left Capture Mixer"},
 700        {"Out3 Mixer", "Left Mixer Switch", "Left Playback Mixer"},
 701        {"Out3 Mixer", "Out4 Playback Switch", "Out4 Mixer"},
 702        {"OUT3", NULL, "Out3 Mixer"},
 703
 704        /* out2 */
 705        {"Right Out2 PGA", NULL, "Right Playback Mixer"},
 706        {"Left Out2 PGA", NULL, "Left Playback Mixer"},
 707        {"OUT2L", NULL, "Left Out2 PGA"},
 708        {"OUT2R", NULL, "Right Out2 PGA"},
 709
 710        /* out1 */
 711        {"Right Out1 PGA", NULL, "Right Playback Mixer"},
 712        {"Left Out1 PGA", NULL, "Left Playback Mixer"},
 713        {"OUT1L", NULL, "Left Out1 PGA"},
 714        {"OUT1R", NULL, "Right Out1 PGA"},
 715
 716        /* ADCs */
 717        {"Left ADC", NULL, "Left Capture Mixer"},
 718        {"Right ADC", NULL, "Right Capture Mixer"},
 719
 720        /* Left capture mixer */
 721        {"Left Capture Mixer", "L2 Capture Volume", "IN2L"},
 722        {"Left Capture Mixer", "L3 Capture Volume", "IN3L PGA"},
 723        {"Left Capture Mixer", "PGA Capture Switch", "Left Mic Mixer"},
 724        {"Left Capture Mixer", NULL, "Out4 Capture Channel"},
 725
 726        /* Right capture mixer */
 727        {"Right Capture Mixer", "L2 Capture Volume", "IN2R"},
 728        {"Right Capture Mixer", "L3 Capture Volume", "IN3R PGA"},
 729        {"Right Capture Mixer", "PGA Capture Switch", "Right Mic Mixer"},
 730        {"Right Capture Mixer", NULL, "Out4 Capture Channel"},
 731
 732        /* L3 Inputs */
 733        {"IN3L PGA", NULL, "IN3L"},
 734        {"IN3R PGA", NULL, "IN3R"},
 735
 736        /* Left Mic mixer */
 737        {"Left Mic Mixer", "INN Capture Switch", "IN1LN"},
 738        {"Left Mic Mixer", "INP Capture Switch", "IN1LP"},
 739        {"Left Mic Mixer", "IN2 Capture Switch", "IN2L"},
 740
 741        /* Right Mic mixer */
 742        {"Right Mic Mixer", "INN Capture Switch", "IN1RN"},
 743        {"Right Mic Mixer", "INP Capture Switch", "IN1RP"},
 744        {"Right Mic Mixer", "IN2 Capture Switch", "IN2R"},
 745
 746        /* out 4 capture */
 747        {"Out4 Capture Channel", NULL, "Out4 Mixer"},
 748
 749        /* Beep */
 750        {"Beep", NULL, "IN3R PGA"},
 751};
 752
 753static int wm8350_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 754                                 int clk_id, unsigned int freq, int dir)
 755{
 756        struct snd_soc_codec *codec = codec_dai->codec;
 757        struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
 758        struct wm8350 *wm8350 = wm8350_data->wm8350;
 759        u16 fll_4;
 760
 761        switch (clk_id) {
 762        case WM8350_MCLK_SEL_MCLK:
 763                wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_1,
 764                                  WM8350_MCLK_SEL);
 765                break;
 766        case WM8350_MCLK_SEL_PLL_MCLK:
 767        case WM8350_MCLK_SEL_PLL_DAC:
 768        case WM8350_MCLK_SEL_PLL_ADC:
 769        case WM8350_MCLK_SEL_PLL_32K:
 770                wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_1,
 771                                WM8350_MCLK_SEL);
 772                fll_4 = snd_soc_read(codec, WM8350_FLL_CONTROL_4) &
 773                    ~WM8350_FLL_CLK_SRC_MASK;
 774                snd_soc_write(codec, WM8350_FLL_CONTROL_4, fll_4 | clk_id);
 775                break;
 776        }
 777
 778        /* MCLK direction */
 779        if (dir == SND_SOC_CLOCK_OUT)
 780                wm8350_set_bits(wm8350, WM8350_CLOCK_CONTROL_2,
 781                                WM8350_MCLK_DIR);
 782        else
 783                wm8350_clear_bits(wm8350, WM8350_CLOCK_CONTROL_2,
 784                                  WM8350_MCLK_DIR);
 785
 786        return 0;
 787}
 788
 789static int wm8350_set_clkdiv(struct snd_soc_dai *codec_dai, int div_id, int div)
 790{
 791        struct snd_soc_codec *codec = codec_dai->codec;
 792        u16 val;
 793
 794        switch (div_id) {
 795        case WM8350_ADC_CLKDIV:
 796                val = snd_soc_read(codec, WM8350_ADC_DIVIDER) &
 797                    ~WM8350_ADC_CLKDIV_MASK;
 798                snd_soc_write(codec, WM8350_ADC_DIVIDER, val | div);
 799                break;
 800        case WM8350_DAC_CLKDIV:
 801                val = snd_soc_read(codec, WM8350_DAC_CLOCK_CONTROL) &
 802                    ~WM8350_DAC_CLKDIV_MASK;
 803                snd_soc_write(codec, WM8350_DAC_CLOCK_CONTROL, val | div);
 804                break;
 805        case WM8350_BCLK_CLKDIV:
 806                val = snd_soc_read(codec, WM8350_CLOCK_CONTROL_1) &
 807                    ~WM8350_BCLK_DIV_MASK;
 808                snd_soc_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
 809                break;
 810        case WM8350_OPCLK_CLKDIV:
 811                val = snd_soc_read(codec, WM8350_CLOCK_CONTROL_1) &
 812                    ~WM8350_OPCLK_DIV_MASK;
 813                snd_soc_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
 814                break;
 815        case WM8350_SYS_CLKDIV:
 816                val = snd_soc_read(codec, WM8350_CLOCK_CONTROL_1) &
 817                    ~WM8350_MCLK_DIV_MASK;
 818                snd_soc_write(codec, WM8350_CLOCK_CONTROL_1, val | div);
 819                break;
 820        case WM8350_DACLR_CLKDIV:
 821                val = snd_soc_read(codec, WM8350_DAC_LR_RATE) &
 822                    ~WM8350_DACLRC_RATE_MASK;
 823                snd_soc_write(codec, WM8350_DAC_LR_RATE, val | div);
 824                break;
 825        case WM8350_ADCLR_CLKDIV:
 826                val = snd_soc_read(codec, WM8350_ADC_LR_RATE) &
 827                    ~WM8350_ADCLRC_RATE_MASK;
 828                snd_soc_write(codec, WM8350_ADC_LR_RATE, val | div);
 829                break;
 830        default:
 831                return -EINVAL;
 832        }
 833
 834        return 0;
 835}
 836
 837static int wm8350_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 838{
 839        struct snd_soc_codec *codec = codec_dai->codec;
 840        u16 iface = snd_soc_read(codec, WM8350_AI_FORMATING) &
 841            ~(WM8350_AIF_BCLK_INV | WM8350_AIF_LRCLK_INV | WM8350_AIF_FMT_MASK);
 842        u16 master = snd_soc_read(codec, WM8350_AI_DAC_CONTROL) &
 843            ~WM8350_BCLK_MSTR;
 844        u16 dac_lrc = snd_soc_read(codec, WM8350_DAC_LR_RATE) &
 845            ~WM8350_DACLRC_ENA;
 846        u16 adc_lrc = snd_soc_read(codec, WM8350_ADC_LR_RATE) &
 847            ~WM8350_ADCLRC_ENA;
 848
 849        /* set master/slave audio interface */
 850        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 851        case SND_SOC_DAIFMT_CBM_CFM:
 852                master |= WM8350_BCLK_MSTR;
 853                dac_lrc |= WM8350_DACLRC_ENA;
 854                adc_lrc |= WM8350_ADCLRC_ENA;
 855                break;
 856        case SND_SOC_DAIFMT_CBS_CFS:
 857                break;
 858        default:
 859                return -EINVAL;
 860        }
 861
 862        /* interface format */
 863        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 864        case SND_SOC_DAIFMT_I2S:
 865                iface |= 0x2 << 8;
 866                break;
 867        case SND_SOC_DAIFMT_RIGHT_J:
 868                break;
 869        case SND_SOC_DAIFMT_LEFT_J:
 870                iface |= 0x1 << 8;
 871                break;
 872        case SND_SOC_DAIFMT_DSP_A:
 873                iface |= 0x3 << 8;
 874                break;
 875        case SND_SOC_DAIFMT_DSP_B:
 876                iface |= 0x3 << 8 | WM8350_AIF_LRCLK_INV;
 877                break;
 878        default:
 879                return -EINVAL;
 880        }
 881
 882        /* clock inversion */
 883        switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 884        case SND_SOC_DAIFMT_NB_NF:
 885                break;
 886        case SND_SOC_DAIFMT_IB_IF:
 887                iface |= WM8350_AIF_LRCLK_INV | WM8350_AIF_BCLK_INV;
 888                break;
 889        case SND_SOC_DAIFMT_IB_NF:
 890                iface |= WM8350_AIF_BCLK_INV;
 891                break;
 892        case SND_SOC_DAIFMT_NB_IF:
 893                iface |= WM8350_AIF_LRCLK_INV;
 894                break;
 895        default:
 896                return -EINVAL;
 897        }
 898
 899        snd_soc_write(codec, WM8350_AI_FORMATING, iface);
 900        snd_soc_write(codec, WM8350_AI_DAC_CONTROL, master);
 901        snd_soc_write(codec, WM8350_DAC_LR_RATE, dac_lrc);
 902        snd_soc_write(codec, WM8350_ADC_LR_RATE, adc_lrc);
 903        return 0;
 904}
 905
 906static int wm8350_pcm_hw_params(struct snd_pcm_substream *substream,
 907                                struct snd_pcm_hw_params *params,
 908                                struct snd_soc_dai *codec_dai)
 909{
 910        struct snd_soc_codec *codec = codec_dai->codec;
 911        struct wm8350_data *wm8350_data = snd_soc_codec_get_drvdata(codec);
 912        struct wm8350 *wm8350 = wm8350_data->wm8350;
 913        u16 iface = snd_soc_read(codec, WM8350_AI_FORMATING) &
 914            ~WM8350_AIF_WL_MASK;
 915
 916        /* bit size */
 917        switch (params_width(params)) {
 918        case 16:
 919                break;
 920        case 20:
 921                iface |= 0x1 << 10;
 922                break;
 923        case 24:
 924                iface |= 0x2 << 10;
 925                break;
 926        case 32:
 927                iface |= 0x3 << 10;
 928                break;
 929        }
 930
 931        snd_soc_write(codec, WM8350_AI_FORMATING, iface);
 932
 933        /* The sloping stopband filter is recommended for use with
 934         * lower sample rates to improve performance.
 935         */
 936        if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 937                if (params_rate(params) < 24000)
 938                        wm8350_set_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
 939                                        WM8350_DAC_SB_FILT);
 940                else
 941                        wm8350_clear_bits(wm8350, WM8350_DAC_MUTE_VOLUME,
 942                                          WM8350_DAC_SB_FILT);
 943        }
 944
 945        return 0;
 946}
 947
 948static int wm8350_mute(struct snd_soc_dai *dai, int mute)
 949{
 950        struct snd_soc_codec *codec = dai->codec;
 951        unsigned int val;
 952
 953        if (mute)
 954                val = WM8350_DAC_MUTE_ENA;
 955        else
 956                val = 0;
 957
 958        snd_soc_update_bits(codec, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA, val);
 959
 960        return 0;
 961}
 962
 963/* FLL divisors */
 964struct _fll_div {
 965        int div;                /* FLL_OUTDIV */
 966        int n;
 967        int k;
 968        int ratio;              /* FLL_FRATIO */
 969};
 970
 971/* The size in bits of the fll divide multiplied by 10
 972 * to allow rounding later */
 973#define FIXED_FLL_SIZE ((1 << 16) * 10)
 974
 975static inline int fll_factors(struct _fll_div *fll_div, unsigned int input,
 976                              unsigned int output)
 977{
 978        u64 Kpart;
 979        unsigned int t1, t2, K, Nmod;
 980
 981        if (output >= 2815250 && output <= 3125000)
 982                fll_div->div = 0x4;
 983        else if (output >= 5625000 && output <= 6250000)
 984                fll_div->div = 0x3;
 985        else if (output >= 11250000 && output <= 12500000)
 986                fll_div->div = 0x2;
 987        else if (output >= 22500000 && output <= 25000000)
 988                fll_div->div = 0x1;
 989        else {
 990                printk(KERN_ERR "wm8350: fll freq %d out of range\n", output);
 991                return -EINVAL;
 992        }
 993
 994        if (input > 48000)
 995                fll_div->ratio = 1;
 996        else
 997                fll_div->ratio = 8;
 998
 999        t1 = output * (1 << (fll_div->div + 1));
1000        t2 = input * fll_div->ratio;
1001
1002        fll_div->n = t1 / t2;
1003        Nmod = t1 % t2;
1004
1005        if (Nmod) {
1006                Kpart = FIXED_FLL_SIZE * (long long)Nmod;
1007                do_div(Kpart, t2);
1008                K = Kpart & 0xFFFFFFFF;
1009
1010                /* Check if we need to round */
1011                if ((K % 10) >= 5)
1012                        K += 5;
1013
1014                /* Move down to proper range now rounding is done */
1015                K /= 10;
1016                fll_div->k = K;
1017        } else
1018                fll_div->k = 0;
1019
1020        return 0;
1021}
1022
1023static int wm8350_set_fll(struct snd_soc_dai *codec_dai,
1024                          int pll_id, int source, unsigned int freq_in,
1025                          unsigned int freq_out)
1026{
1027        struct snd_soc_codec *codec = codec_dai->codec;
1028        struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1029        struct wm8350 *wm8350 = priv->wm8350;
1030        struct _fll_div fll_div;
1031        int ret = 0;
1032        u16 fll_1, fll_4;
1033
1034        if (freq_in == priv->fll_freq_in && freq_out == priv->fll_freq_out)
1035                return 0;
1036
1037        /* power down FLL - we need to do this for reconfiguration */
1038        wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
1039                          WM8350_FLL_ENA | WM8350_FLL_OSC_ENA);
1040
1041        if (freq_out == 0 || freq_in == 0)
1042                return ret;
1043
1044        ret = fll_factors(&fll_div, freq_in, freq_out);
1045        if (ret < 0)
1046                return ret;
1047        dev_dbg(wm8350->dev,
1048                "FLL in %u FLL out %u N 0x%x K 0x%x div %d ratio %d",
1049                freq_in, freq_out, fll_div.n, fll_div.k, fll_div.div,
1050                fll_div.ratio);
1051
1052        /* set up N.K & dividers */
1053        fll_1 = snd_soc_read(codec, WM8350_FLL_CONTROL_1) &
1054            ~(WM8350_FLL_OUTDIV_MASK | WM8350_FLL_RSP_RATE_MASK | 0xc000);
1055        snd_soc_write(codec, WM8350_FLL_CONTROL_1,
1056                           fll_1 | (fll_div.div << 8) | 0x50);
1057        snd_soc_write(codec, WM8350_FLL_CONTROL_2,
1058                           (fll_div.ratio << 11) | (fll_div.
1059                                                    n & WM8350_FLL_N_MASK));
1060        snd_soc_write(codec, WM8350_FLL_CONTROL_3, fll_div.k);
1061        fll_4 = snd_soc_read(codec, WM8350_FLL_CONTROL_4) &
1062            ~(WM8350_FLL_FRAC | WM8350_FLL_SLOW_LOCK_REF);
1063        snd_soc_write(codec, WM8350_FLL_CONTROL_4,
1064                           fll_4 | (fll_div.k ? WM8350_FLL_FRAC : 0) |
1065                           (fll_div.ratio == 8 ? WM8350_FLL_SLOW_LOCK_REF : 0));
1066
1067        /* power FLL on */
1068        wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_OSC_ENA);
1069        wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_FLL_ENA);
1070
1071        priv->fll_freq_out = freq_out;
1072        priv->fll_freq_in = freq_in;
1073
1074        return 0;
1075}
1076
1077static int wm8350_set_bias_level(struct snd_soc_codec *codec,
1078                                 enum snd_soc_bias_level level)
1079{
1080        struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1081        struct wm8350 *wm8350 = priv->wm8350;
1082        struct wm8350_audio_platform_data *platform =
1083                wm8350->codec.platform_data;
1084        u16 pm1;
1085        int ret;
1086
1087        switch (level) {
1088        case SND_SOC_BIAS_ON:
1089                pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1090                    ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1091                wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1092                                 pm1 | WM8350_VMID_50K |
1093                                 platform->codec_current_on << 14);
1094                break;
1095
1096        case SND_SOC_BIAS_PREPARE:
1097                pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1);
1098                pm1 &= ~WM8350_VMID_MASK;
1099                wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1100                                 pm1 | WM8350_VMID_50K);
1101                break;
1102
1103        case SND_SOC_BIAS_STANDBY:
1104                if (snd_soc_codec_get_bias_level(codec) == SND_SOC_BIAS_OFF) {
1105                        ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies),
1106                                                    priv->supplies);
1107                        if (ret != 0)
1108                                return ret;
1109
1110                        /* Enable the system clock */
1111                        wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4,
1112                                        WM8350_SYSCLK_ENA);
1113
1114                        /* mute DAC & outputs */
1115                        wm8350_set_bits(wm8350, WM8350_DAC_MUTE,
1116                                        WM8350_DAC_MUTE_ENA);
1117
1118                        /* discharge cap memory */
1119                        wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1120                                         platform->dis_out1 |
1121                                         (platform->dis_out2 << 2) |
1122                                         (platform->dis_out3 << 4) |
1123                                         (platform->dis_out4 << 6));
1124
1125                        /* wait for discharge */
1126                        schedule_timeout_interruptible(msecs_to_jiffies
1127                                                       (platform->
1128                                                        cap_discharge_msecs));
1129
1130                        /* enable antipop */
1131                        wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1132                                         (platform->vmid_s_curve << 8));
1133
1134                        /* ramp up vmid */
1135                        wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1136                                         (platform->
1137                                          codec_current_charge << 14) |
1138                                         WM8350_VMID_5K | WM8350_VMIDEN |
1139                                         WM8350_VBUFEN);
1140
1141                        /* wait for vmid */
1142                        schedule_timeout_interruptible(msecs_to_jiffies
1143                                                       (platform->
1144                                                        vmid_charge_msecs));
1145
1146                        /* turn on vmid 300k  */
1147                        pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1148                            ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1149                        pm1 |= WM8350_VMID_300K |
1150                                (platform->codec_current_standby << 14);
1151                        wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1152                                         pm1);
1153
1154
1155                        /* enable analogue bias */
1156                        pm1 |= WM8350_BIASEN;
1157                        wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1158
1159                        /* disable antipop */
1160                        wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
1161
1162                } else {
1163                        /* turn on vmid 300k and reduce current */
1164                        pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1165                            ~(WM8350_VMID_MASK | WM8350_CODEC_ISEL_MASK);
1166                        wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1167                                         pm1 | WM8350_VMID_300K |
1168                                         (platform->
1169                                          codec_current_standby << 14));
1170
1171                }
1172                break;
1173
1174        case SND_SOC_BIAS_OFF:
1175
1176                /* mute DAC & enable outputs */
1177                wm8350_set_bits(wm8350, WM8350_DAC_MUTE, WM8350_DAC_MUTE_ENA);
1178
1179                wm8350_set_bits(wm8350, WM8350_POWER_MGMT_3,
1180                                WM8350_OUT1L_ENA | WM8350_OUT1R_ENA |
1181                                WM8350_OUT2L_ENA | WM8350_OUT2R_ENA);
1182
1183                /* enable anti pop S curve */
1184                wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1185                                 (platform->vmid_s_curve << 8));
1186
1187                /* turn off vmid  */
1188                pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1189                    ~WM8350_VMIDEN;
1190                wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1191
1192                /* wait */
1193                schedule_timeout_interruptible(msecs_to_jiffies
1194                                               (platform->
1195                                                vmid_discharge_msecs));
1196
1197                wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL,
1198                                 (platform->vmid_s_curve << 8) |
1199                                 platform->dis_out1 |
1200                                 (platform->dis_out2 << 2) |
1201                                 (platform->dis_out3 << 4) |
1202                                 (platform->dis_out4 << 6));
1203
1204                /* turn off VBuf and drain */
1205                pm1 = wm8350_reg_read(wm8350, WM8350_POWER_MGMT_1) &
1206                    ~(WM8350_VBUFEN | WM8350_VMID_MASK);
1207                wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1,
1208                                 pm1 | WM8350_OUTPUT_DRAIN_EN);
1209
1210                /* wait */
1211                schedule_timeout_interruptible(msecs_to_jiffies
1212                                               (platform->drain_msecs));
1213
1214                pm1 &= ~WM8350_BIASEN;
1215                wm8350_reg_write(wm8350, WM8350_POWER_MGMT_1, pm1);
1216
1217                /* disable anti-pop */
1218                wm8350_reg_write(wm8350, WM8350_ANTI_POP_CONTROL, 0);
1219
1220                wm8350_clear_bits(wm8350, WM8350_LOUT1_VOLUME,
1221                                  WM8350_OUT1L_ENA);
1222                wm8350_clear_bits(wm8350, WM8350_ROUT1_VOLUME,
1223                                  WM8350_OUT1R_ENA);
1224                wm8350_clear_bits(wm8350, WM8350_LOUT2_VOLUME,
1225                                  WM8350_OUT2L_ENA);
1226                wm8350_clear_bits(wm8350, WM8350_ROUT2_VOLUME,
1227                                  WM8350_OUT2R_ENA);
1228
1229                /* disable clock gen */
1230                wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4,
1231                                  WM8350_SYSCLK_ENA);
1232
1233                regulator_bulk_disable(ARRAY_SIZE(priv->supplies),
1234                                       priv->supplies);
1235                break;
1236        }
1237        return 0;
1238}
1239
1240static void wm8350_hp_work(struct wm8350_data *priv,
1241                           struct wm8350_jack_data *jack,
1242                           u16 mask)
1243{
1244        struct wm8350 *wm8350 = priv->wm8350;
1245        u16 reg;
1246        int report;
1247
1248        reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1249        if (reg & mask)
1250                report = jack->report;
1251        else
1252                report = 0;
1253
1254        snd_soc_jack_report(jack->jack, report, jack->report);
1255
1256}
1257
1258static void wm8350_hpl_work(struct work_struct *work)
1259{
1260        struct wm8350_data *priv =
1261            container_of(work, struct wm8350_data, hpl.work.work);
1262
1263        wm8350_hp_work(priv, &priv->hpl, WM8350_JACK_L_LVL);
1264}
1265
1266static void wm8350_hpr_work(struct work_struct *work)
1267{
1268        struct wm8350_data *priv =
1269            container_of(work, struct wm8350_data, hpr.work.work);
1270        
1271        wm8350_hp_work(priv, &priv->hpr, WM8350_JACK_R_LVL);
1272}
1273
1274static irqreturn_t wm8350_hpl_jack_handler(int irq, void *data)
1275{
1276        struct wm8350_data *priv = data;
1277        struct wm8350 *wm8350 = priv->wm8350;
1278
1279#ifndef CONFIG_SND_SOC_WM8350_MODULE
1280        trace_snd_soc_jack_irq("WM8350 HPL");
1281#endif
1282
1283        if (device_may_wakeup(wm8350->dev))
1284                pm_wakeup_event(wm8350->dev, 250);
1285
1286        queue_delayed_work(system_power_efficient_wq,
1287                           &priv->hpl.work, msecs_to_jiffies(200));
1288
1289        return IRQ_HANDLED;
1290}
1291
1292static irqreturn_t wm8350_hpr_jack_handler(int irq, void *data)
1293{
1294        struct wm8350_data *priv = data;
1295        struct wm8350 *wm8350 = priv->wm8350;
1296
1297#ifndef CONFIG_SND_SOC_WM8350_MODULE
1298        trace_snd_soc_jack_irq("WM8350 HPR");
1299#endif
1300
1301        if (device_may_wakeup(wm8350->dev))
1302                pm_wakeup_event(wm8350->dev, 250);
1303
1304        queue_delayed_work(system_power_efficient_wq,
1305                           &priv->hpr.work, msecs_to_jiffies(200));
1306
1307        return IRQ_HANDLED;
1308}
1309
1310/**
1311 * wm8350_hp_jack_detect - Enable headphone jack detection.
1312 *
1313 * @codec:  WM8350 codec
1314 * @which:  left or right jack detect signal
1315 * @jack:   jack to report detection events on
1316 * @report: value to report
1317 *
1318 * Enables the headphone jack detection of the WM8350.  If no report
1319 * is specified then detection is disabled.
1320 */
1321int wm8350_hp_jack_detect(struct snd_soc_codec *codec, enum wm8350_jack which,
1322                          struct snd_soc_jack *jack, int report)
1323{
1324        struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1325        struct wm8350 *wm8350 = priv->wm8350;
1326        int ena;
1327
1328        switch (which) {
1329        case WM8350_JDL:
1330                priv->hpl.jack = jack;
1331                priv->hpl.report = report;
1332                ena = WM8350_JDL_ENA;
1333                break;
1334
1335        case WM8350_JDR:
1336                priv->hpr.jack = jack;
1337                priv->hpr.report = report;
1338                ena = WM8350_JDR_ENA;
1339                break;
1340
1341        default:
1342                return -EINVAL;
1343        }
1344
1345        if (report) {
1346                wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1347                wm8350_set_bits(wm8350, WM8350_JACK_DETECT, ena);
1348        } else {
1349                wm8350_clear_bits(wm8350, WM8350_JACK_DETECT, ena);
1350        }
1351
1352        /* Sync status */
1353        switch (which) {
1354        case WM8350_JDL:
1355                wm8350_hpl_jack_handler(0, priv);
1356                break;
1357        case WM8350_JDR:
1358                wm8350_hpr_jack_handler(0, priv);
1359                break;
1360        }
1361
1362        return 0;
1363}
1364EXPORT_SYMBOL_GPL(wm8350_hp_jack_detect);
1365
1366static irqreturn_t wm8350_mic_handler(int irq, void *data)
1367{
1368        struct wm8350_data *priv = data;
1369        struct wm8350 *wm8350 = priv->wm8350;
1370        u16 reg;
1371        int report = 0;
1372
1373#ifndef CONFIG_SND_SOC_WM8350_MODULE
1374        trace_snd_soc_jack_irq("WM8350 mic");
1375#endif
1376
1377        reg = wm8350_reg_read(wm8350, WM8350_JACK_PIN_STATUS);
1378        if (reg & WM8350_JACK_MICSCD_LVL)
1379                report |= priv->mic.short_report;
1380        if (reg & WM8350_JACK_MICSD_LVL)
1381                report |= priv->mic.report;
1382
1383        snd_soc_jack_report(priv->mic.jack, report,
1384                            priv->mic.report | priv->mic.short_report);
1385
1386        return IRQ_HANDLED;
1387}
1388
1389/**
1390 * wm8350_mic_jack_detect - Enable microphone jack detection.
1391 *
1392 * @codec:         WM8350 codec
1393 * @jack:          jack to report detection events on
1394 * @detect_report: value to report when presence detected
1395 * @short_report:  value to report when microphone short detected
1396 *
1397 * Enables the microphone jack detection of the WM8350.  If both reports
1398 * are specified as zero then detection is disabled.
1399 */
1400int wm8350_mic_jack_detect(struct snd_soc_codec *codec,
1401                           struct snd_soc_jack *jack,
1402                           int detect_report, int short_report)
1403{
1404        struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1405        struct wm8350 *wm8350 = priv->wm8350;
1406
1407        priv->mic.jack = jack;
1408        priv->mic.report = detect_report;
1409        priv->mic.short_report = short_report;
1410
1411        if (detect_report || short_report) {
1412                wm8350_set_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1413                wm8350_set_bits(wm8350, WM8350_POWER_MGMT_1,
1414                                WM8350_MIC_DET_ENA);
1415        } else {
1416                wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_1,
1417                                  WM8350_MIC_DET_ENA);
1418        }
1419
1420        return 0;
1421}
1422EXPORT_SYMBOL_GPL(wm8350_mic_jack_detect);
1423
1424#define WM8350_RATES (SNDRV_PCM_RATE_8000_96000)
1425
1426#define WM8350_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
1427                        SNDRV_PCM_FMTBIT_S20_3LE |\
1428                        SNDRV_PCM_FMTBIT_S24_LE)
1429
1430static const struct snd_soc_dai_ops wm8350_dai_ops = {
1431         .hw_params     = wm8350_pcm_hw_params,
1432         .digital_mute  = wm8350_mute,
1433         .set_fmt       = wm8350_set_dai_fmt,
1434         .set_sysclk    = wm8350_set_dai_sysclk,
1435         .set_pll       = wm8350_set_fll,
1436         .set_clkdiv    = wm8350_set_clkdiv,
1437};
1438
1439static struct snd_soc_dai_driver wm8350_dai = {
1440        .name = "wm8350-hifi",
1441        .playback = {
1442                .stream_name = "Playback",
1443                .channels_min = 1,
1444                .channels_max = 2,
1445                .rates = WM8350_RATES,
1446                .formats = WM8350_FORMATS,
1447        },
1448        .capture = {
1449                 .stream_name = "Capture",
1450                 .channels_min = 1,
1451                 .channels_max = 2,
1452                 .rates = WM8350_RATES,
1453                 .formats = WM8350_FORMATS,
1454         },
1455        .ops = &wm8350_dai_ops,
1456};
1457
1458static  int wm8350_codec_probe(struct snd_soc_codec *codec)
1459{
1460        struct wm8350 *wm8350 = dev_get_platdata(codec->dev);
1461        struct wm8350_data *priv;
1462        struct wm8350_output *out1;
1463        struct wm8350_output *out2;
1464        int ret, i;
1465
1466        if (wm8350->codec.platform_data == NULL) {
1467                dev_err(codec->dev, "No audio platform data supplied\n");
1468                return -EINVAL;
1469        }
1470
1471        priv = devm_kzalloc(codec->dev, sizeof(struct wm8350_data),
1472                            GFP_KERNEL);
1473        if (priv == NULL)
1474                return -ENOMEM;
1475        snd_soc_codec_set_drvdata(codec, priv);
1476
1477        priv->wm8350 = wm8350;
1478
1479        for (i = 0; i < ARRAY_SIZE(supply_names); i++)
1480                priv->supplies[i].supply = supply_names[i];
1481
1482        ret = devm_regulator_bulk_get(wm8350->dev, ARRAY_SIZE(priv->supplies),
1483                                 priv->supplies);
1484        if (ret != 0)
1485                return ret;
1486
1487        /* Put the codec into reset if it wasn't already */
1488        wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1489
1490        INIT_DELAYED_WORK(&priv->pga_work, wm8350_pga_work);
1491        INIT_DELAYED_WORK(&priv->hpl.work, wm8350_hpl_work);
1492        INIT_DELAYED_WORK(&priv->hpr.work, wm8350_hpr_work);
1493
1494        /* Enable the codec */
1495        wm8350_set_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1496
1497        /* Enable robust clocking mode in ADC */
1498        snd_soc_write(codec, WM8350_SECURITY, 0xa7);
1499        snd_soc_write(codec, 0xde, 0x13);
1500        snd_soc_write(codec, WM8350_SECURITY, 0);
1501
1502        /* read OUT1 & OUT2 volumes */
1503        out1 = &priv->out1;
1504        out2 = &priv->out2;
1505        out1->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT1_VOLUME) &
1506                          WM8350_OUT1L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
1507        out1->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT1_VOLUME) &
1508                           WM8350_OUT1R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
1509        out2->left_vol = (wm8350_reg_read(wm8350, WM8350_LOUT2_VOLUME) &
1510                          WM8350_OUT2L_VOL_MASK) >> WM8350_OUT1L_VOL_SHIFT;
1511        out2->right_vol = (wm8350_reg_read(wm8350, WM8350_ROUT2_VOLUME) &
1512                           WM8350_OUT2R_VOL_MASK) >> WM8350_OUT1R_VOL_SHIFT;
1513        wm8350_reg_write(wm8350, WM8350_LOUT1_VOLUME, 0);
1514        wm8350_reg_write(wm8350, WM8350_ROUT1_VOLUME, 0);
1515        wm8350_reg_write(wm8350, WM8350_LOUT2_VOLUME, 0);
1516        wm8350_reg_write(wm8350, WM8350_ROUT2_VOLUME, 0);
1517
1518        /* Latch VU bits & mute */
1519        wm8350_set_bits(wm8350, WM8350_LOUT1_VOLUME,
1520                        WM8350_OUT1_VU | WM8350_OUT1L_MUTE);
1521        wm8350_set_bits(wm8350, WM8350_LOUT2_VOLUME,
1522                        WM8350_OUT2_VU | WM8350_OUT2L_MUTE);
1523        wm8350_set_bits(wm8350, WM8350_ROUT1_VOLUME,
1524                        WM8350_OUT1_VU | WM8350_OUT1R_MUTE);
1525        wm8350_set_bits(wm8350, WM8350_ROUT2_VOLUME,
1526                        WM8350_OUT2_VU | WM8350_OUT2R_MUTE);
1527
1528        /* Make sure AIF tristating is disabled by default */
1529        wm8350_clear_bits(wm8350, WM8350_AI_FORMATING, WM8350_AIF_TRI);
1530
1531        /* Make sure we've got a sane companding setup too */
1532        wm8350_clear_bits(wm8350, WM8350_ADC_DAC_COMP,
1533                          WM8350_DAC_COMP | WM8350_LOOPBACK);
1534
1535        /* Make sure jack detect is disabled to start off with */
1536        wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
1537                          WM8350_JDL_ENA | WM8350_JDR_ENA);
1538
1539        wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L,
1540                            wm8350_hpl_jack_handler, 0, "Left jack detect",
1541                            priv);
1542        wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R,
1543                            wm8350_hpr_jack_handler, 0, "Right jack detect",
1544                            priv);
1545        wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICSCD,
1546                            wm8350_mic_handler, 0, "Microphone short", priv);
1547        wm8350_register_irq(wm8350, WM8350_IRQ_CODEC_MICD,
1548                            wm8350_mic_handler, 0, "Microphone detect", priv);
1549
1550        return 0;
1551}
1552
1553static int  wm8350_codec_remove(struct snd_soc_codec *codec)
1554{
1555        struct wm8350_data *priv = snd_soc_codec_get_drvdata(codec);
1556        struct wm8350 *wm8350 = dev_get_platdata(codec->dev);
1557
1558        wm8350_clear_bits(wm8350, WM8350_JACK_DETECT,
1559                          WM8350_JDL_ENA | WM8350_JDR_ENA);
1560        wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_4, WM8350_TOCLK_ENA);
1561
1562        wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICD, priv);
1563        wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_MICSCD, priv);
1564        wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_L, priv);
1565        wm8350_free_irq(wm8350, WM8350_IRQ_CODEC_JCK_DET_R, priv);
1566
1567        priv->hpl.jack = NULL;
1568        priv->hpr.jack = NULL;
1569        priv->mic.jack = NULL;
1570
1571        cancel_delayed_work_sync(&priv->hpl.work);
1572        cancel_delayed_work_sync(&priv->hpr.work);
1573
1574        /* if there was any work waiting then we run it now and
1575         * wait for its completion */
1576        flush_delayed_work(&priv->pga_work);
1577
1578        wm8350_clear_bits(wm8350, WM8350_POWER_MGMT_5, WM8350_CODEC_ENA);
1579
1580        return 0;
1581}
1582
1583static struct regmap *wm8350_get_regmap(struct device *dev)
1584{
1585        struct wm8350 *wm8350 = dev_get_platdata(dev);
1586
1587        return wm8350->regmap;
1588}
1589
1590static const struct snd_soc_codec_driver soc_codec_dev_wm8350 = {
1591        .probe =        wm8350_codec_probe,
1592        .remove =       wm8350_codec_remove,
1593        .get_regmap =   wm8350_get_regmap,
1594        .set_bias_level = wm8350_set_bias_level,
1595        .suspend_bias_off = true,
1596
1597        .component_driver = {
1598                .controls               = wm8350_snd_controls,
1599                .num_controls           = ARRAY_SIZE(wm8350_snd_controls),
1600                .dapm_widgets           = wm8350_dapm_widgets,
1601                .num_dapm_widgets       = ARRAY_SIZE(wm8350_dapm_widgets),
1602                .dapm_routes            = wm8350_dapm_routes,
1603                .num_dapm_routes        = ARRAY_SIZE(wm8350_dapm_routes),
1604        },
1605};
1606
1607static int wm8350_probe(struct platform_device *pdev)
1608{
1609        return snd_soc_register_codec(&pdev->dev, &soc_codec_dev_wm8350,
1610                        &wm8350_dai, 1);
1611}
1612
1613static int wm8350_remove(struct platform_device *pdev)
1614{
1615        snd_soc_unregister_codec(&pdev->dev);
1616        return 0;
1617}
1618
1619static struct platform_driver wm8350_codec_driver = {
1620        .driver = {
1621                   .name = "wm8350-codec",
1622                   },
1623        .probe = wm8350_probe,
1624        .remove = wm8350_remove,
1625};
1626
1627module_platform_driver(wm8350_codec_driver);
1628
1629MODULE_DESCRIPTION("ASoC WM8350 driver");
1630MODULE_AUTHOR("Liam Girdwood");
1631MODULE_LICENSE("GPL");
1632MODULE_ALIAS("platform:wm8350-codec");
1633