linux/sound/soc/intel/boards/cht_bsw_rt5672.c
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   1/*
   2 *  cht_bsw_rt5672.c - ASoc Machine driver for Intel Cherryview-based platforms
   3 *                     Cherrytrail and Braswell, with RT5672 codec.
   4 *
   5 *  Copyright (C) 2014 Intel Corp
   6 *  Author: Subhransu S. Prusty <subhransu.s.prusty@intel.com>
   7 *          Mengdong Lin <mengdong.lin@intel.com>
   8 *
   9 *  This program is free software; you can redistribute it and/or modify
  10 *  it under the terms of the GNU General Public License as published by
  11 *  the Free Software Foundation; version 2 of the License.
  12 *
  13 *  This program is distributed in the hope that it will be useful, but
  14 *  WITHOUT ANY WARRANTY; without even the implied warranty of
  15 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16 *  General Public License for more details.
  17 */
  18
  19#include <linux/module.h>
  20#include <linux/platform_device.h>
  21#include <linux/slab.h>
  22#include <linux/clk.h>
  23#include <asm/cpu_device_id.h>
  24#include <sound/pcm.h>
  25#include <sound/pcm_params.h>
  26#include <sound/soc.h>
  27#include <sound/jack.h>
  28#include "../../codecs/rt5670.h"
  29#include "../atom/sst-atom-controls.h"
  30#include "../common/sst-acpi.h"
  31
  32/* The platform clock #3 outputs 19.2Mhz clock to codec as I2S MCLK */
  33#define CHT_PLAT_CLK_3_HZ       19200000
  34#define CHT_CODEC_DAI   "rt5670-aif1"
  35
  36struct cht_mc_private {
  37        struct snd_soc_jack headset;
  38        char codec_name[16];
  39        struct clk *mclk;
  40};
  41
  42/* Headset jack detection DAPM pins */
  43static struct snd_soc_jack_pin cht_bsw_headset_pins[] = {
  44        {
  45                .pin = "Headset Mic",
  46                .mask = SND_JACK_MICROPHONE,
  47        },
  48        {
  49                .pin = "Headphone",
  50                .mask = SND_JACK_HEADPHONE,
  51        },
  52};
  53
  54static inline struct snd_soc_dai *cht_get_codec_dai(struct snd_soc_card *card)
  55{
  56        struct snd_soc_pcm_runtime *rtd;
  57
  58        list_for_each_entry(rtd, &card->rtd_list, list) {
  59                if (!strncmp(rtd->codec_dai->name, CHT_CODEC_DAI,
  60                             strlen(CHT_CODEC_DAI)))
  61                        return rtd->codec_dai;
  62        }
  63        return NULL;
  64}
  65
  66static int platform_clock_control(struct snd_soc_dapm_widget *w,
  67                struct snd_kcontrol *k, int  event)
  68{
  69        struct snd_soc_dapm_context *dapm = w->dapm;
  70        struct snd_soc_card *card = dapm->card;
  71        struct snd_soc_dai *codec_dai;
  72        struct cht_mc_private *ctx = snd_soc_card_get_drvdata(card);
  73        int ret;
  74
  75        codec_dai = cht_get_codec_dai(card);
  76        if (!codec_dai) {
  77                dev_err(card->dev, "Codec dai not found; Unable to set platform clock\n");
  78                return -EIO;
  79        }
  80
  81        if (SND_SOC_DAPM_EVENT_ON(event)) {
  82                if (ctx->mclk) {
  83                        ret = clk_prepare_enable(ctx->mclk);
  84                        if (ret < 0) {
  85                                dev_err(card->dev,
  86                                        "could not configure MCLK state");
  87                                return ret;
  88                        }
  89                }
  90
  91                /* set codec PLL source to the 19.2MHz platform clock (MCLK) */
  92                ret = snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_MCLK,
  93                                CHT_PLAT_CLK_3_HZ, 48000 * 512);
  94                if (ret < 0) {
  95                        dev_err(card->dev, "can't set codec pll: %d\n", ret);
  96                        return ret;
  97                }
  98
  99                /* set codec sysclk source to PLL */
 100                ret = snd_soc_dai_set_sysclk(codec_dai, RT5670_SCLK_S_PLL1,
 101                        48000 * 512, SND_SOC_CLOCK_IN);
 102                if (ret < 0) {
 103                        dev_err(card->dev, "can't set codec sysclk: %d\n", ret);
 104                        return ret;
 105                }
 106        } else {
 107                /* Set codec sysclk source to its internal clock because codec
 108                 * PLL will be off when idle and MCLK will also be off by ACPI
 109                 * when codec is runtime suspended. Codec needs clock for jack
 110                 * detection and button press.
 111                 */
 112                snd_soc_dai_set_sysclk(codec_dai, RT5670_SCLK_S_RCCLK,
 113                                       48000 * 512, SND_SOC_CLOCK_IN);
 114
 115                if (ctx->mclk)
 116                        clk_disable_unprepare(ctx->mclk);
 117        }
 118        return 0;
 119}
 120
 121static const struct snd_soc_dapm_widget cht_dapm_widgets[] = {
 122        SND_SOC_DAPM_HP("Headphone", NULL),
 123        SND_SOC_DAPM_MIC("Headset Mic", NULL),
 124        SND_SOC_DAPM_MIC("Int Mic", NULL),
 125        SND_SOC_DAPM_SPK("Ext Spk", NULL),
 126        SND_SOC_DAPM_SUPPLY("Platform Clock", SND_SOC_NOPM, 0, 0,
 127                        platform_clock_control, SND_SOC_DAPM_PRE_PMU |
 128                        SND_SOC_DAPM_POST_PMD),
 129};
 130
 131static const struct snd_soc_dapm_route cht_audio_map[] = {
 132        {"IN1P", NULL, "Headset Mic"},
 133        {"IN1N", NULL, "Headset Mic"},
 134        {"DMIC L1", NULL, "Int Mic"},
 135        {"DMIC R1", NULL, "Int Mic"},
 136        {"Headphone", NULL, "HPOL"},
 137        {"Headphone", NULL, "HPOR"},
 138        {"Ext Spk", NULL, "SPOLP"},
 139        {"Ext Spk", NULL, "SPOLN"},
 140        {"Ext Spk", NULL, "SPORP"},
 141        {"Ext Spk", NULL, "SPORN"},
 142        {"AIF1 Playback", NULL, "ssp2 Tx"},
 143        {"ssp2 Tx", NULL, "codec_out0"},
 144        {"ssp2 Tx", NULL, "codec_out1"},
 145        {"codec_in0", NULL, "ssp2 Rx"},
 146        {"codec_in1", NULL, "ssp2 Rx"},
 147        {"ssp2 Rx", NULL, "AIF1 Capture"},
 148        {"Headphone", NULL, "Platform Clock"},
 149        {"Headset Mic", NULL, "Platform Clock"},
 150        {"Int Mic", NULL, "Platform Clock"},
 151        {"Ext Spk", NULL, "Platform Clock"},
 152};
 153
 154static const struct snd_kcontrol_new cht_mc_controls[] = {
 155        SOC_DAPM_PIN_SWITCH("Headphone"),
 156        SOC_DAPM_PIN_SWITCH("Headset Mic"),
 157        SOC_DAPM_PIN_SWITCH("Int Mic"),
 158        SOC_DAPM_PIN_SWITCH("Ext Spk"),
 159};
 160
 161static int cht_aif1_hw_params(struct snd_pcm_substream *substream,
 162                                        struct snd_pcm_hw_params *params)
 163{
 164        struct snd_soc_pcm_runtime *rtd = substream->private_data;
 165        struct snd_soc_dai *codec_dai = rtd->codec_dai;
 166        int ret;
 167
 168        /* set codec PLL source to the 19.2MHz platform clock (MCLK) */
 169        ret = snd_soc_dai_set_pll(codec_dai, 0, RT5670_PLL1_S_MCLK,
 170                                  CHT_PLAT_CLK_3_HZ, params_rate(params) * 512);
 171        if (ret < 0) {
 172                dev_err(rtd->dev, "can't set codec pll: %d\n", ret);
 173                return ret;
 174        }
 175
 176        /* set codec sysclk source to PLL */
 177        ret = snd_soc_dai_set_sysclk(codec_dai, RT5670_SCLK_S_PLL1,
 178                                     params_rate(params) * 512,
 179                                     SND_SOC_CLOCK_IN);
 180        if (ret < 0) {
 181                dev_err(rtd->dev, "can't set codec sysclk: %d\n", ret);
 182                return ret;
 183        }
 184        return 0;
 185}
 186
 187static const struct acpi_gpio_params headset_gpios = { 0, 0, false };
 188
 189static const struct acpi_gpio_mapping cht_rt5672_gpios[] = {
 190        { "headset-gpios", &headset_gpios, 1 },
 191        {},
 192};
 193
 194static int cht_codec_init(struct snd_soc_pcm_runtime *runtime)
 195{
 196        int ret;
 197        struct snd_soc_dai *codec_dai = runtime->codec_dai;
 198        struct snd_soc_codec *codec = codec_dai->codec;
 199        struct cht_mc_private *ctx = snd_soc_card_get_drvdata(runtime->card);
 200
 201        if (devm_acpi_dev_add_driver_gpios(codec->dev, cht_rt5672_gpios))
 202                dev_warn(runtime->dev, "Unable to add GPIO mapping table\n");
 203
 204        /* TDM 4 slots 24 bit, set Rx & Tx bitmask to 4 active slots */
 205        ret = snd_soc_dai_set_tdm_slot(codec_dai, 0xF, 0xF, 4, 24);
 206        if (ret < 0) {
 207                dev_err(runtime->dev, "can't set codec TDM slot %d\n", ret);
 208                return ret;
 209        }
 210
 211        /* Select codec ASRC clock source to track I2S1 clock, because codec
 212         * is in slave mode and 100fs I2S format (BCLK = 100 * LRCLK) cannot
 213         * be supported by RT5672. Otherwise, ASRC will be disabled and cause
 214         * noise.
 215         */
 216        rt5670_sel_asrc_clk_src(codec,
 217                                RT5670_DA_STEREO_FILTER
 218                                | RT5670_DA_MONO_L_FILTER
 219                                | RT5670_DA_MONO_R_FILTER
 220                                | RT5670_AD_STEREO_FILTER
 221                                | RT5670_AD_MONO_L_FILTER
 222                                | RT5670_AD_MONO_R_FILTER,
 223                                RT5670_CLK_SEL_I2S1_ASRC);
 224
 225        ret = snd_soc_card_jack_new(runtime->card, "Headset",
 226                                    SND_JACK_HEADSET | SND_JACK_BTN_0 |
 227                                    SND_JACK_BTN_1 | SND_JACK_BTN_2,
 228                                    &ctx->headset,
 229                                    cht_bsw_headset_pins,
 230                                    ARRAY_SIZE(cht_bsw_headset_pins));
 231        if (ret)
 232                return ret;
 233
 234        rt5670_set_jack_detect(codec, &ctx->headset);
 235        if (ctx->mclk) {
 236                /*
 237                 * The firmware might enable the clock at
 238                 * boot (this information may or may not
 239                 * be reflected in the enable clock register).
 240                 * To change the rate we must disable the clock
 241                 * first to cover these cases. Due to common
 242                 * clock framework restrictions that do not allow
 243                 * to disable a clock that has not been enabled,
 244                 * we need to enable the clock first.
 245                 */
 246                ret = clk_prepare_enable(ctx->mclk);
 247                if (!ret)
 248                        clk_disable_unprepare(ctx->mclk);
 249
 250                ret = clk_set_rate(ctx->mclk, CHT_PLAT_CLK_3_HZ);
 251
 252                if (ret) {
 253                        dev_err(runtime->dev, "unable to set MCLK rate\n");
 254                        return ret;
 255                }
 256        }
 257        return 0;
 258}
 259
 260static int cht_codec_fixup(struct snd_soc_pcm_runtime *rtd,
 261                            struct snd_pcm_hw_params *params)
 262{
 263        struct snd_interval *rate = hw_param_interval(params,
 264                        SNDRV_PCM_HW_PARAM_RATE);
 265        struct snd_interval *channels = hw_param_interval(params,
 266                                                SNDRV_PCM_HW_PARAM_CHANNELS);
 267
 268        /* The DSP will covert the FE rate to 48k, stereo, 24bits */
 269        rate->min = rate->max = 48000;
 270        channels->min = channels->max = 2;
 271
 272        /* set SSP2 to 24-bit */
 273        params_set_format(params, SNDRV_PCM_FORMAT_S24_LE);
 274        return 0;
 275}
 276
 277static int cht_aif1_startup(struct snd_pcm_substream *substream)
 278{
 279        return snd_pcm_hw_constraint_single(substream->runtime,
 280                        SNDRV_PCM_HW_PARAM_RATE, 48000);
 281}
 282
 283static const struct snd_soc_ops cht_aif1_ops = {
 284        .startup = cht_aif1_startup,
 285};
 286
 287static const struct snd_soc_ops cht_be_ssp2_ops = {
 288        .hw_params = cht_aif1_hw_params,
 289};
 290
 291static struct snd_soc_dai_link cht_dailink[] = {
 292        /* Front End DAI links */
 293        [MERR_DPCM_AUDIO] = {
 294                .name = "Audio Port",
 295                .stream_name = "Audio",
 296                .cpu_dai_name = "media-cpu-dai",
 297                .codec_dai_name = "snd-soc-dummy-dai",
 298                .codec_name = "snd-soc-dummy",
 299                .platform_name = "sst-mfld-platform",
 300                .nonatomic = true,
 301                .dynamic = 1,
 302                .dpcm_playback = 1,
 303                .dpcm_capture = 1,
 304                .ops = &cht_aif1_ops,
 305        },
 306        [MERR_DPCM_DEEP_BUFFER] = {
 307                .name = "Deep-Buffer Audio Port",
 308                .stream_name = "Deep-Buffer Audio",
 309                .cpu_dai_name = "deepbuffer-cpu-dai",
 310                .codec_dai_name = "snd-soc-dummy-dai",
 311                .codec_name = "snd-soc-dummy",
 312                .platform_name = "sst-mfld-platform",
 313                .nonatomic = true,
 314                .dynamic = 1,
 315                .dpcm_playback = 1,
 316                .ops = &cht_aif1_ops,
 317        },
 318        [MERR_DPCM_COMPR] = {
 319                .name = "Compressed Port",
 320                .stream_name = "Compress",
 321                .cpu_dai_name = "compress-cpu-dai",
 322                .codec_dai_name = "snd-soc-dummy-dai",
 323                .codec_name = "snd-soc-dummy",
 324                .platform_name = "sst-mfld-platform",
 325        },
 326
 327        /* Back End DAI links */
 328        {
 329                /* SSP2 - Codec */
 330                .name = "SSP2-Codec",
 331                .id = 1,
 332                .cpu_dai_name = "ssp2-port",
 333                .platform_name = "sst-mfld-platform",
 334                .no_pcm = 1,
 335                .nonatomic = true,
 336                .codec_dai_name = "rt5670-aif1",
 337                .codec_name = "i2c-10EC5670:00",
 338                .dai_fmt = SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF
 339                                        | SND_SOC_DAIFMT_CBS_CFS,
 340                .init = cht_codec_init,
 341                .be_hw_params_fixup = cht_codec_fixup,
 342                .dpcm_playback = 1,
 343                .dpcm_capture = 1,
 344                .ops = &cht_be_ssp2_ops,
 345        },
 346};
 347
 348static int cht_suspend_pre(struct snd_soc_card *card)
 349{
 350        struct snd_soc_component *component;
 351
 352        list_for_each_entry(component, &card->component_dev_list, card_list) {
 353                if (!strcmp(component->name, "i2c-10EC5670:00")) {
 354                        struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
 355
 356                        dev_dbg(codec->dev, "disabling jack detect before going to suspend.\n");
 357                        rt5670_jack_suspend(codec);
 358                        break;
 359                }
 360        }
 361        return 0;
 362}
 363
 364static int cht_resume_post(struct snd_soc_card *card)
 365{
 366        struct snd_soc_component *component;
 367
 368        list_for_each_entry(component, &card->component_dev_list, card_list) {
 369                if (!strcmp(component->name, "i2c-10EC5670:00")) {
 370                        struct snd_soc_codec *codec = snd_soc_component_to_codec(component);
 371
 372                        dev_dbg(codec->dev, "enabling jack detect for resume.\n");
 373                        rt5670_jack_resume(codec);
 374                        break;
 375                }
 376        }
 377
 378        return 0;
 379}
 380
 381/* SoC card */
 382static struct snd_soc_card snd_soc_card_cht = {
 383        .name = "cherrytrailcraudio",
 384        .owner = THIS_MODULE,
 385        .dai_link = cht_dailink,
 386        .num_links = ARRAY_SIZE(cht_dailink),
 387        .dapm_widgets = cht_dapm_widgets,
 388        .num_dapm_widgets = ARRAY_SIZE(cht_dapm_widgets),
 389        .dapm_routes = cht_audio_map,
 390        .num_dapm_routes = ARRAY_SIZE(cht_audio_map),
 391        .controls = cht_mc_controls,
 392        .num_controls = ARRAY_SIZE(cht_mc_controls),
 393        .suspend_pre = cht_suspend_pre,
 394        .resume_post = cht_resume_post,
 395};
 396
 397static bool is_valleyview(void)
 398{
 399        static const struct x86_cpu_id cpu_ids[] = {
 400                { X86_VENDOR_INTEL, 6, 55 }, /* Valleyview, Bay Trail */
 401                {}
 402        };
 403
 404        if (!x86_match_cpu(cpu_ids))
 405                return false;
 406        return true;
 407}
 408
 409#define RT5672_I2C_DEFAULT      "i2c-10EC5670:00"
 410
 411static int snd_cht_mc_probe(struct platform_device *pdev)
 412{
 413        int ret_val = 0;
 414        struct cht_mc_private *drv;
 415        struct sst_acpi_mach *mach = pdev->dev.platform_data;
 416        const char *i2c_name;
 417        int i;
 418
 419        drv = devm_kzalloc(&pdev->dev, sizeof(*drv), GFP_ATOMIC);
 420        if (!drv)
 421                return -ENOMEM;
 422
 423        strcpy(drv->codec_name, RT5672_I2C_DEFAULT);
 424
 425        /* fixup codec name based on HID */
 426        if (mach) {
 427                i2c_name = sst_acpi_find_name_from_hid(mach->id);
 428                if (i2c_name) {
 429                        snprintf(drv->codec_name, sizeof(drv->codec_name),
 430                                 "i2c-%s", i2c_name);
 431                        for (i = 0; i < ARRAY_SIZE(cht_dailink); i++) {
 432                                if (!strcmp(cht_dailink[i].codec_name,
 433                                            RT5672_I2C_DEFAULT)) {
 434                                        cht_dailink[i].codec_name =
 435                                                drv->codec_name;
 436                                        break;
 437                                }
 438                        }
 439                }
 440        }
 441
 442        if (is_valleyview()) {
 443                drv->mclk = devm_clk_get(&pdev->dev, "pmc_plt_clk_3");
 444                if (IS_ERR(drv->mclk)) {
 445                        dev_err(&pdev->dev,
 446                                "Failed to get MCLK from pmc_plt_clk_3: %ld\n",
 447                                PTR_ERR(drv->mclk));
 448                        return PTR_ERR(drv->mclk);
 449                }
 450        }
 451        snd_soc_card_set_drvdata(&snd_soc_card_cht, drv);
 452
 453        /* register the soc card */
 454        snd_soc_card_cht.dev = &pdev->dev;
 455        ret_val = devm_snd_soc_register_card(&pdev->dev, &snd_soc_card_cht);
 456        if (ret_val) {
 457                dev_err(&pdev->dev,
 458                        "snd_soc_register_card failed %d\n", ret_val);
 459                return ret_val;
 460        }
 461        platform_set_drvdata(pdev, &snd_soc_card_cht);
 462        return ret_val;
 463}
 464
 465static struct platform_driver snd_cht_mc_driver = {
 466        .driver = {
 467                .name = "cht-bsw-rt5672",
 468        },
 469        .probe = snd_cht_mc_probe,
 470};
 471
 472module_platform_driver(snd_cht_mc_driver);
 473
 474MODULE_DESCRIPTION("ASoC Intel(R) Baytrail CR Machine driver");
 475MODULE_AUTHOR("Subhransu S. Prusty, Mengdong Lin");
 476MODULE_LICENSE("GPL v2");
 477MODULE_ALIAS("platform:cht-bsw-rt5672");
 478