LXR linux/sound/soc/intel/skylake/skl-sst-ipc.h

   1/*
   2 * Intel SKL IPC Support
   3 *
   4 * Copyright (C) 2014-15, Intel Corporation.
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License as version 2, as
   8 * published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope that it will be useful, but
  11 * WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13 * General Public License for more details.
  14 */
  15
  16#ifndef __SKL_IPC_H
  17#define __SKL_IPC_H
  18
  19#include <linux/irqreturn.h>
  20#include "../common/sst-ipc.h"
  21
  22struct sst_dsp;
  23struct skl_sst;
  24struct sst_generic_ipc;
  25
  26enum skl_ipc_pipeline_state {
  27        PPL_INVALID_STATE =     0,
  28        PPL_UNINITIALIZED =     1,
  29        PPL_RESET =             2,
  30        PPL_PAUSED =            3,
  31        PPL_RUNNING =           4,
  32        PPL_ERROR_STOP =        5,
  33        PPL_SAVED =             6,
  34        PPL_RESTORED =          7
  35};
  36
  37struct skl_ipc_dxstate_info {
  38        u32 core_mask;
  39        u32 dx_mask;
  40};
  41
  42struct skl_ipc_header {
  43        u32 primary;
  44        u32 extension;
  45};
  46
  47#define SKL_DSP_CORES_MAX  2
  48
  49struct skl_dsp_cores {
  50        unsigned int count;
  51        enum skl_dsp_states state[SKL_DSP_CORES_MAX];
  52        int usage_count[SKL_DSP_CORES_MAX];
  53};
  54
  55/**
  56 * skl_d0i3_data: skl D0i3 counters data struct
  57 *
  58 * @streaming: Count of usecases that can attempt streaming D0i3
  59 * @non_streaming: Count of usecases that can attempt non-streaming D0i3
  60 * @non_d0i3: Count of usecases that cannot attempt D0i3
  61 * @state: current state
  62 * @work: D0i3 worker thread
  63 */
  64struct skl_d0i3_data {
  65        int streaming;
  66        int non_streaming;
  67        int non_d0i3;
  68        enum skl_dsp_d0i3_states state;
  69        struct delayed_work work;
  70};
  71
  72#define SKL_LIB_NAME_LENGTH 128
  73#define SKL_MAX_LIB 16
  74
  75struct skl_lib_info {
  76        char name[SKL_LIB_NAME_LENGTH];
  77        const struct firmware *fw;
  78};
  79
  80struct skl_sst {
  81        struct device *dev;
  82        struct sst_dsp *dsp;
  83
  84        /* boot */
  85        wait_queue_head_t boot_wait;
  86        bool boot_complete;
  87
  88        /* module load */
  89        wait_queue_head_t mod_load_wait;
  90        bool mod_load_complete;
  91        bool mod_load_status;
  92
  93        /* IPC messaging */
  94        struct sst_generic_ipc ipc;
  95
  96        /* callback for miscbdge */
  97        void (*enable_miscbdcge)(struct device *dev, bool enable);
  98        /* Is CGCTL.MISCBDCGE disabled */
  99        bool miscbdcg_disabled;
 100
 101        /* Populate module information */
 102        struct list_head uuid_list;
 103
 104        /* Is firmware loaded */
 105        bool fw_loaded;
 106
 107        /* first boot ? */
 108        bool is_first_boot;
 109
 110        /* multi-core */
 111        struct skl_dsp_cores cores;
 112
 113        /* library info */
 114        struct skl_lib_info  lib_info[SKL_MAX_LIB];
 115        int lib_count;
 116
 117        /* Callback to update D0i3C register */
 118        void (*update_d0i3c)(struct device *dev, bool enable);
 119
 120        struct skl_d0i3_data d0i3;
 121
 122        const struct skl_dsp_ops *dsp_ops;
 123};
 124
 125struct skl_ipc_init_instance_msg {
 126        u32 module_id;
 127        u32 instance_id;
 128        u16 param_data_size;
 129        u8 ppl_instance_id;
 130        u8 core_id;
 131        u8 domain;
 132};
 133
 134struct skl_ipc_bind_unbind_msg {
 135        u32 module_id;
 136        u32 instance_id;
 137        u32 dst_module_id;
 138        u32 dst_instance_id;
 139        u8 src_queue;
 140        u8 dst_queue;
 141        bool bind;
 142};
 143
 144struct skl_ipc_large_config_msg {
 145        u32 module_id;
 146        u32 instance_id;
 147        u32 large_param_id;
 148        u32 param_data_size;
 149};
 150
 151struct skl_ipc_d0ix_msg {
 152        u32 module_id;
 153        u32 instance_id;
 154        u8 streaming;
 155        u8 wake;
 156};
 157
 158#define SKL_IPC_BOOT_MSECS              3000
 159
 160#define SKL_IPC_D3_MASK 0
 161#define SKL_IPC_D0_MASK 3
 162
 163irqreturn_t skl_dsp_irq_thread_handler(int irq, void *context);
 164
 165int skl_ipc_create_pipeline(struct sst_generic_ipc *sst_ipc,
 166                u16 ppl_mem_size, u8 ppl_type, u8 instance_id, u8 lp_mode);
 167
 168int skl_ipc_delete_pipeline(struct sst_generic_ipc *sst_ipc, u8 instance_id);
 169
 170int skl_ipc_set_pipeline_state(struct sst_generic_ipc *sst_ipc,
 171                u8 instance_id, enum skl_ipc_pipeline_state state);
 172
 173int skl_ipc_save_pipeline(struct sst_generic_ipc *ipc,
 174                u8 instance_id, int dma_id);
 175
 176int skl_ipc_restore_pipeline(struct sst_generic_ipc *ipc, u8 instance_id);
 177
 178int skl_ipc_init_instance(struct sst_generic_ipc *sst_ipc,
 179                struct skl_ipc_init_instance_msg *msg, void *param_data);
 180
 181int skl_ipc_bind_unbind(struct sst_generic_ipc *sst_ipc,
 182                struct skl_ipc_bind_unbind_msg *msg);
 183
 184int skl_ipc_load_modules(struct sst_generic_ipc *ipc,
 185                                u8 module_cnt, void *data);
 186
 187int skl_ipc_unload_modules(struct sst_generic_ipc *ipc,
 188                                u8 module_cnt, void *data);
 189
 190int skl_ipc_set_dx(struct sst_generic_ipc *ipc,
 191                u8 instance_id, u16 module_id, struct skl_ipc_dxstate_info *dx);
 192
 193int skl_ipc_set_large_config(struct sst_generic_ipc *ipc,
 194                struct skl_ipc_large_config_msg *msg, u32 *param);
 195
 196int skl_ipc_get_large_config(struct sst_generic_ipc *ipc,
 197                struct skl_ipc_large_config_msg *msg, u32 *param);
 198
 199int skl_sst_ipc_load_library(struct sst_generic_ipc *ipc,
 200                        u8 dma_id, u8 table_id, bool wait);
 201
 202int skl_ipc_set_d0ix(struct sst_generic_ipc *ipc,
 203                struct skl_ipc_d0ix_msg *msg);
 204
 205int skl_ipc_check_D0i0(struct sst_dsp *dsp, bool state);
 206
 207void skl_ipc_int_enable(struct sst_dsp *dsp);
 208void skl_ipc_op_int_enable(struct sst_dsp *ctx);
 209void skl_ipc_op_int_disable(struct sst_dsp *ctx);
 210void skl_ipc_int_disable(struct sst_dsp *dsp);
 211
 212bool skl_ipc_int_status(struct sst_dsp *dsp);
 213void skl_ipc_free(struct sst_generic_ipc *ipc);
 214int skl_ipc_init(struct device *dev, struct skl_sst *skl);
 215void skl_clear_module_cnt(struct sst_dsp *ctx);
 216
 217#endif /* __SKL_IPC_H */
 218