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27#include <linux/init.h>
28#include <linux/module.h>
29#include <linux/platform_device.h>
30#include <linux/interrupt.h>
31#include <linux/err.h>
32#include <linux/io.h>
33#include <linux/irq.h>
34#include <linux/slab.h>
35#include <linux/pm_runtime.h>
36#include <linux/of_device.h>
37
38#include <sound/core.h>
39#include <sound/pcm.h>
40#include <sound/pcm_params.h>
41#include <sound/soc.h>
42#include <sound/dmaengine_pcm.h>
43#include <sound/omap-pcm.h>
44
45#include "omap-mcpdm.h"
46
47struct mcpdm_link_config {
48 u32 link_mask;
49 u32 threshold;
50};
51
52struct omap_mcpdm {
53 struct device *dev;
54 unsigned long phys_base;
55 void __iomem *io_base;
56 int irq;
57
58 struct mutex mutex;
59
60
61 struct mcpdm_link_config config[2];
62
63
64 u32 dn_rx_offset;
65
66
67 bool restart;
68
69
70 int pm_active_count;
71
72 struct snd_dmaengine_dai_dma_data dma_data[2];
73};
74
75
76
77
78
79static inline void omap_mcpdm_write(struct omap_mcpdm *mcpdm, u16 reg, u32 val)
80{
81 writel_relaxed(val, mcpdm->io_base + reg);
82}
83
84static inline int omap_mcpdm_read(struct omap_mcpdm *mcpdm, u16 reg)
85{
86 return readl_relaxed(mcpdm->io_base + reg);
87}
88
89#ifdef DEBUG
90static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm)
91{
92 dev_dbg(mcpdm->dev, "***********************\n");
93 dev_dbg(mcpdm->dev, "IRQSTATUS_RAW: 0x%04x\n",
94 omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS_RAW));
95 dev_dbg(mcpdm->dev, "IRQSTATUS: 0x%04x\n",
96 omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS));
97 dev_dbg(mcpdm->dev, "IRQENABLE_SET: 0x%04x\n",
98 omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_SET));
99 dev_dbg(mcpdm->dev, "IRQENABLE_CLR: 0x%04x\n",
100 omap_mcpdm_read(mcpdm, MCPDM_REG_IRQENABLE_CLR));
101 dev_dbg(mcpdm->dev, "IRQWAKE_EN: 0x%04x\n",
102 omap_mcpdm_read(mcpdm, MCPDM_REG_IRQWAKE_EN));
103 dev_dbg(mcpdm->dev, "DMAENABLE_SET: 0x%04x\n",
104 omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_SET));
105 dev_dbg(mcpdm->dev, "DMAENABLE_CLR: 0x%04x\n",
106 omap_mcpdm_read(mcpdm, MCPDM_REG_DMAENABLE_CLR));
107 dev_dbg(mcpdm->dev, "DMAWAKEEN: 0x%04x\n",
108 omap_mcpdm_read(mcpdm, MCPDM_REG_DMAWAKEEN));
109 dev_dbg(mcpdm->dev, "CTRL: 0x%04x\n",
110 omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL));
111 dev_dbg(mcpdm->dev, "DN_DATA: 0x%04x\n",
112 omap_mcpdm_read(mcpdm, MCPDM_REG_DN_DATA));
113 dev_dbg(mcpdm->dev, "UP_DATA: 0x%04x\n",
114 omap_mcpdm_read(mcpdm, MCPDM_REG_UP_DATA));
115 dev_dbg(mcpdm->dev, "FIFO_CTRL_DN: 0x%04x\n",
116 omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_DN));
117 dev_dbg(mcpdm->dev, "FIFO_CTRL_UP: 0x%04x\n",
118 omap_mcpdm_read(mcpdm, MCPDM_REG_FIFO_CTRL_UP));
119 dev_dbg(mcpdm->dev, "***********************\n");
120}
121#else
122static void omap_mcpdm_reg_dump(struct omap_mcpdm *mcpdm) {}
123#endif
124
125
126
127
128
129static void omap_mcpdm_start(struct omap_mcpdm *mcpdm)
130{
131 u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
132 u32 link_mask = mcpdm->config[0].link_mask | mcpdm->config[1].link_mask;
133
134 ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
135 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
136
137 ctrl |= link_mask;
138 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
139
140 ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
141 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
142}
143
144
145
146
147
148static void omap_mcpdm_stop(struct omap_mcpdm *mcpdm)
149{
150 u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
151 u32 link_mask = MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK;
152
153 ctrl |= (MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
154 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
155
156 ctrl &= ~(link_mask);
157 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
158
159 ctrl &= ~(MCPDM_SW_DN_RST | MCPDM_SW_UP_RST);
160 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl);
161
162}
163
164
165
166
167static inline int omap_mcpdm_active(struct omap_mcpdm *mcpdm)
168{
169 return omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL) &
170 (MCPDM_PDM_DN_MASK | MCPDM_PDM_UP_MASK);
171}
172
173
174
175
176
177static void omap_mcpdm_open_streams(struct omap_mcpdm *mcpdm)
178{
179 u32 ctrl = omap_mcpdm_read(mcpdm, MCPDM_REG_CTRL);
180
181 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, ctrl | MCPDM_WD_EN);
182
183 omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_SET,
184 MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL |
185 MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
186
187
188 if (mcpdm->dn_rx_offset) {
189 u32 dn_offset = mcpdm->dn_rx_offset;
190
191 omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
192 dn_offset |= (MCPDM_DN_OFST_RX1_EN | MCPDM_DN_OFST_RX2_EN);
193 omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, dn_offset);
194 }
195
196 omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_DN,
197 mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold);
198 omap_mcpdm_write(mcpdm, MCPDM_REG_FIFO_CTRL_UP,
199 mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold);
200
201 omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_SET,
202 MCPDM_DMA_DN_ENABLE | MCPDM_DMA_UP_ENABLE);
203}
204
205
206
207
208
209static void omap_mcpdm_close_streams(struct omap_mcpdm *mcpdm)
210{
211
212 omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
213 MCPDM_DN_IRQ_EMPTY | MCPDM_DN_IRQ_FULL);
214
215
216 omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_DN_ENABLE);
217
218
219 omap_mcpdm_write(mcpdm, MCPDM_REG_IRQENABLE_CLR,
220 MCPDM_UP_IRQ_EMPTY | MCPDM_UP_IRQ_FULL);
221
222
223 omap_mcpdm_write(mcpdm, MCPDM_REG_DMAENABLE_CLR, MCPDM_DMA_UP_ENABLE);
224
225
226 if (mcpdm->dn_rx_offset)
227 omap_mcpdm_write(mcpdm, MCPDM_REG_DN_OFFSET, 0);
228}
229
230static irqreturn_t omap_mcpdm_irq_handler(int irq, void *dev_id)
231{
232 struct omap_mcpdm *mcpdm = dev_id;
233 int irq_status;
234
235 irq_status = omap_mcpdm_read(mcpdm, MCPDM_REG_IRQSTATUS);
236
237
238 omap_mcpdm_write(mcpdm, MCPDM_REG_IRQSTATUS, irq_status);
239
240 if (irq_status & MCPDM_DN_IRQ_FULL)
241 dev_dbg(mcpdm->dev, "DN (playback) FIFO Full\n");
242
243 if (irq_status & MCPDM_DN_IRQ_EMPTY)
244 dev_dbg(mcpdm->dev, "DN (playback) FIFO Empty\n");
245
246 if (irq_status & MCPDM_DN_IRQ)
247 dev_dbg(mcpdm->dev, "DN (playback) write request\n");
248
249 if (irq_status & MCPDM_UP_IRQ_FULL)
250 dev_dbg(mcpdm->dev, "UP (capture) FIFO Full\n");
251
252 if (irq_status & MCPDM_UP_IRQ_EMPTY)
253 dev_dbg(mcpdm->dev, "UP (capture) FIFO Empty\n");
254
255 if (irq_status & MCPDM_UP_IRQ)
256 dev_dbg(mcpdm->dev, "UP (capture) write request\n");
257
258 return IRQ_HANDLED;
259}
260
261static int omap_mcpdm_dai_startup(struct snd_pcm_substream *substream,
262 struct snd_soc_dai *dai)
263{
264 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
265
266 mutex_lock(&mcpdm->mutex);
267
268 if (!dai->active)
269 omap_mcpdm_open_streams(mcpdm);
270
271 mutex_unlock(&mcpdm->mutex);
272
273 return 0;
274}
275
276static void omap_mcpdm_dai_shutdown(struct snd_pcm_substream *substream,
277 struct snd_soc_dai *dai)
278{
279 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
280
281 mutex_lock(&mcpdm->mutex);
282
283 if (!dai->active) {
284 if (omap_mcpdm_active(mcpdm)) {
285 omap_mcpdm_stop(mcpdm);
286 omap_mcpdm_close_streams(mcpdm);
287 mcpdm->config[0].link_mask = 0;
288 mcpdm->config[1].link_mask = 0;
289 }
290 }
291
292 mutex_unlock(&mcpdm->mutex);
293}
294
295static int omap_mcpdm_dai_hw_params(struct snd_pcm_substream *substream,
296 struct snd_pcm_hw_params *params,
297 struct snd_soc_dai *dai)
298{
299 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
300 int stream = substream->stream;
301 struct snd_dmaengine_dai_dma_data *dma_data;
302 u32 threshold;
303 int channels;
304 int link_mask = 0;
305
306 channels = params_channels(params);
307 switch (channels) {
308 case 5:
309 if (stream == SNDRV_PCM_STREAM_CAPTURE)
310
311 return -EINVAL;
312 link_mask |= 1 << 4;
313 case 4:
314 if (stream == SNDRV_PCM_STREAM_CAPTURE)
315
316 return -EINVAL;
317 link_mask |= 1 << 3;
318 case 3:
319 link_mask |= 1 << 2;
320 case 2:
321 link_mask |= 1 << 1;
322 case 1:
323 link_mask |= 1 << 0;
324 break;
325 default:
326
327 return -EINVAL;
328 }
329
330 dma_data = snd_soc_dai_get_dma_data(dai, substream);
331
332 threshold = mcpdm->config[stream].threshold;
333
334 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
335 link_mask <<= 3;
336
337
338 if (!mcpdm->config[!stream].link_mask)
339 mcpdm->config[!stream].link_mask = 0x3;
340
341 dma_data->maxburst =
342 (MCPDM_DN_THRES_MAX - threshold) * channels;
343 } else {
344
345 if (!mcpdm->config[!stream].link_mask)
346 mcpdm->config[!stream].link_mask = (0x3 << 3);
347
348 dma_data->maxburst = threshold * channels;
349 }
350
351
352 if (mcpdm->config[stream].link_mask &&
353 mcpdm->config[stream].link_mask != link_mask)
354 mcpdm->restart = true;
355
356 mcpdm->config[stream].link_mask = link_mask;
357
358 return 0;
359}
360
361static int omap_mcpdm_prepare(struct snd_pcm_substream *substream,
362 struct snd_soc_dai *dai)
363{
364 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
365
366 if (!omap_mcpdm_active(mcpdm)) {
367 omap_mcpdm_start(mcpdm);
368 omap_mcpdm_reg_dump(mcpdm);
369 } else if (mcpdm->restart) {
370 omap_mcpdm_stop(mcpdm);
371 omap_mcpdm_start(mcpdm);
372 mcpdm->restart = false;
373 omap_mcpdm_reg_dump(mcpdm);
374 }
375
376 return 0;
377}
378
379static const struct snd_soc_dai_ops omap_mcpdm_dai_ops = {
380 .startup = omap_mcpdm_dai_startup,
381 .shutdown = omap_mcpdm_dai_shutdown,
382 .hw_params = omap_mcpdm_dai_hw_params,
383 .prepare = omap_mcpdm_prepare,
384};
385
386static int omap_mcpdm_probe(struct snd_soc_dai *dai)
387{
388 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
389 int ret;
390
391 pm_runtime_enable(mcpdm->dev);
392
393
394 pm_runtime_get_sync(mcpdm->dev);
395 omap_mcpdm_write(mcpdm, MCPDM_REG_CTRL, 0x00);
396
397 ret = request_irq(mcpdm->irq, omap_mcpdm_irq_handler, 0, "McPDM",
398 (void *)mcpdm);
399
400 pm_runtime_put_sync(mcpdm->dev);
401
402 if (ret) {
403 dev_err(mcpdm->dev, "Request for IRQ failed\n");
404 pm_runtime_disable(mcpdm->dev);
405 }
406
407
408 mcpdm->config[SNDRV_PCM_STREAM_PLAYBACK].threshold = 2;
409 mcpdm->config[SNDRV_PCM_STREAM_CAPTURE].threshold =
410 MCPDM_UP_THRES_MAX - 3;
411
412 snd_soc_dai_init_dma_data(dai,
413 &mcpdm->dma_data[SNDRV_PCM_STREAM_PLAYBACK],
414 &mcpdm->dma_data[SNDRV_PCM_STREAM_CAPTURE]);
415
416 return ret;
417}
418
419static int omap_mcpdm_remove(struct snd_soc_dai *dai)
420{
421 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
422
423 free_irq(mcpdm->irq, (void *)mcpdm);
424 pm_runtime_disable(mcpdm->dev);
425
426 return 0;
427}
428
429#ifdef CONFIG_PM_SLEEP
430static int omap_mcpdm_suspend(struct snd_soc_dai *dai)
431{
432 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
433
434 if (dai->active) {
435 omap_mcpdm_stop(mcpdm);
436 omap_mcpdm_close_streams(mcpdm);
437 }
438
439 mcpdm->pm_active_count = 0;
440 while (pm_runtime_active(mcpdm->dev)) {
441 pm_runtime_put_sync(mcpdm->dev);
442 mcpdm->pm_active_count++;
443 }
444
445 return 0;
446}
447
448static int omap_mcpdm_resume(struct snd_soc_dai *dai)
449{
450 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(dai);
451
452 if (mcpdm->pm_active_count) {
453 while (mcpdm->pm_active_count--)
454 pm_runtime_get_sync(mcpdm->dev);
455
456 if (dai->active) {
457 omap_mcpdm_open_streams(mcpdm);
458 omap_mcpdm_start(mcpdm);
459 }
460 }
461
462
463 return 0;
464}
465#else
466#define omap_mcpdm_suspend NULL
467#define omap_mcpdm_resume NULL
468#endif
469
470#define OMAP_MCPDM_RATES (SNDRV_PCM_RATE_88200 | SNDRV_PCM_RATE_96000)
471#define OMAP_MCPDM_FORMATS SNDRV_PCM_FMTBIT_S32_LE
472
473static struct snd_soc_dai_driver omap_mcpdm_dai = {
474 .probe = omap_mcpdm_probe,
475 .remove = omap_mcpdm_remove,
476 .suspend = omap_mcpdm_suspend,
477 .resume = omap_mcpdm_resume,
478 .probe_order = SND_SOC_COMP_ORDER_LATE,
479 .remove_order = SND_SOC_COMP_ORDER_EARLY,
480 .playback = {
481 .channels_min = 1,
482 .channels_max = 5,
483 .rates = OMAP_MCPDM_RATES,
484 .formats = OMAP_MCPDM_FORMATS,
485 .sig_bits = 24,
486 },
487 .capture = {
488 .channels_min = 1,
489 .channels_max = 3,
490 .rates = OMAP_MCPDM_RATES,
491 .formats = OMAP_MCPDM_FORMATS,
492 .sig_bits = 24,
493 },
494 .ops = &omap_mcpdm_dai_ops,
495};
496
497static const struct snd_soc_component_driver omap_mcpdm_component = {
498 .name = "omap-mcpdm",
499};
500
501void omap_mcpdm_configure_dn_offsets(struct snd_soc_pcm_runtime *rtd,
502 u8 rx1, u8 rx2)
503{
504 struct omap_mcpdm *mcpdm = snd_soc_dai_get_drvdata(rtd->cpu_dai);
505
506 mcpdm->dn_rx_offset = MCPDM_DNOFST_RX1(rx1) | MCPDM_DNOFST_RX2(rx2);
507}
508EXPORT_SYMBOL_GPL(omap_mcpdm_configure_dn_offsets);
509
510static int asoc_mcpdm_probe(struct platform_device *pdev)
511{
512 struct omap_mcpdm *mcpdm;
513 struct resource *res;
514 int ret;
515
516 mcpdm = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcpdm), GFP_KERNEL);
517 if (!mcpdm)
518 return -ENOMEM;
519
520 platform_set_drvdata(pdev, mcpdm);
521
522 mutex_init(&mcpdm->mutex);
523
524 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
525 if (res == NULL)
526 return -ENOMEM;
527
528 mcpdm->dma_data[0].addr = res->start + MCPDM_REG_DN_DATA;
529 mcpdm->dma_data[1].addr = res->start + MCPDM_REG_UP_DATA;
530
531 mcpdm->dma_data[0].filter_data = "dn_link";
532 mcpdm->dma_data[1].filter_data = "up_link";
533
534 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
535 mcpdm->io_base = devm_ioremap_resource(&pdev->dev, res);
536 if (IS_ERR(mcpdm->io_base))
537 return PTR_ERR(mcpdm->io_base);
538
539 mcpdm->irq = platform_get_irq(pdev, 0);
540 if (mcpdm->irq < 0)
541 return mcpdm->irq;
542
543 mcpdm->dev = &pdev->dev;
544
545 ret = devm_snd_soc_register_component(&pdev->dev,
546 &omap_mcpdm_component,
547 &omap_mcpdm_dai, 1);
548 if (ret)
549 return ret;
550
551 return omap_pcm_platform_register(&pdev->dev);
552}
553
554static const struct of_device_id omap_mcpdm_of_match[] = {
555 { .compatible = "ti,omap4-mcpdm", },
556 { }
557};
558MODULE_DEVICE_TABLE(of, omap_mcpdm_of_match);
559
560static struct platform_driver asoc_mcpdm_driver = {
561 .driver = {
562 .name = "omap-mcpdm",
563 .of_match_table = omap_mcpdm_of_match,
564 },
565
566 .probe = asoc_mcpdm_probe,
567};
568
569module_platform_driver(asoc_mcpdm_driver);
570
571MODULE_ALIAS("platform:omap-mcpdm");
572MODULE_AUTHOR("Misael Lopez Cruz <misael.lopez@ti.com>");
573MODULE_DESCRIPTION("OMAP PDM SoC Interface");
574MODULE_LICENSE("GPL");
575
