1/* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License, version 2, as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, write to the Free Software 13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 14 * 15 * Copyright IBM Corp. 2007 16 * 17 * Authors: Hollis Blanchard <hollisb@us.ibm.com> 18 */ 19 20#ifndef __LINUX_KVM_POWERPC_H 21#define __LINUX_KVM_POWERPC_H 22 23#include <linux/types.h> 24 25/* Select powerpc specific features in <linux/kvm.h> */ 26#define __KVM_HAVE_SPAPR_TCE 27#define __KVM_HAVE_PPC_SMT 28#define __KVM_HAVE_IRQCHIP 29#define __KVM_HAVE_IRQ_LINE 30#define __KVM_HAVE_GUEST_DEBUG 31 32/* Not always available, but if it is, this is the correct offset. */ 33#define KVM_COALESCED_MMIO_PAGE_OFFSET 1 34 35struct kvm_regs { 36 __u64 pc; 37 __u64 cr; 38 __u64 ctr; 39 __u64 lr; 40 __u64 xer; 41 __u64 msr; 42 __u64 srr0; 43 __u64 srr1; 44 __u64 pid; 45 46 __u64 sprg0; 47 __u64 sprg1; 48 __u64 sprg2; 49 __u64 sprg3; 50 __u64 sprg4; 51 __u64 sprg5; 52 __u64 sprg6; 53 __u64 sprg7; 54 55 __u64 gpr[32]; 56}; 57 58#define KVM_SREGS_E_IMPL_NONE 0 59#define KVM_SREGS_E_IMPL_FSL 1 60 61#define KVM_SREGS_E_FSL_PIDn (1 << 0) /* PID1/PID2 */ 62 63/* 64 * Feature bits indicate which sections of the sregs struct are valid, 65 * both in KVM_GET_SREGS and KVM_SET_SREGS. On KVM_SET_SREGS, registers 66 * corresponding to unset feature bits will not be modified. This allows 67 * restoring a checkpoint made without that feature, while keeping the 68 * default values of the new registers. 69 * 70 * KVM_SREGS_E_BASE contains: 71 * CSRR0/1 (refers to SRR2/3 on 40x) 72 * ESR 73 * DEAR 74 * MCSR 75 * TSR 76 * TCR 77 * DEC 78 * TB 79 * VRSAVE (USPRG0) 80 */ 81#define KVM_SREGS_E_BASE (1 << 0) 82 83/* 84 * KVM_SREGS_E_ARCH206 contains: 85 * 86 * PIR 87 * MCSRR0/1 88 * DECAR 89 * IVPR 90 */ 91#define KVM_SREGS_E_ARCH206 (1 << 1) 92 93/* 94 * Contains EPCR, plus the upper half of 64-bit registers 95 * that are 32-bit on 32-bit implementations. 96 */ 97#define KVM_SREGS_E_64 (1 << 2) 98 99#define KVM_SREGS_E_SPRG8 (1 << 3) 100#define KVM_SREGS_E_MCIVPR (1 << 4) 101 102/* 103 * IVORs are used -- contains IVOR0-15, plus additional IVORs 104 * in combination with an appropriate feature bit. 105 */ 106#define KVM_SREGS_E_IVOR (1 << 5) 107 108/* 109 * Contains MAS0-4, MAS6-7, TLBnCFG, MMUCFG. 110 * Also TLBnPS if MMUCFG[MAVN] = 1. 111 */ 112#define KVM_SREGS_E_ARCH206_MMU (1 << 6) 113 114/* DBSR, DBCR, IAC, DAC, DVC */ 115#define KVM_SREGS_E_DEBUG (1 << 7) 116 117/* Enhanced debug -- DSRR0/1, SPRG9 */ 118#define KVM_SREGS_E_ED (1 << 8) 119 120/* Embedded Floating Point (SPE) -- IVOR32-34 if KVM_SREGS_E_IVOR */ 121#define KVM_SREGS_E_SPE (1 << 9) 122 123/* 124 * DEPRECATED! USE ONE_REG FOR THIS ONE! 125 * External Proxy (EXP) -- EPR 126 */ 127#define KVM_SREGS_EXP (1 << 10) 128 129/* External PID (E.PD) -- EPSC/EPLC */ 130#define KVM_SREGS_E_PD (1 << 11) 131 132/* Processor Control (E.PC) -- IVOR36-37 if KVM_SREGS_E_IVOR */ 133#define KVM_SREGS_E_PC (1 << 12) 134 135/* Page table (E.PT) -- EPTCFG */ 136#define KVM_SREGS_E_PT (1 << 13) 137 138/* Embedded Performance Monitor (E.PM) -- IVOR35 if KVM_SREGS_E_IVOR */ 139#define KVM_SREGS_E_PM (1 << 14) 140 141/* 142 * Special updates: 143 * 144 * Some registers may change even while a vcpu is not running. 145 * To avoid losing these changes, by default these registers are 146 * not updated by KVM_SET_SREGS. To force an update, set the bit 147 * in u.e.update_special corresponding to the register to be updated. 148 * 149 * The update_special field is zero on return from KVM_GET_SREGS. 150 * 151 * When restoring a checkpoint, the caller can set update_special 152 * to 0xffffffff to ensure that everything is restored, even new features 153 * that the caller doesn't know about. 154 */ 155#define KVM_SREGS_E_UPDATE_MCSR (1 << 0) 156#define KVM_SREGS_E_UPDATE_TSR (1 << 1) 157#define KVM_SREGS_E_UPDATE_DEC (1 << 2) 158#define KVM_SREGS_E_UPDATE_DBSR (1 << 3) 159 160/* 161 * In KVM_SET_SREGS, reserved/pad fields must be left untouched from a 162 * previous KVM_GET_REGS. 163 * 164 * Unless otherwise indicated, setting any register with KVM_SET_SREGS 165 * directly sets its value. It does not trigger any special semantics such 166 * as write-one-to-clear. Calling KVM_SET_SREGS on an unmodified struct 167 * just received from KVM_GET_SREGS is always a no-op. 168 */ 169struct kvm_sregs { 170 __u32 pvr; 171 union { 172 struct { 173 __u64 sdr1; 174 struct { 175 struct { 176 __u64 slbe; 177 __u64 slbv; 178 } slb[64]; 179 } ppc64; 180 struct { 181 __u32 sr[16]; 182 __u64 ibat[8]; 183 __u64 dbat[8]; 184 } ppc32; 185 } s; 186 struct { 187 union { 188 struct { /* KVM_SREGS_E_IMPL_FSL */ 189 __u32 features; /* KVM_SREGS_E_FSL_ */ 190 __u32 svr; 191 __u64 mcar; 192 __u32 hid0; 193 194 /* KVM_SREGS_E_FSL_PIDn */ 195 __u32 pid1, pid2; 196 } fsl; 197 __u8 pad[256]; 198 } impl; 199 200 __u32 features; /* KVM_SREGS_E_ */ 201 __u32 impl_id; /* KVM_SREGS_E_IMPL_ */ 202 __u32 update_special; /* KVM_SREGS_E_UPDATE_ */ 203 __u32 pir; /* read-only */ 204 __u64 sprg8; 205 __u64 sprg9; /* E.ED */ 206 __u64 csrr0; 207 __u64 dsrr0; /* E.ED */ 208 __u64 mcsrr0; 209 __u32 csrr1; 210 __u32 dsrr1; /* E.ED */ 211 __u32 mcsrr1; 212 __u32 esr; 213 __u64 dear; 214 __u64 ivpr; 215 __u64 mcivpr; 216 __u64 mcsr; /* KVM_SREGS_E_UPDATE_MCSR */ 217 218 __u32 tsr; /* KVM_SREGS_E_UPDATE_TSR */ 219 __u32 tcr; 220 __u32 decar; 221 __u32 dec; /* KVM_SREGS_E_UPDATE_DEC */ 222 223 /* 224 * Userspace can read TB directly, but the 225 * value reported here is consistent with "dec". 226 * 227 * Read-only. 228 */ 229 __u64 tb; 230 231 __u32 dbsr; /* KVM_SREGS_E_UPDATE_DBSR */ 232 __u32 dbcr[3]; 233 /* 234 * iac/dac registers are 64bit wide, while this API 235 * interface provides only lower 32 bits on 64 bit 236 * processors. ONE_REG interface is added for 64bit 237 * iac/dac registers. 238 */ 239 __u32 iac[4]; 240 __u32 dac[2]; 241 __u32 dvc[2]; 242 __u8 num_iac; /* read-only */ 243 __u8 num_dac; /* read-only */ 244 __u8 num_dvc; /* read-only */ 245 __u8 pad; 246 247 __u32 epr; /* EXP */ 248 __u32 vrsave; /* a.k.a. USPRG0 */ 249 __u32 epcr; /* KVM_SREGS_E_64 */ 250 251 __u32 mas0; 252 __u32 mas1; 253 __u64 mas2; 254 __u64 mas7_3; 255 __u32 mas4; 256 __u32 mas6; 257 258 __u32 ivor_low[16]; /* IVOR0-15 */ 259 __u32 ivor_high[18]; /* IVOR32+, plus room to expand */ 260 261 __u32 mmucfg; /* read-only */ 262 __u32 eptcfg; /* E.PT, read-only */ 263 __u32 tlbcfg[4];/* read-only */ 264 __u32 tlbps[4]; /* read-only */ 265 266 __u32 eplc, epsc; /* E.PD */ 267 } e; 268 __u8 pad[1020]; 269 } u; 270}; 271 272struct kvm_fpu { 273 __u64 fpr[32]; 274}; 275 276/* 277 * Defines for h/w breakpoint, watchpoint (read, write or both) and 278 * software breakpoint. 279 * These are used as "type" in KVM_SET_GUEST_DEBUG ioctl and "status" 280 * for KVM_DEBUG_EXIT. 281 */ 282#define KVMPPC_DEBUG_NONE 0x0 283#define KVMPPC_DEBUG_BREAKPOINT (1UL << 1) 284#define KVMPPC_DEBUG_WATCH_WRITE (1UL << 2) 285#define KVMPPC_DEBUG_WATCH_READ (1UL << 3) 286struct kvm_debug_exit_arch { 287 __u64 address; 288 /* 289 * exiting to userspace because of h/w breakpoint, watchpoint 290 * (read, write or both) and software breakpoint. 291 */ 292 __u32 status; 293 __u32 reserved; 294}; 295 296/* for KVM_SET_GUEST_DEBUG */ 297struct kvm_guest_debug_arch { 298 struct { 299 /* H/W breakpoint/watchpoint address */ 300 __u64 addr; 301 /* 302 * Type denotes h/w breakpoint, read watchpoint, write 303 * watchpoint or watchpoint (both read and write). 304 */ 305 __u32 type; 306 __u32 reserved; 307 } bp[16]; 308}; 309 310/* Debug related defines */ 311/* 312 * kvm_guest_debug->control is a 32 bit field. The lower 16 bits are generic 313 * and upper 16 bits are architecture specific. Architecture specific defines 314 * that ioctl is for setting hardware breakpoint or software breakpoint. 315 */ 316#define KVM_GUESTDBG_USE_SW_BP 0x00010000 317#define KVM_GUESTDBG_USE_HW_BP 0x00020000 318 319/* definition of registers in kvm_run */ 320struct kvm_sync_regs { 321}; 322 323#define KVM_INTERRUPT_SET -1U 324#define KVM_INTERRUPT_UNSET -2U 325#define KVM_INTERRUPT_SET_LEVEL -3U 326 327#define KVM_CPU_440 1 328#define KVM_CPU_E500V2 2 329#define KVM_CPU_3S_32 3 330#define KVM_CPU_3S_64 4 331#define KVM_CPU_E500MC 5 332 333/* for KVM_CAP_SPAPR_TCE */ 334struct kvm_create_spapr_tce { 335 __u64 liobn; 336 __u32 window_size; 337}; 338 339/* for KVM_CAP_SPAPR_TCE_64 */ 340struct kvm_create_spapr_tce_64 { 341 __u64 liobn; 342 __u32 page_shift; 343 __u32 flags; 344 __u64 offset; /* in pages */ 345 __u64 size; /* in pages */ 346}; 347 348/* for KVM_ALLOCATE_RMA */ 349struct kvm_allocate_rma { 350 __u64 rma_size; 351}; 352 353/* for KVM_CAP_PPC_RTAS */ 354struct kvm_rtas_token_args { 355 char name[120]; 356 __u64 token; /* Use a token of 0 to undefine a mapping */ 357}; 358 359struct kvm_book3e_206_tlb_entry { 360 __u32 mas8; 361 __u32 mas1; 362 __u64 mas2; 363 __u64 mas7_3; 364}; 365 366struct kvm_book3e_206_tlb_params { 367 /* 368 * For mmu types KVM_MMU_FSL_BOOKE_NOHV and KVM_MMU_FSL_BOOKE_HV: 369 * 370 * - The number of ways of TLB0 must be a power of two between 2 and 371 * 16. 372 * - TLB1 must be fully associative. 373 * - The size of TLB0 must be a multiple of the number of ways, and 374 * the number of sets must be a power of two. 375 * - The size of TLB1 may not exceed 64 entries. 376 * - TLB0 supports 4 KiB pages. 377 * - The page sizes supported by TLB1 are as indicated by 378 * TLB1CFG (if MMUCFG[MAVN] = 0) or TLB1PS (if MMUCFG[MAVN] = 1) 379 * as returned by KVM_GET_SREGS. 380 * - TLB2 and TLB3 are reserved, and their entries in tlb_sizes[] 381 * and tlb_ways[] must be zero. 382 * 383 * tlb_ways[n] = tlb_sizes[n] means the array is fully associative. 384 * 385 * KVM will adjust TLBnCFG based on the sizes configured here, 386 * though arrays greater than 2048 entries will have TLBnCFG[NENTRY] 387 * set to zero. 388 */ 389 __u32 tlb_sizes[4]; 390 __u32 tlb_ways[4]; 391 __u32 reserved[8]; 392}; 393 394/* For KVM_PPC_GET_HTAB_FD */ 395struct kvm_get_htab_fd { 396 __u64 flags; 397 __u64 start_index; 398 __u64 reserved[2]; 399}; 400 401/* Values for kvm_get_htab_fd.flags */ 402#define KVM_GET_HTAB_BOLTED_ONLY ((__u64)0x1) 403#define KVM_GET_HTAB_WRITE ((__u64)0x2) 404 405/* 406 * Data read on the file descriptor is formatted as a series of 407 * records, each consisting of a header followed by a series of 408 * `n_valid' HPTEs (16 bytes each), which are all valid. Following 409 * those valid HPTEs there are `n_invalid' invalid HPTEs, which 410 * are not represented explicitly in the stream. The same format 411 * is used for writing. 412 */ 413struct kvm_get_htab_header { 414 __u32 index; 415 __u16 n_valid; 416 __u16 n_invalid; 417}; 418 419/* For KVM_PPC_CONFIGURE_V3_MMU */ 420struct kvm_ppc_mmuv3_cfg { 421 __u64 flags; 422 __u64 process_table; /* second doubleword of partition table entry */ 423}; 424 425/* Flag values for KVM_PPC_CONFIGURE_V3_MMU */ 426#define KVM_PPC_MMUV3_RADIX 1 /* 1 = radix mode, 0 = HPT */ 427#define KVM_PPC_MMUV3_GTSE 2 /* global translation shootdown enb. */ 428 429/* For KVM_PPC_GET_RMMU_INFO */ 430struct kvm_ppc_rmmu_info { 431 struct kvm_ppc_radix_geom { 432 __u8 page_shift; 433 __u8 level_bits[4]; 434 __u8 pad[3]; 435 } geometries[8]; 436 __u32 ap_encodings[8]; 437}; 438 439/* Per-vcpu XICS interrupt controller state */ 440#define KVM_REG_PPC_ICP_STATE (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8c) 441 442#define KVM_REG_PPC_ICP_CPPR_SHIFT 56 /* current proc priority */ 443#define KVM_REG_PPC_ICP_CPPR_MASK 0xff 444#define KVM_REG_PPC_ICP_XISR_SHIFT 32 /* interrupt status field */ 445#define KVM_REG_PPC_ICP_XISR_MASK 0xffffff 446#define KVM_REG_PPC_ICP_MFRR_SHIFT 24 /* pending IPI priority */ 447#define KVM_REG_PPC_ICP_MFRR_MASK 0xff 448#define KVM_REG_PPC_ICP_PPRI_SHIFT 16 /* pending irq priority */ 449#define KVM_REG_PPC_ICP_PPRI_MASK 0xff 450 451/* Device control API: PPC-specific devices */ 452#define KVM_DEV_MPIC_GRP_MISC 1 453#define KVM_DEV_MPIC_BASE_ADDR 0 /* 64-bit */ 454 455#define KVM_DEV_MPIC_GRP_REGISTER 2 /* 32-bit */ 456#define KVM_DEV_MPIC_GRP_IRQ_ACTIVE 3 /* 32-bit */ 457 458/* One-Reg API: PPC-specific registers */ 459#define KVM_REG_PPC_HIOR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x1) 460#define KVM_REG_PPC_IAC1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x2) 461#define KVM_REG_PPC_IAC2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3) 462#define KVM_REG_PPC_IAC3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x4) 463#define KVM_REG_PPC_IAC4 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x5) 464#define KVM_REG_PPC_DAC1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x6) 465#define KVM_REG_PPC_DAC2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x7) 466#define KVM_REG_PPC_DABR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8) 467#define KVM_REG_PPC_DSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9) 468#define KVM_REG_PPC_PURR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa) 469#define KVM_REG_PPC_SPURR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb) 470#define KVM_REG_PPC_DAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc) 471#define KVM_REG_PPC_DSISR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xd) 472#define KVM_REG_PPC_AMR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xe) 473#define KVM_REG_PPC_UAMOR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xf) 474 475#define KVM_REG_PPC_MMCR0 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x10) 476#define KVM_REG_PPC_MMCR1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x11) 477#define KVM_REG_PPC_MMCRA (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x12) 478#define KVM_REG_PPC_MMCR2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x13) 479#define KVM_REG_PPC_MMCRS (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x14) 480#define KVM_REG_PPC_SIAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x15) 481#define KVM_REG_PPC_SDAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x16) 482#define KVM_REG_PPC_SIER (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x17) 483 484#define KVM_REG_PPC_PMC1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x18) 485#define KVM_REG_PPC_PMC2 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x19) 486#define KVM_REG_PPC_PMC3 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1a) 487#define KVM_REG_PPC_PMC4 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1b) 488#define KVM_REG_PPC_PMC5 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1c) 489#define KVM_REG_PPC_PMC6 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1d) 490#define KVM_REG_PPC_PMC7 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1e) 491#define KVM_REG_PPC_PMC8 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1f) 492 493/* 32 floating-point registers */ 494#define KVM_REG_PPC_FPR0 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x20) 495#define KVM_REG_PPC_FPR(n) (KVM_REG_PPC_FPR0 + (n)) 496#define KVM_REG_PPC_FPR31 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3f) 497 498/* 32 VMX/Altivec vector registers */ 499#define KVM_REG_PPC_VR0 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x40) 500#define KVM_REG_PPC_VR(n) (KVM_REG_PPC_VR0 + (n)) 501#define KVM_REG_PPC_VR31 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x5f) 502 503/* 32 double-width FP registers for VSX */ 504/* High-order halves overlap with FP regs */ 505#define KVM_REG_PPC_VSR0 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x60) 506#define KVM_REG_PPC_VSR(n) (KVM_REG_PPC_VSR0 + (n)) 507#define KVM_REG_PPC_VSR31 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x7f) 508 509/* FP and vector status/control registers */ 510#define KVM_REG_PPC_FPSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x80) 511/* 512 * VSCR register is documented as a 32-bit register in the ISA, but it can 513 * only be accesses via a vector register. Expose VSCR as a 32-bit register 514 * even though the kernel represents it as a 128-bit vector. 515 */ 516#define KVM_REG_PPC_VSCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x81) 517 518/* Virtual processor areas */ 519/* For SLB & DTL, address in high (first) half, length in low half */ 520#define KVM_REG_PPC_VPA_ADDR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x82) 521#define KVM_REG_PPC_VPA_SLB (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x83) 522#define KVM_REG_PPC_VPA_DTL (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x84) 523 524#define KVM_REG_PPC_EPCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x85) 525#define KVM_REG_PPC_EPR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x86) 526 527/* Timer Status Register OR/CLEAR interface */ 528#define KVM_REG_PPC_OR_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x87) 529#define KVM_REG_PPC_CLEAR_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x88) 530#define KVM_REG_PPC_TCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x89) 531#define KVM_REG_PPC_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8a) 532 533/* Debugging: Special instruction for software breakpoint */ 534#define KVM_REG_PPC_DEBUG_INST (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8b) 535 536/* MMU registers */ 537#define KVM_REG_PPC_MAS0 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8c) 538#define KVM_REG_PPC_MAS1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8d) 539#define KVM_REG_PPC_MAS2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8e) 540#define KVM_REG_PPC_MAS7_3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8f) 541#define KVM_REG_PPC_MAS4 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x90) 542#define KVM_REG_PPC_MAS6 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x91) 543#define KVM_REG_PPC_MMUCFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x92) 544/* 545 * TLBnCFG fields TLBnCFG_N_ENTRY and TLBnCFG_ASSOC can be changed only using 546 * KVM_CAP_SW_TLB ioctl 547 */ 548#define KVM_REG_PPC_TLB0CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x93) 549#define KVM_REG_PPC_TLB1CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x94) 550#define KVM_REG_PPC_TLB2CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x95) 551#define KVM_REG_PPC_TLB3CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x96) 552#define KVM_REG_PPC_TLB0PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x97) 553#define KVM_REG_PPC_TLB1PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x98) 554#define KVM_REG_PPC_TLB2PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x99) 555#define KVM_REG_PPC_TLB3PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9a) 556#define KVM_REG_PPC_EPTCFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9b) 557 558/* Timebase offset */ 559#define KVM_REG_PPC_TB_OFFSET (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9c) 560 561/* POWER8 registers */ 562#define KVM_REG_PPC_SPMC1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9d) 563#define KVM_REG_PPC_SPMC2 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9e) 564#define KVM_REG_PPC_IAMR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9f) 565#define KVM_REG_PPC_TFHAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa0) 566#define KVM_REG_PPC_TFIAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa1) 567#define KVM_REG_PPC_TEXASR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa2) 568#define KVM_REG_PPC_FSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa3) 569#define KVM_REG_PPC_PSPB (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xa4) 570#define KVM_REG_PPC_EBBHR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa5) 571#define KVM_REG_PPC_EBBRR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa6) 572#define KVM_REG_PPC_BESCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa7) 573#define KVM_REG_PPC_TAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa8) 574#define KVM_REG_PPC_DPDES (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa9) 575#define KVM_REG_PPC_DAWR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xaa) 576#define KVM_REG_PPC_DAWRX (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xab) 577#define KVM_REG_PPC_CIABR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xac) 578#define KVM_REG_PPC_IC (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xad) 579#define KVM_REG_PPC_VTB (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xae) 580#define KVM_REG_PPC_CSIGR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xaf) 581#define KVM_REG_PPC_TACR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb0) 582#define KVM_REG_PPC_TCSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb1) 583#define KVM_REG_PPC_PID (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb2) 584#define KVM_REG_PPC_ACOP (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb3) 585 586#define KVM_REG_PPC_VRSAVE (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb4) 587#define KVM_REG_PPC_LPCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb5) 588#define KVM_REG_PPC_LPCR_64 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb5) 589#define KVM_REG_PPC_PPR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb6) 590 591/* Architecture compatibility level */ 592#define KVM_REG_PPC_ARCH_COMPAT (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb7) 593 594#define KVM_REG_PPC_DABRX (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb8) 595#define KVM_REG_PPC_WORT (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb9) 596#define KVM_REG_PPC_SPRG9 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xba) 597#define KVM_REG_PPC_DBSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbb) 598 599/* POWER9 registers */ 600#define KVM_REG_PPC_TIDR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbc) 601#define KVM_REG_PPC_PSSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xbd) 602 603/* Transactional Memory checkpointed state: 604 * This is all GPRs, all VSX regs and a subset of SPRs 605 */ 606#define KVM_REG_PPC_TM (KVM_REG_PPC | 0x80000000) 607/* TM GPRs */ 608#define KVM_REG_PPC_TM_GPR0 (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0) 609#define KVM_REG_PPC_TM_GPR(n) (KVM_REG_PPC_TM_GPR0 + (n)) 610#define KVM_REG_PPC_TM_GPR31 (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x1f) 611/* TM VSX */ 612#define KVM_REG_PPC_TM_VSR0 (KVM_REG_PPC_TM | KVM_REG_SIZE_U128 | 0x20) 613#define KVM_REG_PPC_TM_VSR(n) (KVM_REG_PPC_TM_VSR0 + (n)) 614#define KVM_REG_PPC_TM_VSR63 (KVM_REG_PPC_TM | KVM_REG_SIZE_U128 | 0x5f) 615/* TM SPRS */ 616#define KVM_REG_PPC_TM_CR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x60) 617#define KVM_REG_PPC_TM_LR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x61) 618#define KVM_REG_PPC_TM_CTR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x62) 619#define KVM_REG_PPC_TM_FPSCR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x63) 620#define KVM_REG_PPC_TM_AMR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x64) 621#define KVM_REG_PPC_TM_PPR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x65) 622#define KVM_REG_PPC_TM_VRSAVE (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x66) 623#define KVM_REG_PPC_TM_VSCR (KVM_REG_PPC_TM | KVM_REG_SIZE_U32 | 0x67) 624#define KVM_REG_PPC_TM_DSCR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x68) 625#define KVM_REG_PPC_TM_TAR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x69) 626#define KVM_REG_PPC_TM_XER (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x6a) 627 628/* PPC64 eXternal Interrupt Controller Specification */ 629#define KVM_DEV_XICS_GRP_SOURCES 1 /* 64-bit source attributes */ 630 631/* Layout of 64-bit source attribute values */ 632#define KVM_XICS_DESTINATION_SHIFT 0 633#define KVM_XICS_DESTINATION_MASK 0xffffffffULL 634#define KVM_XICS_PRIORITY_SHIFT 32 635#define KVM_XICS_PRIORITY_MASK 0xff 636#define KVM_XICS_LEVEL_SENSITIVE (1ULL << 40) 637#define KVM_XICS_MASKED (1ULL << 41) 638#define KVM_XICS_PENDING (1ULL << 42) 639#define KVM_XICS_PRESENTED (1ULL << 43) 640#define KVM_XICS_QUEUED (1ULL << 44) 641 642#endif /* __LINUX_KVM_POWERPC_H */ 643