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22#include <asm/irq_regs.h>
23#include <asm/perf_event.h>
24#include <asm/sysreg.h>
25#include <asm/virt.h>
26
27#include <linux/acpi.h>
28#include <linux/of.h>
29#include <linux/perf/arm_pmu.h>
30#include <linux/platform_device.h>
31
32
33
34
35
36
37
38#define ARMV8_PMUV3_PERFCTR_INST_RETIRED 0x08
39#define ARMV8_PMUV3_PERFCTR_INST_SPEC 0x1B
40
41
42#define ARMV8_PMUV3_PERFCTR_LD_RETIRED 0x06
43#define ARMV8_PMUV3_PERFCTR_ST_RETIRED 0x07
44#define ARMV8_PMUV3_PERFCTR_EXC_TAKEN 0x09
45#define ARMV8_PMUV3_PERFCTR_EXC_RETURN 0x0A
46#define ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED 0x0B
47#define ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED 0x0C
48#define ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED 0x0D
49#define ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED 0x0E
50#define ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED 0x0F
51#define ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED 0x1C
52#define ARMV8_PMUV3_PERFCTR_CHAIN 0x1E
53#define ARMV8_PMUV3_PERFCTR_BR_RETIRED 0x21
54
55
56#define ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL 0x01
57#define ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL 0x02
58#define ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL 0x05
59#define ARMV8_PMUV3_PERFCTR_MEM_ACCESS 0x13
60#define ARMV8_PMUV3_PERFCTR_L1I_CACHE 0x14
61#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB 0x15
62#define ARMV8_PMUV3_PERFCTR_L2D_CACHE 0x16
63#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL 0x17
64#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB 0x18
65#define ARMV8_PMUV3_PERFCTR_BUS_ACCESS 0x19
66#define ARMV8_PMUV3_PERFCTR_MEMORY_ERROR 0x1A
67#define ARMV8_PMUV3_PERFCTR_BUS_CYCLES 0x1D
68#define ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE 0x1F
69#define ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE 0x20
70#define ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED 0x22
71#define ARMV8_PMUV3_PERFCTR_STALL_FRONTEND 0x23
72#define ARMV8_PMUV3_PERFCTR_STALL_BACKEND 0x24
73#define ARMV8_PMUV3_PERFCTR_L1D_TLB 0x25
74#define ARMV8_PMUV3_PERFCTR_L1I_TLB 0x26
75#define ARMV8_PMUV3_PERFCTR_L2I_CACHE 0x27
76#define ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL 0x28
77#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE 0x29
78#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL 0x2A
79#define ARMV8_PMUV3_PERFCTR_L3D_CACHE 0x2B
80#define ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB 0x2C
81#define ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL 0x2D
82#define ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL 0x2E
83#define ARMV8_PMUV3_PERFCTR_L2D_TLB 0x2F
84#define ARMV8_PMUV3_PERFCTR_L2I_TLB 0x30
85
86
87#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD 0x40
88#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR 0x41
89#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD 0x42
90#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR 0x43
91#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_INNER 0x44
92#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_OUTER 0x45
93#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_VICTIM 0x46
94#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WB_CLEAN 0x47
95#define ARMV8_IMPDEF_PERFCTR_L1D_CACHE_INVAL 0x48
96
97#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD 0x4C
98#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR 0x4D
99#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD 0x4E
100#define ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR 0x4F
101#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_RD 0x50
102#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WR 0x51
103#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_RD 0x52
104#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_REFILL_WR 0x53
105
106#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_VICTIM 0x56
107#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_WB_CLEAN 0x57
108#define ARMV8_IMPDEF_PERFCTR_L2D_CACHE_INVAL 0x58
109
110#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_RD 0x5C
111#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_REFILL_WR 0x5D
112#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_RD 0x5E
113#define ARMV8_IMPDEF_PERFCTR_L2D_TLB_WR 0x5F
114
115#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD 0x60
116#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR 0x61
117#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_SHARED 0x62
118#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NOT_SHARED 0x63
119#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_NORMAL 0x64
120#define ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_PERIPH 0x65
121
122#define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_RD 0x66
123#define ARMV8_IMPDEF_PERFCTR_MEM_ACCESS_WR 0x67
124#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LD_SPEC 0x68
125#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_ST_SPEC 0x69
126#define ARMV8_IMPDEF_PERFCTR_UNALIGNED_LDST_SPEC 0x6A
127
128#define ARMV8_IMPDEF_PERFCTR_LDREX_SPEC 0x6C
129#define ARMV8_IMPDEF_PERFCTR_STREX_PASS_SPEC 0x6D
130#define ARMV8_IMPDEF_PERFCTR_STREX_FAIL_SPEC 0x6E
131#define ARMV8_IMPDEF_PERFCTR_STREX_SPEC 0x6F
132#define ARMV8_IMPDEF_PERFCTR_LD_SPEC 0x70
133#define ARMV8_IMPDEF_PERFCTR_ST_SPEC 0x71
134#define ARMV8_IMPDEF_PERFCTR_LDST_SPEC 0x72
135#define ARMV8_IMPDEF_PERFCTR_DP_SPEC 0x73
136#define ARMV8_IMPDEF_PERFCTR_ASE_SPEC 0x74
137#define ARMV8_IMPDEF_PERFCTR_VFP_SPEC 0x75
138#define ARMV8_IMPDEF_PERFCTR_PC_WRITE_SPEC 0x76
139#define ARMV8_IMPDEF_PERFCTR_CRYPTO_SPEC 0x77
140#define ARMV8_IMPDEF_PERFCTR_BR_IMMED_SPEC 0x78
141#define ARMV8_IMPDEF_PERFCTR_BR_RETURN_SPEC 0x79
142#define ARMV8_IMPDEF_PERFCTR_BR_INDIRECT_SPEC 0x7A
143
144#define ARMV8_IMPDEF_PERFCTR_ISB_SPEC 0x7C
145#define ARMV8_IMPDEF_PERFCTR_DSB_SPEC 0x7D
146#define ARMV8_IMPDEF_PERFCTR_DMB_SPEC 0x7E
147
148#define ARMV8_IMPDEF_PERFCTR_EXC_UNDEF 0x81
149#define ARMV8_IMPDEF_PERFCTR_EXC_SVC 0x82
150#define ARMV8_IMPDEF_PERFCTR_EXC_PABORT 0x83
151#define ARMV8_IMPDEF_PERFCTR_EXC_DABORT 0x84
152
153#define ARMV8_IMPDEF_PERFCTR_EXC_IRQ 0x86
154#define ARMV8_IMPDEF_PERFCTR_EXC_FIQ 0x87
155#define ARMV8_IMPDEF_PERFCTR_EXC_SMC 0x88
156
157#define ARMV8_IMPDEF_PERFCTR_EXC_HVC 0x8A
158#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_PABORT 0x8B
159#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_DABORT 0x8C
160#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_OTHER 0x8D
161#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_IRQ 0x8E
162#define ARMV8_IMPDEF_PERFCTR_EXC_TRAP_FIQ 0x8F
163#define ARMV8_IMPDEF_PERFCTR_RC_LD_SPEC 0x90
164#define ARMV8_IMPDEF_PERFCTR_RC_ST_SPEC 0x91
165
166#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_RD 0xA0
167#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WR 0xA1
168#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_RD 0xA2
169#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_REFILL_WR 0xA3
170
171#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_VICTIM 0xA6
172#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_WB_CLEAN 0xA7
173#define ARMV8_IMPDEF_PERFCTR_L3D_CACHE_INVAL 0xA8
174
175
176#define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2
177
178
179#define ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST 0xE9
180#define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS 0xEA
181#define ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS 0xEB
182#define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS 0xEC
183#define ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS 0xED
184
185
186
187
188
189
190
191
192static const unsigned armv8_pmuv3_perf_map[PERF_COUNT_HW_MAX] = {
193 PERF_MAP_ALL_UNSUPPORTED,
194 [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CPU_CYCLES,
195 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_INST_RETIRED,
196 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
197 [PERF_COUNT_HW_CACHE_MISSES] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
198 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED,
199 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
200 [PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES,
201 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV8_PMUV3_PERFCTR_STALL_FRONTEND,
202 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV8_PMUV3_PERFCTR_STALL_BACKEND,
203};
204
205static const unsigned armv8_pmuv3_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
206 [PERF_COUNT_HW_CACHE_OP_MAX]
207 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
208 PERF_CACHE_MAP_ALL_UNSUPPORTED,
209
210 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
211 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
212 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE,
213 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL,
214
215 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE,
216 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL,
217
218 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL,
219 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1D_TLB,
220
221 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL,
222 [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_L1I_TLB,
223
224 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
225 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
226 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_PMUV3_PERFCTR_BR_PRED,
227 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_PMUV3_PERFCTR_BR_MIS_PRED,
228};
229
230static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
231 [PERF_COUNT_HW_CACHE_OP_MAX]
232 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
233 PERF_CACHE_MAP_ALL_UNSUPPORTED,
234
235 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL,
236
237 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
238 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
239};
240
241static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
242 [PERF_COUNT_HW_CACHE_OP_MAX]
243 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
244 PERF_CACHE_MAP_ALL_UNSUPPORTED,
245
246 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
247 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
248 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
249 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
250
251 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
252 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
253
254 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
255 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
256};
257
258static const unsigned armv8_a73_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
259 [PERF_COUNT_HW_CACHE_OP_MAX]
260 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
261 PERF_CACHE_MAP_ALL_UNSUPPORTED,
262
263 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
264 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
265
266 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
267 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
268
269 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
270 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
271};
272
273static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
274 [PERF_COUNT_HW_CACHE_OP_MAX]
275 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
276 PERF_CACHE_MAP_ALL_UNSUPPORTED,
277
278 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
279 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
280 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
281 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_MISS_ST,
282 [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_ACCESS,
283 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1D_CACHE_PREF_MISS,
284
285 [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_ACCESS,
286 [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_THUNDER_PERFCTR_L1I_CACHE_PREF_MISS,
287
288 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
289 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
290 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
291 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
292};
293
294static const unsigned armv8_vulcan_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
295 [PERF_COUNT_HW_CACHE_OP_MAX]
296 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
297 PERF_CACHE_MAP_ALL_UNSUPPORTED,
298
299 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
300 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
301 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
302 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
303
304 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_RD,
305 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_WR,
306 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_RD,
307 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_TLB_REFILL_WR,
308
309 [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
310 [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
311};
312
313static ssize_t
314armv8pmu_events_sysfs_show(struct device *dev,
315 struct device_attribute *attr, char *page)
316{
317 struct perf_pmu_events_attr *pmu_attr;
318
319 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
320
321 return sprintf(page, "event=0x%03llx\n", pmu_attr->id);
322}
323
324#define ARMV8_EVENT_ATTR_RESOLVE(m) #m
325#define ARMV8_EVENT_ATTR(name, config) \
326 PMU_EVENT_ATTR(name, armv8_event_attr_##name, \
327 config, armv8pmu_events_sysfs_show)
328
329ARMV8_EVENT_ATTR(sw_incr, ARMV8_PMUV3_PERFCTR_SW_INCR);
330ARMV8_EVENT_ATTR(l1i_cache_refill, ARMV8_PMUV3_PERFCTR_L1I_CACHE_REFILL);
331ARMV8_EVENT_ATTR(l1i_tlb_refill, ARMV8_PMUV3_PERFCTR_L1I_TLB_REFILL);
332ARMV8_EVENT_ATTR(l1d_cache_refill, ARMV8_PMUV3_PERFCTR_L1D_CACHE_REFILL);
333ARMV8_EVENT_ATTR(l1d_cache, ARMV8_PMUV3_PERFCTR_L1D_CACHE);
334ARMV8_EVENT_ATTR(l1d_tlb_refill, ARMV8_PMUV3_PERFCTR_L1D_TLB_REFILL);
335ARMV8_EVENT_ATTR(ld_retired, ARMV8_PMUV3_PERFCTR_LD_RETIRED);
336ARMV8_EVENT_ATTR(st_retired, ARMV8_PMUV3_PERFCTR_ST_RETIRED);
337ARMV8_EVENT_ATTR(inst_retired, ARMV8_PMUV3_PERFCTR_INST_RETIRED);
338ARMV8_EVENT_ATTR(exc_taken, ARMV8_PMUV3_PERFCTR_EXC_TAKEN);
339ARMV8_EVENT_ATTR(exc_return, ARMV8_PMUV3_PERFCTR_EXC_RETURN);
340ARMV8_EVENT_ATTR(cid_write_retired, ARMV8_PMUV3_PERFCTR_CID_WRITE_RETIRED);
341ARMV8_EVENT_ATTR(pc_write_retired, ARMV8_PMUV3_PERFCTR_PC_WRITE_RETIRED);
342ARMV8_EVENT_ATTR(br_immed_retired, ARMV8_PMUV3_PERFCTR_BR_IMMED_RETIRED);
343ARMV8_EVENT_ATTR(br_return_retired, ARMV8_PMUV3_PERFCTR_BR_RETURN_RETIRED);
344ARMV8_EVENT_ATTR(unaligned_ldst_retired, ARMV8_PMUV3_PERFCTR_UNALIGNED_LDST_RETIRED);
345ARMV8_EVENT_ATTR(br_mis_pred, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED);
346ARMV8_EVENT_ATTR(cpu_cycles, ARMV8_PMUV3_PERFCTR_CPU_CYCLES);
347ARMV8_EVENT_ATTR(br_pred, ARMV8_PMUV3_PERFCTR_BR_PRED);
348ARMV8_EVENT_ATTR(mem_access, ARMV8_PMUV3_PERFCTR_MEM_ACCESS);
349ARMV8_EVENT_ATTR(l1i_cache, ARMV8_PMUV3_PERFCTR_L1I_CACHE);
350ARMV8_EVENT_ATTR(l1d_cache_wb, ARMV8_PMUV3_PERFCTR_L1D_CACHE_WB);
351ARMV8_EVENT_ATTR(l2d_cache, ARMV8_PMUV3_PERFCTR_L2D_CACHE);
352ARMV8_EVENT_ATTR(l2d_cache_refill, ARMV8_PMUV3_PERFCTR_L2D_CACHE_REFILL);
353ARMV8_EVENT_ATTR(l2d_cache_wb, ARMV8_PMUV3_PERFCTR_L2D_CACHE_WB);
354ARMV8_EVENT_ATTR(bus_access, ARMV8_PMUV3_PERFCTR_BUS_ACCESS);
355ARMV8_EVENT_ATTR(memory_error, ARMV8_PMUV3_PERFCTR_MEMORY_ERROR);
356ARMV8_EVENT_ATTR(inst_spec, ARMV8_PMUV3_PERFCTR_INST_SPEC);
357ARMV8_EVENT_ATTR(ttbr_write_retired, ARMV8_PMUV3_PERFCTR_TTBR_WRITE_RETIRED);
358ARMV8_EVENT_ATTR(bus_cycles, ARMV8_PMUV3_PERFCTR_BUS_CYCLES);
359
360ARMV8_EVENT_ATTR(l1d_cache_allocate, ARMV8_PMUV3_PERFCTR_L1D_CACHE_ALLOCATE);
361ARMV8_EVENT_ATTR(l2d_cache_allocate, ARMV8_PMUV3_PERFCTR_L2D_CACHE_ALLOCATE);
362ARMV8_EVENT_ATTR(br_retired, ARMV8_PMUV3_PERFCTR_BR_RETIRED);
363ARMV8_EVENT_ATTR(br_mis_pred_retired, ARMV8_PMUV3_PERFCTR_BR_MIS_PRED_RETIRED);
364ARMV8_EVENT_ATTR(stall_frontend, ARMV8_PMUV3_PERFCTR_STALL_FRONTEND);
365ARMV8_EVENT_ATTR(stall_backend, ARMV8_PMUV3_PERFCTR_STALL_BACKEND);
366ARMV8_EVENT_ATTR(l1d_tlb, ARMV8_PMUV3_PERFCTR_L1D_TLB);
367ARMV8_EVENT_ATTR(l1i_tlb, ARMV8_PMUV3_PERFCTR_L1I_TLB);
368ARMV8_EVENT_ATTR(l2i_cache, ARMV8_PMUV3_PERFCTR_L2I_CACHE);
369ARMV8_EVENT_ATTR(l2i_cache_refill, ARMV8_PMUV3_PERFCTR_L2I_CACHE_REFILL);
370ARMV8_EVENT_ATTR(l3d_cache_allocate, ARMV8_PMUV3_PERFCTR_L3D_CACHE_ALLOCATE);
371ARMV8_EVENT_ATTR(l3d_cache_refill, ARMV8_PMUV3_PERFCTR_L3D_CACHE_REFILL);
372ARMV8_EVENT_ATTR(l3d_cache, ARMV8_PMUV3_PERFCTR_L3D_CACHE);
373ARMV8_EVENT_ATTR(l3d_cache_wb, ARMV8_PMUV3_PERFCTR_L3D_CACHE_WB);
374ARMV8_EVENT_ATTR(l2d_tlb_refill, ARMV8_PMUV3_PERFCTR_L2D_TLB_REFILL);
375ARMV8_EVENT_ATTR(l2i_tlb_refill, ARMV8_PMUV3_PERFCTR_L2I_TLB_REFILL);
376ARMV8_EVENT_ATTR(l2d_tlb, ARMV8_PMUV3_PERFCTR_L2D_TLB);
377ARMV8_EVENT_ATTR(l2i_tlb, ARMV8_PMUV3_PERFCTR_L2I_TLB);
378
379static struct attribute *armv8_pmuv3_event_attrs[] = {
380 &armv8_event_attr_sw_incr.attr.attr,
381 &armv8_event_attr_l1i_cache_refill.attr.attr,
382 &armv8_event_attr_l1i_tlb_refill.attr.attr,
383 &armv8_event_attr_l1d_cache_refill.attr.attr,
384 &armv8_event_attr_l1d_cache.attr.attr,
385 &armv8_event_attr_l1d_tlb_refill.attr.attr,
386 &armv8_event_attr_ld_retired.attr.attr,
387 &armv8_event_attr_st_retired.attr.attr,
388 &armv8_event_attr_inst_retired.attr.attr,
389 &armv8_event_attr_exc_taken.attr.attr,
390 &armv8_event_attr_exc_return.attr.attr,
391 &armv8_event_attr_cid_write_retired.attr.attr,
392 &armv8_event_attr_pc_write_retired.attr.attr,
393 &armv8_event_attr_br_immed_retired.attr.attr,
394 &armv8_event_attr_br_return_retired.attr.attr,
395 &armv8_event_attr_unaligned_ldst_retired.attr.attr,
396 &armv8_event_attr_br_mis_pred.attr.attr,
397 &armv8_event_attr_cpu_cycles.attr.attr,
398 &armv8_event_attr_br_pred.attr.attr,
399 &armv8_event_attr_mem_access.attr.attr,
400 &armv8_event_attr_l1i_cache.attr.attr,
401 &armv8_event_attr_l1d_cache_wb.attr.attr,
402 &armv8_event_attr_l2d_cache.attr.attr,
403 &armv8_event_attr_l2d_cache_refill.attr.attr,
404 &armv8_event_attr_l2d_cache_wb.attr.attr,
405 &armv8_event_attr_bus_access.attr.attr,
406 &armv8_event_attr_memory_error.attr.attr,
407 &armv8_event_attr_inst_spec.attr.attr,
408 &armv8_event_attr_ttbr_write_retired.attr.attr,
409 &armv8_event_attr_bus_cycles.attr.attr,
410 &armv8_event_attr_l1d_cache_allocate.attr.attr,
411 &armv8_event_attr_l2d_cache_allocate.attr.attr,
412 &armv8_event_attr_br_retired.attr.attr,
413 &armv8_event_attr_br_mis_pred_retired.attr.attr,
414 &armv8_event_attr_stall_frontend.attr.attr,
415 &armv8_event_attr_stall_backend.attr.attr,
416 &armv8_event_attr_l1d_tlb.attr.attr,
417 &armv8_event_attr_l1i_tlb.attr.attr,
418 &armv8_event_attr_l2i_cache.attr.attr,
419 &armv8_event_attr_l2i_cache_refill.attr.attr,
420 &armv8_event_attr_l3d_cache_allocate.attr.attr,
421 &armv8_event_attr_l3d_cache_refill.attr.attr,
422 &armv8_event_attr_l3d_cache.attr.attr,
423 &armv8_event_attr_l3d_cache_wb.attr.attr,
424 &armv8_event_attr_l2d_tlb_refill.attr.attr,
425 &armv8_event_attr_l2i_tlb_refill.attr.attr,
426 &armv8_event_attr_l2d_tlb.attr.attr,
427 &armv8_event_attr_l2i_tlb.attr.attr,
428 NULL,
429};
430
431static umode_t
432armv8pmu_event_attr_is_visible(struct kobject *kobj,
433 struct attribute *attr, int unused)
434{
435 struct device *dev = kobj_to_dev(kobj);
436 struct pmu *pmu = dev_get_drvdata(dev);
437 struct arm_pmu *cpu_pmu = container_of(pmu, struct arm_pmu, pmu);
438 struct perf_pmu_events_attr *pmu_attr;
439
440 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr.attr);
441
442 if (test_bit(pmu_attr->id, cpu_pmu->pmceid_bitmap))
443 return attr->mode;
444
445 return 0;
446}
447
448static struct attribute_group armv8_pmuv3_events_attr_group = {
449 .name = "events",
450 .attrs = armv8_pmuv3_event_attrs,
451 .is_visible = armv8pmu_event_attr_is_visible,
452};
453
454PMU_FORMAT_ATTR(event, "config:0-15");
455
456static struct attribute *armv8_pmuv3_format_attrs[] = {
457 &format_attr_event.attr,
458 NULL,
459};
460
461static struct attribute_group armv8_pmuv3_format_attr_group = {
462 .name = "format",
463 .attrs = armv8_pmuv3_format_attrs,
464};
465
466
467
468
469#define ARMV8_IDX_CYCLE_COUNTER 0
470#define ARMV8_IDX_COUNTER0 1
471#define ARMV8_IDX_COUNTER_LAST(cpu_pmu) \
472 (ARMV8_IDX_CYCLE_COUNTER + cpu_pmu->num_events - 1)
473
474
475
476
477
478
479
480
481#define ARMV8_IDX_TO_COUNTER(x) \
482 (((x) - ARMV8_IDX_COUNTER0) & ARMV8_PMU_COUNTER_MASK)
483
484static inline u32 armv8pmu_pmcr_read(void)
485{
486 return read_sysreg(pmcr_el0);
487}
488
489static inline void armv8pmu_pmcr_write(u32 val)
490{
491 val &= ARMV8_PMU_PMCR_MASK;
492 isb();
493 write_sysreg(val, pmcr_el0);
494}
495
496static inline int armv8pmu_has_overflowed(u32 pmovsr)
497{
498 return pmovsr & ARMV8_PMU_OVERFLOWED_MASK;
499}
500
501static inline int armv8pmu_counter_valid(struct arm_pmu *cpu_pmu, int idx)
502{
503 return idx >= ARMV8_IDX_CYCLE_COUNTER &&
504 idx <= ARMV8_IDX_COUNTER_LAST(cpu_pmu);
505}
506
507static inline int armv8pmu_counter_has_overflowed(u32 pmnc, int idx)
508{
509 return pmnc & BIT(ARMV8_IDX_TO_COUNTER(idx));
510}
511
512static inline int armv8pmu_select_counter(int idx)
513{
514 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
515 write_sysreg(counter, pmselr_el0);
516 isb();
517
518 return idx;
519}
520
521static inline u32 armv8pmu_read_counter(struct perf_event *event)
522{
523 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
524 struct hw_perf_event *hwc = &event->hw;
525 int idx = hwc->idx;
526 u32 value = 0;
527
528 if (!armv8pmu_counter_valid(cpu_pmu, idx))
529 pr_err("CPU%u reading wrong counter %d\n",
530 smp_processor_id(), idx);
531 else if (idx == ARMV8_IDX_CYCLE_COUNTER)
532 value = read_sysreg(pmccntr_el0);
533 else if (armv8pmu_select_counter(idx) == idx)
534 value = read_sysreg(pmxevcntr_el0);
535
536 return value;
537}
538
539static inline void armv8pmu_write_counter(struct perf_event *event, u32 value)
540{
541 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
542 struct hw_perf_event *hwc = &event->hw;
543 int idx = hwc->idx;
544
545 if (!armv8pmu_counter_valid(cpu_pmu, idx))
546 pr_err("CPU%u writing wrong counter %d\n",
547 smp_processor_id(), idx);
548 else if (idx == ARMV8_IDX_CYCLE_COUNTER) {
549
550
551
552
553
554 u64 value64 = 0xffffffff00000000ULL | value;
555
556 write_sysreg(value64, pmccntr_el0);
557 } else if (armv8pmu_select_counter(idx) == idx)
558 write_sysreg(value, pmxevcntr_el0);
559}
560
561static inline void armv8pmu_write_evtype(int idx, u32 val)
562{
563 if (armv8pmu_select_counter(idx) == idx) {
564 val &= ARMV8_PMU_EVTYPE_MASK;
565 write_sysreg(val, pmxevtyper_el0);
566 }
567}
568
569static inline int armv8pmu_enable_counter(int idx)
570{
571 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
572 write_sysreg(BIT(counter), pmcntenset_el0);
573 return idx;
574}
575
576static inline int armv8pmu_disable_counter(int idx)
577{
578 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
579 write_sysreg(BIT(counter), pmcntenclr_el0);
580 return idx;
581}
582
583static inline int armv8pmu_enable_intens(int idx)
584{
585 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
586 write_sysreg(BIT(counter), pmintenset_el1);
587 return idx;
588}
589
590static inline int armv8pmu_disable_intens(int idx)
591{
592 u32 counter = ARMV8_IDX_TO_COUNTER(idx);
593 write_sysreg(BIT(counter), pmintenclr_el1);
594 isb();
595
596 write_sysreg(BIT(counter), pmovsclr_el0);
597 isb();
598
599 return idx;
600}
601
602static inline u32 armv8pmu_getreset_flags(void)
603{
604 u32 value;
605
606
607 value = read_sysreg(pmovsclr_el0);
608
609
610 value &= ARMV8_PMU_OVSR_MASK;
611 write_sysreg(value, pmovsclr_el0);
612
613 return value;
614}
615
616static void armv8pmu_enable_event(struct perf_event *event)
617{
618 unsigned long flags;
619 struct hw_perf_event *hwc = &event->hw;
620 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
621 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
622 int idx = hwc->idx;
623
624
625
626
627
628 raw_spin_lock_irqsave(&events->pmu_lock, flags);
629
630
631
632
633 armv8pmu_disable_counter(idx);
634
635
636
637
638 armv8pmu_write_evtype(idx, hwc->config_base);
639
640
641
642
643 armv8pmu_enable_intens(idx);
644
645
646
647
648 armv8pmu_enable_counter(idx);
649
650 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
651}
652
653static void armv8pmu_disable_event(struct perf_event *event)
654{
655 unsigned long flags;
656 struct hw_perf_event *hwc = &event->hw;
657 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
658 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
659 int idx = hwc->idx;
660
661
662
663
664 raw_spin_lock_irqsave(&events->pmu_lock, flags);
665
666
667
668
669 armv8pmu_disable_counter(idx);
670
671
672
673
674 armv8pmu_disable_intens(idx);
675
676 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
677}
678
679static irqreturn_t armv8pmu_handle_irq(int irq_num, void *dev)
680{
681 u32 pmovsr;
682 struct perf_sample_data data;
683 struct arm_pmu *cpu_pmu = (struct arm_pmu *)dev;
684 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);
685 struct pt_regs *regs;
686 int idx;
687
688
689
690
691 pmovsr = armv8pmu_getreset_flags();
692
693
694
695
696 if (!armv8pmu_has_overflowed(pmovsr))
697 return IRQ_NONE;
698
699
700
701
702 regs = get_irq_regs();
703
704 for (idx = 0; idx < cpu_pmu->num_events; ++idx) {
705 struct perf_event *event = cpuc->events[idx];
706 struct hw_perf_event *hwc;
707
708
709 if (!event)
710 continue;
711
712
713
714
715
716 if (!armv8pmu_counter_has_overflowed(pmovsr, idx))
717 continue;
718
719 hwc = &event->hw;
720 armpmu_event_update(event);
721 perf_sample_data_init(&data, 0, hwc->last_period);
722 if (!armpmu_event_set_period(event))
723 continue;
724
725 if (perf_event_overflow(event, &data, regs))
726 cpu_pmu->disable(event);
727 }
728
729
730
731
732
733
734
735
736 irq_work_run();
737
738 return IRQ_HANDLED;
739}
740
741static void armv8pmu_start(struct arm_pmu *cpu_pmu)
742{
743 unsigned long flags;
744 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
745
746 raw_spin_lock_irqsave(&events->pmu_lock, flags);
747
748 armv8pmu_pmcr_write(armv8pmu_pmcr_read() | ARMV8_PMU_PMCR_E);
749 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
750}
751
752static void armv8pmu_stop(struct arm_pmu *cpu_pmu)
753{
754 unsigned long flags;
755 struct pmu_hw_events *events = this_cpu_ptr(cpu_pmu->hw_events);
756
757 raw_spin_lock_irqsave(&events->pmu_lock, flags);
758
759 armv8pmu_pmcr_write(armv8pmu_pmcr_read() & ~ARMV8_PMU_PMCR_E);
760 raw_spin_unlock_irqrestore(&events->pmu_lock, flags);
761}
762
763static int armv8pmu_get_event_idx(struct pmu_hw_events *cpuc,
764 struct perf_event *event)
765{
766 int idx;
767 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu);
768 struct hw_perf_event *hwc = &event->hw;
769 unsigned long evtype = hwc->config_base & ARMV8_PMU_EVTYPE_EVENT;
770
771
772 if (evtype == ARMV8_PMUV3_PERFCTR_CPU_CYCLES) {
773 if (!test_and_set_bit(ARMV8_IDX_CYCLE_COUNTER, cpuc->used_mask))
774 return ARMV8_IDX_CYCLE_COUNTER;
775 }
776
777
778
779
780 for (idx = ARMV8_IDX_COUNTER0; idx < cpu_pmu->num_events; ++idx) {
781 if (!test_and_set_bit(idx, cpuc->used_mask))
782 return idx;
783 }
784
785
786 return -EAGAIN;
787}
788
789
790
791
792static int armv8pmu_set_event_filter(struct hw_perf_event *event,
793 struct perf_event_attr *attr)
794{
795 unsigned long config_base = 0;
796
797 if (attr->exclude_idle)
798 return -EPERM;
799
800
801
802
803
804
805
806 if (is_kernel_in_hyp_mode()) {
807 if (!attr->exclude_kernel)
808 config_base |= ARMV8_PMU_INCLUDE_EL2;
809 } else {
810 if (attr->exclude_kernel)
811 config_base |= ARMV8_PMU_EXCLUDE_EL1;
812 if (!attr->exclude_hv)
813 config_base |= ARMV8_PMU_INCLUDE_EL2;
814 }
815 if (attr->exclude_user)
816 config_base |= ARMV8_PMU_EXCLUDE_EL0;
817
818
819
820
821
822 event->config_base = config_base;
823
824 return 0;
825}
826
827static void armv8pmu_reset(void *info)
828{
829 struct arm_pmu *cpu_pmu = (struct arm_pmu *)info;
830 u32 idx, nb_cnt = cpu_pmu->num_events;
831
832
833 for (idx = ARMV8_IDX_CYCLE_COUNTER; idx < nb_cnt; ++idx) {
834 armv8pmu_disable_counter(idx);
835 armv8pmu_disable_intens(idx);
836 }
837
838
839
840
841
842 armv8pmu_pmcr_write(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C |
843 ARMV8_PMU_PMCR_LC);
844}
845
846static int __armv8_pmuv3_map_event(struct perf_event *event,
847 const unsigned (*extra_event_map)
848 [PERF_COUNT_HW_MAX],
849 const unsigned (*extra_cache_map)
850 [PERF_COUNT_HW_CACHE_MAX]
851 [PERF_COUNT_HW_CACHE_OP_MAX]
852 [PERF_COUNT_HW_CACHE_RESULT_MAX])
853{
854 int hw_event_id;
855 struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
856
857 hw_event_id = armpmu_map_event(event, &armv8_pmuv3_perf_map,
858 &armv8_pmuv3_perf_cache_map,
859 ARMV8_PMU_EVTYPE_EVENT);
860
861
862 if ((hw_event_id > 0) && (hw_event_id < ARMV8_PMUV3_MAX_COMMON_EVENTS)
863 && test_bit(hw_event_id, armpmu->pmceid_bitmap)) {
864 return hw_event_id;
865 }
866
867 return armpmu_map_event(event, extra_event_map, extra_cache_map,
868 ARMV8_PMU_EVTYPE_EVENT);
869}
870
871static int armv8_pmuv3_map_event(struct perf_event *event)
872{
873 return __armv8_pmuv3_map_event(event, NULL, NULL);
874}
875
876static int armv8_a53_map_event(struct perf_event *event)
877{
878 return __armv8_pmuv3_map_event(event, NULL, &armv8_a53_perf_cache_map);
879}
880
881static int armv8_a57_map_event(struct perf_event *event)
882{
883 return __armv8_pmuv3_map_event(event, NULL, &armv8_a57_perf_cache_map);
884}
885
886static int armv8_a73_map_event(struct perf_event *event)
887{
888 return __armv8_pmuv3_map_event(event, NULL, &armv8_a73_perf_cache_map);
889}
890
891static int armv8_thunder_map_event(struct perf_event *event)
892{
893 return __armv8_pmuv3_map_event(event, NULL,
894 &armv8_thunder_perf_cache_map);
895}
896
897static int armv8_vulcan_map_event(struct perf_event *event)
898{
899 return __armv8_pmuv3_map_event(event, NULL,
900 &armv8_vulcan_perf_cache_map);
901}
902
903struct armv8pmu_probe_info {
904 struct arm_pmu *pmu;
905 bool present;
906};
907
908static void __armv8pmu_probe_pmu(void *info)
909{
910 struct armv8pmu_probe_info *probe = info;
911 struct arm_pmu *cpu_pmu = probe->pmu;
912 u64 dfr0;
913 u32 pmceid[2];
914 int pmuver;
915
916 dfr0 = read_sysreg(id_aa64dfr0_el1);
917 pmuver = cpuid_feature_extract_signed_field(dfr0,
918 ID_AA64DFR0_PMUVER_SHIFT);
919 if (pmuver < 1)
920 return;
921
922 probe->present = true;
923
924
925 cpu_pmu->num_events = (armv8pmu_pmcr_read() >> ARMV8_PMU_PMCR_N_SHIFT)
926 & ARMV8_PMU_PMCR_N_MASK;
927
928
929 cpu_pmu->num_events += 1;
930
931 pmceid[0] = read_sysreg(pmceid0_el0);
932 pmceid[1] = read_sysreg(pmceid1_el0);
933
934 bitmap_from_u32array(cpu_pmu->pmceid_bitmap,
935 ARMV8_PMUV3_MAX_COMMON_EVENTS, pmceid,
936 ARRAY_SIZE(pmceid));
937}
938
939static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu)
940{
941 struct armv8pmu_probe_info probe = {
942 .pmu = cpu_pmu,
943 .present = false,
944 };
945 int ret;
946
947 ret = smp_call_function_any(&cpu_pmu->supported_cpus,
948 __armv8pmu_probe_pmu,
949 &probe, 1);
950 if (ret)
951 return ret;
952
953 return probe.present ? 0 : -ENODEV;
954}
955
956static int armv8_pmu_init(struct arm_pmu *cpu_pmu)
957{
958 int ret = armv8pmu_probe_pmu(cpu_pmu);
959 if (ret)
960 return ret;
961
962 cpu_pmu->handle_irq = armv8pmu_handle_irq,
963 cpu_pmu->enable = armv8pmu_enable_event,
964 cpu_pmu->disable = armv8pmu_disable_event,
965 cpu_pmu->read_counter = armv8pmu_read_counter,
966 cpu_pmu->write_counter = armv8pmu_write_counter,
967 cpu_pmu->get_event_idx = armv8pmu_get_event_idx,
968 cpu_pmu->start = armv8pmu_start,
969 cpu_pmu->stop = armv8pmu_stop,
970 cpu_pmu->reset = armv8pmu_reset,
971 cpu_pmu->max_period = (1LLU << 32) - 1,
972 cpu_pmu->set_event_filter = armv8pmu_set_event_filter;
973
974 return 0;
975}
976
977static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
978{
979 int ret = armv8_pmu_init(cpu_pmu);
980 if (ret)
981 return ret;
982
983 cpu_pmu->name = "armv8_pmuv3";
984 cpu_pmu->map_event = armv8_pmuv3_map_event;
985 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
986 &armv8_pmuv3_events_attr_group;
987 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
988 &armv8_pmuv3_format_attr_group;
989
990 return 0;
991}
992
993static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu)
994{
995 int ret = armv8_pmu_init(cpu_pmu);
996 if (ret)
997 return ret;
998
999 cpu_pmu->name = "armv8_cortex_a35";
1000 cpu_pmu->map_event = armv8_a53_map_event;
1001 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1002 &armv8_pmuv3_events_attr_group;
1003 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1004 &armv8_pmuv3_format_attr_group;
1005
1006 return 0;
1007}
1008
1009static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
1010{
1011 int ret = armv8_pmu_init(cpu_pmu);
1012 if (ret)
1013 return ret;
1014
1015 cpu_pmu->name = "armv8_cortex_a53";
1016 cpu_pmu->map_event = armv8_a53_map_event;
1017 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1018 &armv8_pmuv3_events_attr_group;
1019 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1020 &armv8_pmuv3_format_attr_group;
1021
1022 return 0;
1023}
1024
1025static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
1026{
1027 int ret = armv8_pmu_init(cpu_pmu);
1028 if (ret)
1029 return ret;
1030
1031 cpu_pmu->name = "armv8_cortex_a57";
1032 cpu_pmu->map_event = armv8_a57_map_event;
1033 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1034 &armv8_pmuv3_events_attr_group;
1035 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1036 &armv8_pmuv3_format_attr_group;
1037
1038 return 0;
1039}
1040
1041static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
1042{
1043 int ret = armv8_pmu_init(cpu_pmu);
1044 if (ret)
1045 return ret;
1046
1047 cpu_pmu->name = "armv8_cortex_a72";
1048 cpu_pmu->map_event = armv8_a57_map_event;
1049 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1050 &armv8_pmuv3_events_attr_group;
1051 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1052 &armv8_pmuv3_format_attr_group;
1053
1054 return 0;
1055}
1056
1057static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)
1058{
1059 int ret = armv8_pmu_init(cpu_pmu);
1060 if (ret)
1061 return ret;
1062
1063 cpu_pmu->name = "armv8_cortex_a73";
1064 cpu_pmu->map_event = armv8_a73_map_event;
1065 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1066 &armv8_pmuv3_events_attr_group;
1067 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1068 &armv8_pmuv3_format_attr_group;
1069
1070 return 0;
1071}
1072
1073static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
1074{
1075 int ret = armv8_pmu_init(cpu_pmu);
1076 if (ret)
1077 return ret;
1078
1079 cpu_pmu->name = "armv8_cavium_thunder";
1080 cpu_pmu->map_event = armv8_thunder_map_event;
1081 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1082 &armv8_pmuv3_events_attr_group;
1083 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1084 &armv8_pmuv3_format_attr_group;
1085
1086 return 0;
1087}
1088
1089static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
1090{
1091 int ret = armv8_pmu_init(cpu_pmu);
1092 if (ret)
1093 return ret;
1094
1095 cpu_pmu->name = "armv8_brcm_vulcan";
1096 cpu_pmu->map_event = armv8_vulcan_map_event;
1097 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
1098 &armv8_pmuv3_events_attr_group;
1099 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
1100 &armv8_pmuv3_format_attr_group;
1101
1102 return 0;
1103}
1104
1105static const struct of_device_id armv8_pmu_of_device_ids[] = {
1106 {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_init},
1107 {.compatible = "arm,cortex-a35-pmu", .data = armv8_a35_pmu_init},
1108 {.compatible = "arm,cortex-a53-pmu", .data = armv8_a53_pmu_init},
1109 {.compatible = "arm,cortex-a57-pmu", .data = armv8_a57_pmu_init},
1110 {.compatible = "arm,cortex-a72-pmu", .data = armv8_a72_pmu_init},
1111 {.compatible = "arm,cortex-a73-pmu", .data = armv8_a73_pmu_init},
1112 {.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init},
1113 {.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init},
1114 {},
1115};
1116
1117static int armv8_pmu_device_probe(struct platform_device *pdev)
1118{
1119 return arm_pmu_device_probe(pdev, armv8_pmu_of_device_ids, NULL);
1120}
1121
1122static struct platform_driver armv8_pmu_driver = {
1123 .driver = {
1124 .name = ARMV8_PMU_PDEV_NAME,
1125 .of_match_table = armv8_pmu_of_device_ids,
1126 },
1127 .probe = armv8_pmu_device_probe,
1128};
1129
1130static int __init armv8_pmu_driver_init(void)
1131{
1132 if (acpi_disabled)
1133 return platform_driver_register(&armv8_pmu_driver);
1134 else
1135 return arm_pmu_acpi_probe(armv8_pmuv3_init);
1136}
1137device_initcall(armv8_pmu_driver_init)
1138
