1
2#ifndef __ddr2_defs_h
3#define __ddr2_defs_h
4
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14
15#ifndef REG_RD
16#define REG_RD( scope, inst, reg ) \
17 REG_READ( reg_##scope##_##reg, \
18 (inst) + REG_RD_ADDR_##scope##_##reg )
19#endif
20
21#ifndef REG_WR
22#define REG_WR( scope, inst, reg, val ) \
23 REG_WRITE( reg_##scope##_##reg, \
24 (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
25#endif
26
27#ifndef REG_RD_VECT
28#define REG_RD_VECT( scope, inst, reg, index ) \
29 REG_READ( reg_##scope##_##reg, \
30 (inst) + REG_RD_ADDR_##scope##_##reg + \
31 (index) * STRIDE_##scope##_##reg )
32#endif
33
34#ifndef REG_WR_VECT
35#define REG_WR_VECT( scope, inst, reg, index, val ) \
36 REG_WRITE( reg_##scope##_##reg, \
37 (inst) + REG_WR_ADDR_##scope##_##reg + \
38 (index) * STRIDE_##scope##_##reg, (val) )
39#endif
40
41#ifndef REG_RD_INT
42#define REG_RD_INT( scope, inst, reg ) \
43 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg )
44#endif
45
46#ifndef REG_WR_INT
47#define REG_WR_INT( scope, inst, reg, val ) \
48 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg, (val) )
49#endif
50
51#ifndef REG_RD_INT_VECT
52#define REG_RD_INT_VECT( scope, inst, reg, index ) \
53 REG_READ( int, (inst) + REG_RD_ADDR_##scope##_##reg + \
54 (index) * STRIDE_##scope##_##reg )
55#endif
56
57#ifndef REG_WR_INT_VECT
58#define REG_WR_INT_VECT( scope, inst, reg, index, val ) \
59 REG_WRITE( int, (inst) + REG_WR_ADDR_##scope##_##reg + \
60 (index) * STRIDE_##scope##_##reg, (val) )
61#endif
62
63#ifndef REG_TYPE_CONV
64#define REG_TYPE_CONV( type, orgtype, val ) \
65 ( { union { orgtype o; type n; } r; r.o = val; r.n; } )
66#endif
67
68#ifndef reg_page_size
69#define reg_page_size 8192
70#endif
71
72#ifndef REG_ADDR
73#define REG_ADDR( scope, inst, reg ) \
74 ( (inst) + REG_RD_ADDR_##scope##_##reg )
75#endif
76
77#ifndef REG_ADDR_VECT
78#define REG_ADDR_VECT( scope, inst, reg, index ) \
79 ( (inst) + REG_RD_ADDR_##scope##_##reg + \
80 (index) * STRIDE_##scope##_##reg )
81#endif
82
83
84
85
86typedef struct {
87 unsigned int col_width : 4;
88 unsigned int nr_banks : 1;
89 unsigned int bw : 1;
90 unsigned int nr_ref : 4;
91 unsigned int ref_interval : 11;
92 unsigned int odt_ctrl : 2;
93 unsigned int odt_mem : 1;
94 unsigned int imp_strength : 1;
95 unsigned int auto_imp_cal : 1;
96 unsigned int imp_cal_override : 1;
97 unsigned int dll_override : 1;
98 unsigned int dummy1 : 4;
99} reg_ddr2_rw_cfg;
100#define REG_RD_ADDR_ddr2_rw_cfg 0
101#define REG_WR_ADDR_ddr2_rw_cfg 0
102
103
104typedef struct {
105 unsigned int wr : 3;
106 unsigned int rcd : 3;
107 unsigned int rp : 3;
108 unsigned int ras : 4;
109 unsigned int rfc : 7;
110 unsigned int rc : 5;
111 unsigned int rtp : 2;
112 unsigned int rtw : 3;
113 unsigned int wtr : 2;
114} reg_ddr2_rw_timing;
115#define REG_RD_ADDR_ddr2_rw_timing 4
116#define REG_WR_ADDR_ddr2_rw_timing 4
117
118
119typedef struct {
120 unsigned int cas : 3;
121 unsigned int additive : 3;
122 unsigned int dummy1 : 26;
123} reg_ddr2_rw_latency;
124#define REG_RD_ADDR_ddr2_rw_latency 8
125#define REG_WR_ADDR_ddr2_rw_latency 8
126
127
128typedef struct {
129 unsigned int en : 1;
130 unsigned int dummy1 : 31;
131} reg_ddr2_rw_phy_cfg;
132#define REG_RD_ADDR_ddr2_rw_phy_cfg 12
133#define REG_WR_ADDR_ddr2_rw_phy_cfg 12
134
135
136typedef struct {
137 unsigned int rst : 1;
138 unsigned int cal_rst : 1;
139 unsigned int cal_start : 1;
140 unsigned int dummy1 : 29;
141} reg_ddr2_rw_phy_ctrl;
142#define REG_RD_ADDR_ddr2_rw_phy_ctrl 16
143#define REG_WR_ADDR_ddr2_rw_phy_ctrl 16
144
145
146typedef struct {
147 unsigned int mrs_data : 16;
148 unsigned int cmd : 8;
149 unsigned int dummy1 : 8;
150} reg_ddr2_rw_ctrl;
151#define REG_RD_ADDR_ddr2_rw_ctrl 20
152#define REG_WR_ADDR_ddr2_rw_ctrl 20
153
154
155typedef struct {
156 unsigned int self_ref : 2;
157 unsigned int phy_en : 1;
158 unsigned int dummy1 : 29;
159} reg_ddr2_rw_pwr_down;
160#define REG_RD_ADDR_ddr2_rw_pwr_down 24
161#define REG_WR_ADDR_ddr2_rw_pwr_down 24
162
163
164typedef struct {
165 unsigned int dll_lock : 1;
166 unsigned int dll_delay_code : 7;
167 unsigned int imp_cal_done : 1;
168 unsigned int imp_cal_fault : 1;
169 unsigned int cal_imp_pu : 4;
170 unsigned int cal_imp_pd : 4;
171 unsigned int dummy1 : 14;
172} reg_ddr2_r_stat;
173#define REG_RD_ADDR_ddr2_r_stat 28
174
175
176typedef struct {
177 unsigned int imp_pu : 4;
178 unsigned int imp_pd : 4;
179 unsigned int dummy1 : 24;
180} reg_ddr2_rw_imp_ctrl;
181#define REG_RD_ADDR_ddr2_rw_imp_ctrl 32
182#define REG_WR_ADDR_ddr2_rw_imp_ctrl 32
183
184#define STRIDE_ddr2_rw_dll_ctrl 4
185
186typedef struct {
187 unsigned int mode : 1;
188 unsigned int clk_delay : 7;
189 unsigned int dummy1 : 24;
190} reg_ddr2_rw_dll_ctrl;
191#define REG_RD_ADDR_ddr2_rw_dll_ctrl 36
192#define REG_WR_ADDR_ddr2_rw_dll_ctrl 36
193
194#define STRIDE_ddr2_rw_dqs_dll_ctrl 4
195
196typedef struct {
197 unsigned int dqs90_delay : 7;
198 unsigned int dqs180_delay : 7;
199 unsigned int dqs270_delay : 7;
200 unsigned int dqs360_delay : 7;
201 unsigned int dummy1 : 4;
202} reg_ddr2_rw_dqs_dll_ctrl;
203#define REG_RD_ADDR_ddr2_rw_dqs_dll_ctrl 52
204#define REG_WR_ADDR_ddr2_rw_dqs_dll_ctrl 52
205
206
207
208enum {
209 regk_ddr2_al0 = 0x00000000,
210 regk_ddr2_al1 = 0x00000008,
211 regk_ddr2_al2 = 0x00000010,
212 regk_ddr2_al3 = 0x00000018,
213 regk_ddr2_al4 = 0x00000020,
214 regk_ddr2_auto = 0x00000003,
215 regk_ddr2_bank4 = 0x00000000,
216 regk_ddr2_bank8 = 0x00000001,
217 regk_ddr2_bl4 = 0x00000002,
218 regk_ddr2_bl8 = 0x00000003,
219 regk_ddr2_bt_il = 0x00000008,
220 regk_ddr2_bt_seq = 0x00000000,
221 regk_ddr2_bw16 = 0x00000001,
222 regk_ddr2_bw32 = 0x00000000,
223 regk_ddr2_cas2 = 0x00000020,
224 regk_ddr2_cas3 = 0x00000030,
225 regk_ddr2_cas4 = 0x00000040,
226 regk_ddr2_cas5 = 0x00000050,
227 regk_ddr2_deselect = 0x000000c0,
228 regk_ddr2_dic_weak = 0x00000002,
229 regk_ddr2_direct = 0x00000001,
230 regk_ddr2_dis = 0x00000000,
231 regk_ddr2_dll_dis = 0x00000001,
232 regk_ddr2_dll_en = 0x00000000,
233 regk_ddr2_dll_rst = 0x00000100,
234 regk_ddr2_emrs = 0x00000081,
235 regk_ddr2_emrs2 = 0x00000082,
236 regk_ddr2_emrs3 = 0x00000083,
237 regk_ddr2_full = 0x00000001,
238 regk_ddr2_hi_ref_rate = 0x00000080,
239 regk_ddr2_mrs = 0x00000080,
240 regk_ddr2_no = 0x00000000,
241 regk_ddr2_nop = 0x000000b8,
242 regk_ddr2_ocd_adj = 0x00000200,
243 regk_ddr2_ocd_default = 0x00000380,
244 regk_ddr2_ocd_drive0 = 0x00000100,
245 regk_ddr2_ocd_drive1 = 0x00000080,
246 regk_ddr2_ocd_exit = 0x00000000,
247 regk_ddr2_odt_dis = 0x00000000,
248 regk_ddr2_offs = 0x00000000,
249 regk_ddr2_pre = 0x00000090,
250 regk_ddr2_pre_all = 0x00000400,
251 regk_ddr2_pwr_down_fast = 0x00000000,
252 regk_ddr2_pwr_down_slow = 0x00001000,
253 regk_ddr2_ref = 0x00000088,
254 regk_ddr2_rtt150 = 0x00000040,
255 regk_ddr2_rtt50 = 0x00000044,
256 regk_ddr2_rtt75 = 0x00000004,
257 regk_ddr2_rw_cfg_default = 0x00186000,
258 regk_ddr2_rw_dll_ctrl_default = 0x00000000,
259 regk_ddr2_rw_dll_ctrl_size = 0x00000004,
260 regk_ddr2_rw_dqs_dll_ctrl_default = 0x00000000,
261 regk_ddr2_rw_dqs_dll_ctrl_size = 0x00000004,
262 regk_ddr2_rw_latency_default = 0x00000000,
263 regk_ddr2_rw_phy_cfg_default = 0x00000000,
264 regk_ddr2_rw_pwr_down_default = 0x00000000,
265 regk_ddr2_rw_timing_default = 0x00000000,
266 regk_ddr2_s1Gb = 0x0000001a,
267 regk_ddr2_s256Mb = 0x0000000f,
268 regk_ddr2_s2Gb = 0x00000027,
269 regk_ddr2_s4Gb = 0x00000042,
270 regk_ddr2_s512Mb = 0x00000015,
271 regk_ddr2_temp0_85 = 0x00000618,
272 regk_ddr2_temp85_95 = 0x0000030c,
273 regk_ddr2_term150 = 0x00000002,
274 regk_ddr2_term50 = 0x00000003,
275 regk_ddr2_term75 = 0x00000001,
276 regk_ddr2_test = 0x00000080,
277 regk_ddr2_weak = 0x00000000,
278 regk_ddr2_wr2 = 0x00000200,
279 regk_ddr2_wr3 = 0x00000400,
280 regk_ddr2_yes = 0x00000001
281};
282#endif
283
