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14#include <linux/irq.h>
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18
19#include <asm/m32r.h>
20#include <asm/io.h>
21
22
23
24
25#define irq2port(x) (M32R_ICU_CR1_PORTL + ((x - 1) * sizeof(unsigned long)))
26
27icu_data_t icu_data[M32700UT_NUM_CPU_IRQ];
28
29static void disable_m32700ut_irq(unsigned int irq)
30{
31 unsigned long port, data;
32
33 port = irq2port(irq);
34 data = icu_data[irq].icucr|M32R_ICUCR_ILEVEL7;
35 outl(data, port);
36}
37
38static void enable_m32700ut_irq(unsigned int irq)
39{
40 unsigned long port, data;
41
42 port = irq2port(irq);
43 data = icu_data[irq].icucr|M32R_ICUCR_IEN|M32R_ICUCR_ILEVEL6;
44 outl(data, port);
45}
46
47static void mask_m32700ut(struct irq_data *data)
48{
49 disable_m32700ut_irq(data->irq);
50}
51
52static void unmask_m32700ut(struct irq_data *data)
53{
54 enable_m32700ut_irq(data->irq);
55}
56
57static void shutdown_m32700ut(struct irq_data *data)
58{
59 unsigned long port;
60
61 port = irq2port(data->irq);
62 outl(M32R_ICUCR_ILEVEL7, port);
63}
64
65static struct irq_chip m32700ut_irq_type =
66{
67 .name = "M32700UT-IRQ",
68 .irq_shutdown = shutdown_m32700ut,
69 .irq_mask = mask_m32700ut,
70 .irq_unmask = unmask_m32700ut
71};
72
73
74
75
76#define irq2pldirq(x) ((x) - M32700UT_PLD_IRQ_BASE)
77#define pldirq2port(x) (unsigned long)((int)PLD_ICUCR1 + \
78 (((x) - 1) * sizeof(unsigned short)))
79
80typedef struct {
81 unsigned short icucr;
82} pld_icu_data_t;
83
84static pld_icu_data_t pld_icu_data[M32700UT_NUM_PLD_IRQ];
85
86static void disable_m32700ut_pld_irq(unsigned int irq)
87{
88 unsigned long port, data;
89 unsigned int pldirq;
90
91 pldirq = irq2pldirq(irq);
92 port = pldirq2port(pldirq);
93 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
94 outw(data, port);
95}
96
97static void enable_m32700ut_pld_irq(unsigned int irq)
98{
99 unsigned long port, data;
100 unsigned int pldirq;
101
102 pldirq = irq2pldirq(irq);
103 port = pldirq2port(pldirq);
104 data = pld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
105 outw(data, port);
106}
107
108static void mask_m32700ut_pld(struct irq_data *data)
109{
110 disable_m32700ut_pld_irq(data->irq);
111}
112
113static void unmask_m32700ut_pld(struct irq_data *data)
114{
115 enable_m32700ut_pld_irq(data->irq);
116 enable_m32700ut_irq(M32R_IRQ_INT1);
117}
118
119static void shutdown_m32700ut_pld_irq(struct irq_data *data)
120{
121 unsigned long port;
122 unsigned int pldirq;
123
124 pldirq = irq2pldirq(data->irq);
125 port = pldirq2port(pldirq);
126 outw(PLD_ICUCR_ILEVEL7, port);
127}
128
129static struct irq_chip m32700ut_pld_irq_type =
130{
131 .name = "M32700UT-PLD-IRQ",
132 .irq_shutdown = shutdown_m32700ut_pld_irq,
133 .irq_mask = mask_m32700ut_pld,
134 .irq_unmask = unmask_m32700ut_pld,
135};
136
137
138
139
140#define irq2lanpldirq(x) ((x) - M32700UT_LAN_PLD_IRQ_BASE)
141#define lanpldirq2port(x) (unsigned long)((int)M32700UT_LAN_ICUCR1 + \
142 (((x) - 1) * sizeof(unsigned short)))
143
144static pld_icu_data_t lanpld_icu_data[M32700UT_NUM_LAN_PLD_IRQ];
145
146static void disable_m32700ut_lanpld_irq(unsigned int irq)
147{
148 unsigned long port, data;
149 unsigned int pldirq;
150
151 pldirq = irq2lanpldirq(irq);
152 port = lanpldirq2port(pldirq);
153 data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
154 outw(data, port);
155}
156
157static void enable_m32700ut_lanpld_irq(unsigned int irq)
158{
159 unsigned long port, data;
160 unsigned int pldirq;
161
162 pldirq = irq2lanpldirq(irq);
163 port = lanpldirq2port(pldirq);
164 data = lanpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
165 outw(data, port);
166}
167
168static void mask_m32700ut_lanpld(struct irq_data *data)
169{
170 disable_m32700ut_lanpld_irq(data->irq);
171}
172
173static void unmask_m32700ut_lanpld(struct irq_data *data)
174{
175 enable_m32700ut_lanpld_irq(data->irq);
176 enable_m32700ut_irq(M32R_IRQ_INT0);
177}
178
179static void shutdown_m32700ut_lanpld(struct irq_data *data)
180{
181 unsigned long port;
182 unsigned int pldirq;
183
184 pldirq = irq2lanpldirq(data->irq);
185 port = lanpldirq2port(pldirq);
186 outw(PLD_ICUCR_ILEVEL7, port);
187}
188
189static struct irq_chip m32700ut_lanpld_irq_type =
190{
191 .name = "M32700UT-PLD-LAN-IRQ",
192 .irq_shutdown = shutdown_m32700ut_lanpld,
193 .irq_mask = mask_m32700ut_lanpld,
194 .irq_unmask = unmask_m32700ut_lanpld,
195};
196
197
198
199
200#define irq2lcdpldirq(x) ((x) - M32700UT_LCD_PLD_IRQ_BASE)
201#define lcdpldirq2port(x) (unsigned long)((int)M32700UT_LCD_ICUCR1 + \
202 (((x) - 1) * sizeof(unsigned short)))
203
204#ifdef CONFIG_USB
205static pld_icu_data_t lcdpld_icu_data[M32700UT_NUM_LCD_PLD_IRQ];
206
207static void disable_m32700ut_lcdpld_irq(unsigned int irq)
208{
209 unsigned long port, data;
210 unsigned int pldirq;
211
212 pldirq = irq2lcdpldirq(irq);
213 port = lcdpldirq2port(pldirq);
214 data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_ILEVEL7;
215 outw(data, port);
216}
217
218static void enable_m32700ut_lcdpld_irq(unsigned int irq)
219{
220 unsigned long port, data;
221 unsigned int pldirq;
222
223 pldirq = irq2lcdpldirq(irq);
224 port = lcdpldirq2port(pldirq);
225 data = lcdpld_icu_data[pldirq].icucr|PLD_ICUCR_IEN|PLD_ICUCR_ILEVEL6;
226 outw(data, port);
227}
228
229static void mask_m32700ut_lcdpld(struct irq_data *data)
230{
231 disable_m32700ut_lcdpld_irq(data->irq);
232}
233
234static void unmask_m32700ut_lcdpld(struct irq_data *data)
235{
236 enable_m32700ut_lcdpld_irq(data->irq);
237 enable_m32700ut_irq(M32R_IRQ_INT2);
238}
239
240static void shutdown_m32700ut_lcdpld(struct irq_data *data)
241{
242 unsigned long port;
243 unsigned int pldirq;
244
245 pldirq = irq2lcdpldirq(data->irq);
246 port = lcdpldirq2port(pldirq);
247 outw(PLD_ICUCR_ILEVEL7, port);
248}
249
250static struct irq_chip m32700ut_lcdpld_irq_type =
251{
252 .name = "M32700UT-PLD-LCD-IRQ",
253 .irq_shutdown = shutdown_m32700ut_lcdpld,
254 .irq_mask = mask_m32700ut_lcdpld,
255 .irq_unmask = unmask_m32700ut_lcdpld,
256};
257#endif
258
259void __init init_IRQ(void)
260{
261#if defined(CONFIG_SMC91X)
262
263 irq_set_chip_and_handler(M32700UT_LAN_IRQ_LAN,
264 &m32700ut_lanpld_irq_type, handle_level_irq);
265 lanpld_icu_data[irq2lanpldirq(M32700UT_LAN_IRQ_LAN)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;
266 disable_m32700ut_lanpld_irq(M32700UT_LAN_IRQ_LAN);
267#endif
268
269
270 irq_set_chip_and_handler(M32R_IRQ_MFT2, &m32700ut_irq_type,
271 handle_level_irq);
272 icu_data[M32R_IRQ_MFT2].icucr = M32R_ICUCR_IEN;
273 disable_m32700ut_irq(M32R_IRQ_MFT2);
274
275
276 irq_set_chip_and_handler(M32R_IRQ_SIO0_R, &m32700ut_irq_type,
277 handle_level_irq);
278 icu_data[M32R_IRQ_SIO0_R].icucr = 0;
279 disable_m32700ut_irq(M32R_IRQ_SIO0_R);
280
281
282 irq_set_chip_and_handler(M32R_IRQ_SIO0_S, &m32700ut_irq_type,
283 handle_level_irq);
284 icu_data[M32R_IRQ_SIO0_S].icucr = 0;
285 disable_m32700ut_irq(M32R_IRQ_SIO0_S);
286
287
288 irq_set_chip_and_handler(M32R_IRQ_SIO1_R, &m32700ut_irq_type,
289 handle_level_irq);
290 icu_data[M32R_IRQ_SIO1_R].icucr = 0;
291 disable_m32700ut_irq(M32R_IRQ_SIO1_R);
292
293
294 irq_set_chip_and_handler(M32R_IRQ_SIO1_S, &m32700ut_irq_type,
295 handle_level_irq);
296 icu_data[M32R_IRQ_SIO1_S].icucr = 0;
297 disable_m32700ut_irq(M32R_IRQ_SIO1_S);
298
299
300 irq_set_chip_and_handler(M32R_IRQ_DMA1, &m32700ut_irq_type,
301 handle_level_irq);
302 icu_data[M32R_IRQ_DMA1].icucr = 0;
303 disable_m32700ut_irq(M32R_IRQ_DMA1);
304
305#ifdef CONFIG_SERIAL_M32R_PLDSIO
306
307 irq_set_chip_and_handler(PLD_IRQ_SIO0_RCV, &m32700ut_pld_irq_type,
308 handle_level_irq);
309 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_RCV)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
310 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_RCV);
311
312
313 irq_set_chip_and_handler(PLD_IRQ_SIO0_SND, &m32700ut_pld_irq_type,
314 handle_level_irq);
315 pld_icu_data[irq2pldirq(PLD_IRQ_SIO0_SND)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD03;
316 disable_m32700ut_pld_irq(PLD_IRQ_SIO0_SND);
317#endif
318
319
320 irq_set_chip_and_handler(PLD_IRQ_CFIREQ, &m32700ut_pld_irq_type,
321 handle_level_irq);
322 pld_icu_data[irq2pldirq(PLD_IRQ_CFIREQ)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;
323 disable_m32700ut_pld_irq(PLD_IRQ_CFIREQ);
324
325
326 irq_set_chip_and_handler(PLD_IRQ_CFC_INSERT, &m32700ut_pld_irq_type,
327 handle_level_irq);
328 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_INSERT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD00;
329 disable_m32700ut_pld_irq(PLD_IRQ_CFC_INSERT);
330
331
332 irq_set_chip_and_handler(PLD_IRQ_CFC_EJECT, &m32700ut_pld_irq_type,
333 handle_level_irq);
334 pld_icu_data[irq2pldirq(PLD_IRQ_CFC_EJECT)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD02;
335 disable_m32700ut_pld_irq(PLD_IRQ_CFC_EJECT);
336
337
338
339
340
341 icu_data[M32R_IRQ_INT0].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
342 enable_m32700ut_irq(M32R_IRQ_INT0);
343
344
345
346
347
348 icu_data[M32R_IRQ_INT1].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD11;
349 enable_m32700ut_irq(M32R_IRQ_INT1);
350
351#if defined(CONFIG_USB)
352 outw(USBCR_OTGS, USBCR);
353 irq_set_chip_and_handler(M32700UT_LCD_IRQ_USB_INT1,
354 &m32700ut_lcdpld_irq_type, handle_level_irq);
355
356 lcdpld_icu_data[irq2lcdpldirq(M32700UT_LCD_IRQ_USB_INT1)].icucr = PLD_ICUCR_IEN|PLD_ICUCR_ISMOD01;
357 disable_m32700ut_lcdpld_irq(M32700UT_LCD_IRQ_USB_INT1);
358#endif
359
360
361
362
363 icu_data[M32R_IRQ_INT2].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD01;
364 enable_m32700ut_irq(M32R_IRQ_INT2);
365
366#if defined(CONFIG_VIDEO_M32R_AR)
367
368
369
370 irq_set_chip_and_handler(M32R_IRQ_INT3, &m32700ut_irq_type,
371 handle_level_irq);
372 icu_data[M32R_IRQ_INT3].icucr = M32R_ICUCR_IEN|M32R_ICUCR_ISMOD10;
373 disable_m32700ut_irq(M32R_IRQ_INT3);
374#endif
375}
376
377#if defined(CONFIG_SMC91X)
378
379#define LAN_IOSTART 0x300
380#define LAN_IOEND 0x320
381static struct resource smc91x_resources[] = {
382 [0] = {
383 .start = (LAN_IOSTART),
384 .end = (LAN_IOEND),
385 .flags = IORESOURCE_MEM,
386 },
387 [1] = {
388 .start = M32700UT_LAN_IRQ_LAN,
389 .end = M32700UT_LAN_IRQ_LAN,
390 .flags = IORESOURCE_IRQ,
391 }
392};
393
394static struct platform_device smc91x_device = {
395 .name = "smc91x",
396 .id = 0,
397 .num_resources = ARRAY_SIZE(smc91x_resources),
398 .resource = smc91x_resources,
399};
400#endif
401
402#if defined(CONFIG_FB_S1D13XXX)
403
404#include <video/s1d13xxxfb.h>
405#include <asm/s1d13806.h>
406
407static struct s1d13xxxfb_pdata s1d13xxxfb_data = {
408 .initregs = s1d13xxxfb_initregs,
409 .initregssize = ARRAY_SIZE(s1d13xxxfb_initregs),
410 .platform_init_video = NULL,
411#ifdef CONFIG_PM
412 .platform_suspend_video = NULL,
413 .platform_resume_video = NULL,
414#endif
415};
416
417static struct resource s1d13xxxfb_resources[] = {
418 [0] = {
419 .start = 0x10600000UL,
420 .end = 0x1073FFFFUL,
421 .flags = IORESOURCE_MEM,
422 },
423 [1] = {
424 .start = 0x10400000UL,
425 .end = 0x104001FFUL,
426 .flags = IORESOURCE_MEM,
427 }
428};
429
430static struct platform_device s1d13xxxfb_device = {
431 .name = S1D_DEVICENAME,
432 .id = 0,
433 .dev = {
434 .platform_data = &s1d13xxxfb_data,
435 },
436 .num_resources = ARRAY_SIZE(s1d13xxxfb_resources),
437 .resource = s1d13xxxfb_resources,
438};
439#endif
440
441static int __init platform_init(void)
442{
443#if defined(CONFIG_SMC91X)
444 platform_device_register(&smc91x_device);
445#endif
446#if defined(CONFIG_FB_S1D13XXX)
447 platform_device_register(&s1d13xxxfb_device);
448#endif
449 return 0;
450}
451arch_initcall(platform_init);
452
