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28#ifndef __CVMX_H__
29#define __CVMX_H__
30
31#include <linux/kernel.h>
32#include <linux/string.h>
33
34enum cvmx_mips_space {
35 CVMX_MIPS_SPACE_XKSEG = 3LL,
36 CVMX_MIPS_SPACE_XKPHYS = 2LL,
37 CVMX_MIPS_SPACE_XSSEG = 1LL,
38 CVMX_MIPS_SPACE_XUSEG = 0LL
39};
40
41
42#define CVMX_MIPS32_SPACE_KSEG0 1l
43#define CVMX_ADD_SEG32(segment, add) \
44 (((int32_t)segment << 31) | (int32_t)(add))
45
46#define CVMX_IO_SEG CVMX_MIPS_SPACE_XKPHYS
47
48
49#define CVMX_ADD_SEG(segment, add) \
50 ((((uint64_t)segment) << 62) | (add))
51#ifndef CVMX_ADD_IO_SEG
52#define CVMX_ADD_IO_SEG(add) CVMX_ADD_SEG(CVMX_IO_SEG, (add))
53#endif
54
55#include <asm/octeon/cvmx-asm.h>
56#include <asm/octeon/cvmx-packet.h>
57#include <asm/octeon/cvmx-sysinfo.h>
58
59#include <asm/octeon/cvmx-ciu-defs.h>
60#include <asm/octeon/cvmx-ciu3-defs.h>
61#include <asm/octeon/cvmx-gpio-defs.h>
62#include <asm/octeon/cvmx-iob-defs.h>
63#include <asm/octeon/cvmx-ipd-defs.h>
64#include <asm/octeon/cvmx-l2c-defs.h>
65#include <asm/octeon/cvmx-l2d-defs.h>
66#include <asm/octeon/cvmx-l2t-defs.h>
67#include <asm/octeon/cvmx-led-defs.h>
68#include <asm/octeon/cvmx-mio-defs.h>
69#include <asm/octeon/cvmx-pow-defs.h>
70
71#include <asm/octeon/cvmx-bootinfo.h>
72#include <asm/octeon/cvmx-bootmem.h>
73#include <asm/octeon/cvmx-l2c.h>
74
75#ifndef CVMX_ENABLE_DEBUG_PRINTS
76#define CVMX_ENABLE_DEBUG_PRINTS 1
77#endif
78
79#if CVMX_ENABLE_DEBUG_PRINTS
80#define cvmx_dprintf printk
81#else
82#define cvmx_dprintf(...) {}
83#endif
84
85#define CVMX_MAX_CORES (16)
86#define CVMX_CACHE_LINE_SIZE (128)
87#define CVMX_CACHE_LINE_MASK (CVMX_CACHE_LINE_SIZE - 1)
88#define CVMX_CACHE_LINE_ALIGNED __attribute__ ((aligned(CVMX_CACHE_LINE_SIZE)))
89#define CAST64(v) ((long long)(long)(v))
90#define CASTPTR(type, v) ((type *)(long)(v))
91
92
93
94
95
96static inline uint32_t cvmx_get_proc_id(void) __attribute__ ((pure));
97static inline uint32_t cvmx_get_proc_id(void)
98{
99 uint32_t id;
100 asm("mfc0 %0, $15,0" : "=r"(id));
101 return id;
102}
103
104
105#define CVMX_TMP_STR(x) CVMX_TMP_STR2(x)
106#define CVMX_TMP_STR2(x) #x
107
108
109
110
111
112
113 static inline uint64_t cvmx_build_mask(uint64_t bits)
114{
115 return ~((~0x0ull) << bits);
116}
117
118
119
120
121
122
123
124
125static inline uint64_t cvmx_build_io_address(uint64_t major_did,
126 uint64_t sub_did)
127{
128 return (0x1ull << 48) | (major_did << 43) | (sub_did << 40);
129}
130
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146
147
148static inline uint64_t cvmx_build_bits(uint64_t high_bit,
149 uint64_t low_bit, uint64_t value)
150{
151 return (value & cvmx_build_mask(high_bit - low_bit + 1)) << low_bit;
152}
153
154
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160
161
162static inline uint64_t cvmx_ptr_to_phys(void *ptr)
163{
164 if (sizeof(void *) == 8) {
165
166
167
168
169
170
171
172
173 if ((CAST64(ptr) >> 62) == 3)
174 return CAST64(ptr) & cvmx_build_mask(30);
175 else
176 return CAST64(ptr) & cvmx_build_mask(40);
177 } else {
178 return (long)(ptr) & 0x1fffffff;
179 }
180}
181
182
183
184
185
186
187
188
189
190static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
191{
192 if (sizeof(void *) == 8) {
193
194 return CASTPTR(void,
195 CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
196 physical_address));
197 } else {
198 return CASTPTR(void,
199 CVMX_ADD_SEG32(CVMX_MIPS32_SPACE_KSEG0,
200 physical_address));
201 }
202}
203
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209
210
211#define CVMX_BUILD_WRITE64(TYPE, ST) \
212static inline void cvmx_write64_##TYPE(uint64_t addr, TYPE##_t val) \
213{ \
214 *CASTPTR(volatile TYPE##_t, addr) = val; \
215}
216
217
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223
224
225#define CVMX_BUILD_READ64(TYPE, LT) \
226static inline TYPE##_t cvmx_read64_##TYPE(uint64_t addr) \
227{ \
228 return *CASTPTR(volatile TYPE##_t, addr); \
229}
230
231
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234
235
236
237
238CVMX_BUILD_WRITE64(int64, "sd");
239CVMX_BUILD_WRITE64(int32, "sw");
240CVMX_BUILD_WRITE64(int16, "sh");
241CVMX_BUILD_WRITE64(int8, "sb");
242CVMX_BUILD_WRITE64(uint64, "sd");
243CVMX_BUILD_WRITE64(uint32, "sw");
244CVMX_BUILD_WRITE64(uint16, "sh");
245CVMX_BUILD_WRITE64(uint8, "sb");
246#define cvmx_write64 cvmx_write64_uint64
247
248
249
250
251
252
253
254CVMX_BUILD_READ64(int64, "ld");
255CVMX_BUILD_READ64(int32, "lw");
256CVMX_BUILD_READ64(int16, "lh");
257CVMX_BUILD_READ64(int8, "lb");
258CVMX_BUILD_READ64(uint64, "ld");
259CVMX_BUILD_READ64(uint32, "lw");
260CVMX_BUILD_READ64(uint16, "lhu");
261CVMX_BUILD_READ64(uint8, "lbu");
262#define cvmx_read64 cvmx_read64_uint64
263
264
265static inline void cvmx_write_csr(uint64_t csr_addr, uint64_t val)
266{
267 cvmx_write64(csr_addr, val);
268
269
270
271
272
273
274
275 if (((csr_addr >> 40) & 0x7ffff) == (0x118))
276 cvmx_read64(CVMX_MIO_BOOT_BIST_STAT);
277}
278
279static inline void cvmx_writeq_csr(void __iomem *csr_addr, uint64_t val)
280{
281 cvmx_write_csr((__force uint64_t)csr_addr, val);
282}
283
284static inline void cvmx_write_io(uint64_t io_addr, uint64_t val)
285{
286 cvmx_write64(io_addr, val);
287
288}
289
290static inline uint64_t cvmx_read_csr(uint64_t csr_addr)
291{
292 uint64_t val = cvmx_read64(csr_addr);
293 return val;
294}
295
296static inline uint64_t cvmx_readq_csr(void __iomem *csr_addr)
297{
298 return cvmx_read_csr((__force uint64_t) csr_addr);
299}
300
301static inline void cvmx_send_single(uint64_t data)
302{
303 const uint64_t CVMX_IOBDMA_SENDSINGLE = 0xffffffffffffa200ull;
304 cvmx_write64(CVMX_IOBDMA_SENDSINGLE, data);
305}
306
307static inline void cvmx_read_csr_async(uint64_t scraddr, uint64_t csr_addr)
308{
309 union {
310 uint64_t u64;
311 struct {
312 uint64_t scraddr:8;
313 uint64_t len:8;
314 uint64_t addr:48;
315 } s;
316 } addr;
317 addr.u64 = csr_addr;
318 addr.s.scraddr = scraddr >> 3;
319 addr.s.len = 1;
320 cvmx_send_single(addr.u64);
321}
322
323
324static inline int cvmx_octeon_is_pass1(void)
325{
326#if OCTEON_IS_COMMON_BINARY()
327 return 0;
328#else
329
330#if OCTEON_IS_MODEL(OCTEON_CN38XX)
331 return cvmx_get_proc_id() == OCTEON_CN38XX_PASS1;
332#else
333 return 0;
334#endif
335#endif
336}
337
338static inline unsigned int cvmx_get_core_num(void)
339{
340 unsigned int core_num;
341 CVMX_RDHWRNV(core_num, 0);
342 return core_num;
343}
344
345
346#define CVMX_NODE_NO_SHIFT 7
347#define CVMX_NODE_MASK 0x3
348static inline unsigned int cvmx_get_node_num(void)
349{
350 unsigned int core_num = cvmx_get_core_num();
351
352 return (core_num >> CVMX_NODE_NO_SHIFT) & CVMX_NODE_MASK;
353}
354
355static inline unsigned int cvmx_get_local_core_num(void)
356{
357 return cvmx_get_core_num() & ((1 << CVMX_NODE_NO_SHIFT) - 1);
358}
359
360#define CVMX_NODE_BITS (2)
361#define CVMX_MAX_NODES (1 << CVMX_NODE_BITS)
362#define CVMX_NODE_IO_SHIFT (36)
363#define CVMX_NODE_MEM_SHIFT (40)
364#define CVMX_NODE_IO_MASK ((uint64_t)CVMX_NODE_MASK << CVMX_NODE_IO_SHIFT)
365
366static inline void cvmx_write_csr_node(uint64_t node, uint64_t csr_addr,
367 uint64_t val)
368{
369 uint64_t composite_csr_addr, node_addr;
370
371 node_addr = (node & CVMX_NODE_MASK) << CVMX_NODE_IO_SHIFT;
372 composite_csr_addr = (csr_addr & ~CVMX_NODE_IO_MASK) | node_addr;
373
374 cvmx_write64_uint64(composite_csr_addr, val);
375 if (((csr_addr >> 40) & 0x7ffff) == (0x118))
376 cvmx_read64_uint64(CVMX_MIO_BOOT_BIST_STAT | node_addr);
377}
378
379static inline uint64_t cvmx_read_csr_node(uint64_t node, uint64_t csr_addr)
380{
381 uint64_t node_addr;
382
383 node_addr = (csr_addr & ~CVMX_NODE_IO_MASK) |
384 (node & CVMX_NODE_MASK) << CVMX_NODE_IO_SHIFT;
385 return cvmx_read_csr(node_addr);
386}
387
388
389
390
391
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393
394
395
396static inline uint32_t cvmx_pop(uint32_t val)
397{
398 uint32_t pop;
399 CVMX_POP(pop, val);
400 return pop;
401}
402
403
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409
410
411static inline int cvmx_dpop(uint64_t val)
412{
413 int pop;
414 CVMX_DPOP(pop, val);
415 return pop;
416}
417
418
419
420
421
422
423
424static inline uint64_t cvmx_get_cycle(void)
425{
426 uint64_t cycle;
427 CVMX_RDHWR(cycle, 31);
428 return cycle;
429}
430
431
432
433
434
435static inline void cvmx_wait(uint64_t cycles)
436{
437 uint64_t done = cvmx_get_cycle() + cycles;
438
439 while (cvmx_get_cycle() < done)
440 ;
441}
442
443
444
445
446
447
448
449
450static inline uint64_t cvmx_get_cycle_global(void)
451{
452 if (cvmx_octeon_is_pass1())
453 return 0;
454 else
455 return cvmx_read64(CVMX_IPD_CLK_COUNT);
456}
457
458
459
460
461
462
463
464
465
466
467#define CVMX_WAIT_FOR_FIELD64(address, type, field, op, value, timeout_usec)\
468 ( \
469{ \
470 int result; \
471 do { \
472 uint64_t done = cvmx_get_cycle() + (uint64_t)timeout_usec * \
473 cvmx_sysinfo_get()->cpu_clock_hz / 1000000; \
474 type c; \
475 while (1) { \
476 c.u64 = cvmx_read_csr(address); \
477 if ((c.s.field) op(value)) { \
478 result = 0; \
479 break; \
480 } else if (cvmx_get_cycle() > done) { \
481 result = -1; \
482 break; \
483 } else \
484 cvmx_wait(100); \
485 } \
486 } while (0); \
487 result; \
488})
489
490
491
492
493static inline uint32_t cvmx_octeon_num_cores(void)
494{
495 u64 ciu_fuse_reg;
496 u64 ciu_fuse;
497
498 if (OCTEON_IS_OCTEON3() && !OCTEON_IS_MODEL(OCTEON_CN70XX))
499 ciu_fuse_reg = CVMX_CIU3_FUSE;
500 else
501 ciu_fuse_reg = CVMX_CIU_FUSE;
502 ciu_fuse = cvmx_read_csr(ciu_fuse_reg);
503 return cvmx_dpop(ciu_fuse);
504}
505
506#endif
507