1
2
3
4
5
6
7
8
9
10
11
12#ifndef _ASM_POWERPC_OPAL_H
13#define _ASM_POWERPC_OPAL_H
14
15#include <asm/opal-api.h>
16
17#ifndef __ASSEMBLY__
18
19#include <linux/notifier.h>
20
21
22#define SG_ENTRIES_PER_NODE ((PAGE_SIZE - 16) / sizeof(struct opal_sg_entry))
23
24
25extern struct kobject *opal_kobj;
26
27
28extern struct device_node *opal_node;
29
30
31int64_t opal_invalid_call(void);
32int64_t opal_npu_destroy_context(uint64_t phb_id, uint64_t pid, uint64_t bdf);
33int64_t opal_npu_init_context(uint64_t phb_id, int pasid, uint64_t msr,
34 uint64_t bdf);
35int64_t opal_npu_map_lpar(uint64_t phb_id, uint64_t bdf, uint64_t lparid,
36 uint64_t lpcr);
37int64_t opal_console_write(int64_t term_number, __be64 *length,
38 const uint8_t *buffer);
39int64_t opal_console_read(int64_t term_number, __be64 *length,
40 uint8_t *buffer);
41int64_t opal_console_write_buffer_space(int64_t term_number,
42 __be64 *length);
43int64_t opal_console_flush(int64_t term_number);
44int64_t opal_rtc_read(__be32 *year_month_day,
45 __be64 *hour_minute_second_millisecond);
46int64_t opal_rtc_write(uint32_t year_month_day,
47 uint64_t hour_minute_second_millisecond);
48int64_t opal_tpo_read(uint64_t token, __be32 *year_mon_day, __be32 *hour_min);
49int64_t opal_tpo_write(uint64_t token, uint32_t year_mon_day,
50 uint32_t hour_min);
51int64_t opal_cec_power_down(uint64_t request);
52int64_t opal_cec_reboot(void);
53int64_t opal_cec_reboot2(uint32_t reboot_type, const char *diag);
54int64_t opal_read_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
55int64_t opal_write_nvram(uint64_t buffer, uint64_t size, uint64_t offset);
56int64_t opal_handle_interrupt(uint64_t isn, __be64 *outstanding_event_mask);
57int64_t opal_poll_events(__be64 *outstanding_event_mask);
58int64_t opal_pci_set_hub_tce_memory(uint64_t hub_id, uint64_t tce_mem_addr,
59 uint64_t tce_mem_size);
60int64_t opal_pci_set_phb_tce_memory(uint64_t phb_id, uint64_t tce_mem_addr,
61 uint64_t tce_mem_size);
62int64_t opal_pci_config_read_byte(uint64_t phb_id, uint64_t bus_dev_func,
63 uint64_t offset, uint8_t *data);
64int64_t opal_pci_config_read_half_word(uint64_t phb_id, uint64_t bus_dev_func,
65 uint64_t offset, __be16 *data);
66int64_t opal_pci_config_read_word(uint64_t phb_id, uint64_t bus_dev_func,
67 uint64_t offset, __be32 *data);
68int64_t opal_pci_config_write_byte(uint64_t phb_id, uint64_t bus_dev_func,
69 uint64_t offset, uint8_t data);
70int64_t opal_pci_config_write_half_word(uint64_t phb_id, uint64_t bus_dev_func,
71 uint64_t offset, uint16_t data);
72int64_t opal_pci_config_write_word(uint64_t phb_id, uint64_t bus_dev_func,
73 uint64_t offset, uint32_t data);
74int64_t opal_set_xive(uint32_t isn, uint16_t server, uint8_t priority);
75int64_t opal_get_xive(uint32_t isn, __be16 *server, uint8_t *priority);
76int64_t opal_register_exception_handler(uint64_t opal_exception,
77 uint64_t handler_address,
78 uint64_t glue_cache_line);
79int64_t opal_pci_eeh_freeze_status(uint64_t phb_id, uint64_t pe_number,
80 uint8_t *freeze_state,
81 __be16 *pci_error_type,
82 __be64 *phb_status);
83int64_t opal_pci_eeh_freeze_clear(uint64_t phb_id, uint64_t pe_number,
84 uint64_t eeh_action_token);
85int64_t opal_pci_eeh_freeze_set(uint64_t phb_id, uint64_t pe_number,
86 uint64_t eeh_action_token);
87int64_t opal_pci_err_inject(uint64_t phb_id, uint32_t pe_no, uint32_t type,
88 uint32_t func, uint64_t addr, uint64_t mask);
89int64_t opal_pci_shpc(uint64_t phb_id, uint64_t shpc_action, uint8_t *state);
90
91
92
93int64_t opal_pci_phb_mmio_enable(uint64_t phb_id, uint16_t window_type,
94 uint16_t window_num, uint16_t enable);
95int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, uint16_t window_type,
96 uint16_t window_num,
97 uint64_t starting_real_address,
98 uint64_t starting_pci_address,
99 uint64_t size);
100int64_t opal_pci_map_pe_mmio_window(uint64_t phb_id, uint16_t pe_number,
101 uint16_t window_type, uint16_t window_num,
102 uint16_t segment_num);
103int64_t opal_pci_set_phb_table_memory(uint64_t phb_id, uint64_t rtt_addr,
104 uint64_t ivt_addr, uint64_t ivt_len,
105 uint64_t reject_array_addr,
106 uint64_t peltv_addr);
107int64_t opal_pci_set_pe(uint64_t phb_id, uint64_t pe_number, uint64_t bus_dev_func,
108 uint8_t bus_compare, uint8_t dev_compare, uint8_t func_compare,
109 uint8_t pe_action);
110int64_t opal_pci_set_peltv(uint64_t phb_id, uint32_t parent_pe, uint32_t child_pe,
111 uint8_t state);
112int64_t opal_pci_set_mve(uint64_t phb_id, uint32_t mve_number, uint32_t pe_number);
113int64_t opal_pci_set_mve_enable(uint64_t phb_id, uint32_t mve_number,
114 uint32_t state);
115int64_t opal_pci_get_xive_reissue(uint64_t phb_id, uint32_t xive_number,
116 uint8_t *p_bit, uint8_t *q_bit);
117int64_t opal_pci_set_xive_reissue(uint64_t phb_id, uint32_t xive_number,
118 uint8_t p_bit, uint8_t q_bit);
119int64_t opal_pci_msi_eoi(uint64_t phb_id, uint32_t hw_irq);
120int64_t opal_pci_set_xive_pe(uint64_t phb_id, uint32_t pe_number,
121 uint32_t xive_num);
122int64_t opal_get_xive_source(uint64_t phb_id, uint32_t xive_num,
123 __be32 *interrupt_source_number);
124int64_t opal_get_msi_32(uint64_t phb_id, uint32_t mve_number, uint32_t xive_num,
125 uint8_t msi_range, __be32 *msi_address,
126 __be32 *message_data);
127int64_t opal_get_msi_64(uint64_t phb_id, uint32_t mve_number,
128 uint32_t xive_num, uint8_t msi_range,
129 __be64 *msi_address, __be32 *message_data);
130int64_t opal_start_cpu(uint64_t thread_number, uint64_t start_address);
131int64_t opal_query_cpu_status(uint64_t thread_number, uint8_t *thread_status);
132int64_t opal_write_oppanel(oppanel_line_t *lines, uint64_t num_lines);
133int64_t opal_pci_map_pe_dma_window(uint64_t phb_id, uint16_t pe_number, uint16_t window_id,
134 uint16_t tce_levels, uint64_t tce_table_addr,
135 uint64_t tce_table_size, uint64_t tce_page_size);
136int64_t opal_pci_map_pe_dma_window_real(uint64_t phb_id, uint16_t pe_number,
137 uint16_t dma_window_number, uint64_t pci_start_addr,
138 uint64_t pci_mem_size);
139int64_t opal_pci_reset(uint64_t id, uint8_t reset_scope, uint8_t assert_state);
140
141int64_t opal_pci_get_hub_diag_data(uint64_t hub_id, void *diag_buffer,
142 uint64_t diag_buffer_len);
143int64_t opal_pci_get_phb_diag_data(uint64_t phb_id, void *diag_buffer,
144 uint64_t diag_buffer_len);
145int64_t opal_pci_get_phb_diag_data2(uint64_t phb_id, void *diag_buffer,
146 uint64_t diag_buffer_len);
147int64_t opal_pci_fence_phb(uint64_t phb_id);
148int64_t opal_pci_reinit(uint64_t phb_id, uint64_t reinit_scope, uint64_t data);
149int64_t opal_pci_mask_pe_error(uint64_t phb_id, uint16_t pe_number, uint8_t error_type, uint8_t mask_action);
150int64_t opal_set_slot_led_status(uint64_t phb_id, uint64_t slot_id, uint8_t led_type, uint8_t led_action);
151int64_t opal_get_epow_status(__be16 *epow_status, __be16 *num_epow_classes);
152int64_t opal_get_dpo_status(__be64 *dpo_timeout);
153int64_t opal_set_system_attention_led(uint8_t led_action);
154int64_t opal_pci_next_error(uint64_t phb_id, __be64 *first_frozen_pe,
155 __be16 *pci_error_type, __be16 *severity);
156int64_t opal_pci_poll(uint64_t id);
157int64_t opal_return_cpu(void);
158int64_t opal_check_token(uint64_t token);
159int64_t opal_reinit_cpus(uint64_t flags);
160
161int64_t opal_xscom_read(uint32_t gcid, uint64_t pcb_addr, __be64 *val);
162int64_t opal_xscom_write(uint32_t gcid, uint64_t pcb_addr, uint64_t val);
163
164int64_t opal_lpc_write(uint32_t chip_id, enum OpalLPCAddressType addr_type,
165 uint32_t addr, uint32_t data, uint32_t sz);
166int64_t opal_lpc_read(uint32_t chip_id, enum OpalLPCAddressType addr_type,
167 uint32_t addr, __be32 *data, uint32_t sz);
168
169int64_t opal_read_elog(uint64_t buffer, uint64_t size, uint64_t log_id);
170int64_t opal_get_elog_size(__be64 *log_id, __be64 *size, __be64 *elog_type);
171int64_t opal_write_elog(uint64_t buffer, uint64_t size, uint64_t offset);
172int64_t opal_send_ack_elog(uint64_t log_id);
173void opal_resend_pending_logs(void);
174
175int64_t opal_validate_flash(uint64_t buffer, uint32_t *size, uint32_t *result);
176int64_t opal_manage_flash(uint8_t op);
177int64_t opal_update_flash(uint64_t blk_list);
178int64_t opal_dump_init(uint8_t dump_type);
179int64_t opal_dump_info(__be32 *dump_id, __be32 *dump_size);
180int64_t opal_dump_info2(__be32 *dump_id, __be32 *dump_size, __be32 *dump_type);
181int64_t opal_dump_read(uint32_t dump_id, uint64_t buffer);
182int64_t opal_dump_ack(uint32_t dump_id);
183int64_t opal_dump_resend_notification(void);
184
185int64_t opal_get_msg(uint64_t buffer, uint64_t size);
186int64_t opal_write_oppanel_async(uint64_t token, oppanel_line_t *lines,
187 uint64_t num_lines);
188int64_t opal_check_completion(uint64_t buffer, uint64_t size, uint64_t token);
189int64_t opal_sync_host_reboot(void);
190int64_t opal_get_param(uint64_t token, uint32_t param_id, uint64_t buffer,
191 uint64_t length);
192int64_t opal_set_param(uint64_t token, uint32_t param_id, uint64_t buffer,
193 uint64_t length);
194int64_t opal_sensor_read(uint32_t sensor_hndl, int token, __be32 *sensor_data);
195int64_t opal_handle_hmi(void);
196int64_t opal_register_dump_region(uint32_t id, uint64_t start, uint64_t end);
197int64_t opal_unregister_dump_region(uint32_t id);
198int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val);
199int64_t opal_config_cpu_idle_state(uint64_t state, uint64_t flag);
200int64_t opal_pci_set_phb_cxl_mode(uint64_t phb_id, uint64_t mode, uint64_t pe_number);
201int64_t opal_ipmi_send(uint64_t interface, struct opal_ipmi_msg *msg,
202 uint64_t msg_len);
203int64_t opal_ipmi_recv(uint64_t interface, struct opal_ipmi_msg *msg,
204 uint64_t *msg_len);
205int64_t opal_i2c_request(uint64_t async_token, uint32_t bus_id,
206 struct opal_i2c_request *oreq);
207int64_t opal_prd_msg(struct opal_prd_msg *msg);
208int64_t opal_leds_get_ind(char *loc_code, __be64 *led_mask,
209 __be64 *led_value, __be64 *max_led_type);
210int64_t opal_leds_set_ind(uint64_t token, char *loc_code, const u64 led_mask,
211 const u64 led_value, __be64 *max_led_type);
212
213int64_t opal_flash_read(uint64_t id, uint64_t offset, uint64_t buf,
214 uint64_t size, uint64_t token);
215int64_t opal_flash_write(uint64_t id, uint64_t offset, uint64_t buf,
216 uint64_t size, uint64_t token);
217int64_t opal_flash_erase(uint64_t id, uint64_t offset, uint64_t size,
218 uint64_t token);
219int64_t opal_get_device_tree(uint32_t phandle, uint64_t buf, uint64_t len);
220int64_t opal_pci_get_presence_state(uint64_t id, uint64_t data);
221int64_t opal_pci_get_power_state(uint64_t id, uint64_t data);
222int64_t opal_pci_set_power_state(uint64_t async_token, uint64_t id,
223 uint64_t data);
224int64_t opal_pci_poll2(uint64_t id, uint64_t data);
225
226int64_t opal_int_get_xirr(uint32_t *out_xirr, bool just_poll);
227int64_t opal_int_set_cppr(uint8_t cppr);
228int64_t opal_int_eoi(uint32_t xirr);
229int64_t opal_int_set_mfrr(uint32_t cpu, uint8_t mfrr);
230int64_t opal_pci_tce_kill(uint64_t phb_id, uint32_t kill_type,
231 uint32_t pe_num, uint32_t tce_size,
232 uint64_t dma_addr, uint32_t npages);
233int64_t opal_nmmu_set_ptcr(uint64_t chip_id, uint64_t ptcr);
234int64_t opal_xive_reset(uint64_t version);
235int64_t opal_xive_get_irq_info(uint32_t girq,
236 __be64 *out_flags,
237 __be64 *out_eoi_page,
238 __be64 *out_trig_page,
239 __be32 *out_esb_shift,
240 __be32 *out_src_chip);
241int64_t opal_xive_get_irq_config(uint32_t girq, __be64 *out_vp,
242 uint8_t *out_prio, __be32 *out_lirq);
243int64_t opal_xive_set_irq_config(uint32_t girq, uint64_t vp, uint8_t prio,
244 uint32_t lirq);
245int64_t opal_xive_get_queue_info(uint64_t vp, uint32_t prio,
246 __be64 *out_qpage,
247 __be64 *out_qsize,
248 __be64 *out_qeoi_page,
249 __be32 *out_escalate_irq,
250 __be64 *out_qflags);
251int64_t opal_xive_set_queue_info(uint64_t vp, uint32_t prio,
252 uint64_t qpage,
253 uint64_t qsize,
254 uint64_t qflags);
255int64_t opal_xive_donate_page(uint32_t chip_id, uint64_t addr);
256int64_t opal_xive_alloc_vp_block(uint32_t alloc_order);
257int64_t opal_xive_free_vp_block(uint64_t vp);
258int64_t opal_xive_get_vp_info(uint64_t vp,
259 __be64 *out_flags,
260 __be64 *out_cam_value,
261 __be64 *out_report_cl_pair,
262 __be32 *out_chip_id);
263int64_t opal_xive_set_vp_info(uint64_t vp,
264 uint64_t flags,
265 uint64_t report_cl_pair);
266int64_t opal_xive_allocate_irq(uint32_t chip_id);
267int64_t opal_xive_free_irq(uint32_t girq);
268int64_t opal_xive_sync(uint32_t type, uint32_t id);
269int64_t opal_xive_dump(uint32_t type, uint32_t id);
270int64_t opal_pci_set_p2p(uint64_t phb_init, uint64_t phb_target,
271 uint64_t desc, uint16_t pe_number);
272
273int64_t opal_imc_counters_init(uint32_t type, uint64_t address,
274 uint64_t cpu_pir);
275int64_t opal_imc_counters_start(uint32_t type, uint64_t cpu_pir);
276int64_t opal_imc_counters_stop(uint32_t type, uint64_t cpu_pir);
277
278int opal_get_powercap(u32 handle, int token, u32 *pcap);
279int opal_set_powercap(u32 handle, int token, u32 pcap);
280int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr);
281int opal_set_power_shift_ratio(u32 handle, int token, u32 psr);
282int opal_sensor_group_clear(u32 group_hndl, int token);
283
284
285extern int early_init_dt_scan_opal(unsigned long node, const char *uname,
286 int depth, void *data);
287extern int early_init_dt_scan_recoverable_ranges(unsigned long node,
288 const char *uname, int depth, void *data);
289extern void opal_configure_cores(void);
290
291extern int opal_get_chars(uint32_t vtermno, char *buf, int count);
292extern int opal_put_chars(uint32_t vtermno, const char *buf, int total_len);
293
294extern void hvc_opal_init_early(void);
295
296extern int opal_notifier_register(struct notifier_block *nb);
297extern int opal_notifier_unregister(struct notifier_block *nb);
298
299extern int opal_message_notifier_register(enum opal_msg_type msg_type,
300 struct notifier_block *nb);
301extern int opal_message_notifier_unregister(enum opal_msg_type msg_type,
302 struct notifier_block *nb);
303extern void opal_notifier_enable(void);
304extern void opal_notifier_disable(void);
305extern void opal_notifier_update_evt(uint64_t evt_mask, uint64_t evt_val);
306
307extern int __opal_async_get_token(void);
308extern int opal_async_get_token_interruptible(void);
309extern int __opal_async_release_token(int token);
310extern int opal_async_release_token(int token);
311extern int opal_async_wait_response(uint64_t token, struct opal_msg *msg);
312extern int opal_get_sensor_data(u32 sensor_hndl, u32 *sensor_data);
313
314struct rtc_time;
315extern unsigned long opal_get_boot_time(void);
316extern void opal_nvram_init(void);
317extern void opal_flash_update_init(void);
318extern void opal_flash_term_callback(void);
319extern int opal_elog_init(void);
320extern void opal_platform_dump_init(void);
321extern void opal_sys_param_init(void);
322extern void opal_msglog_init(void);
323extern void opal_msglog_sysfs_init(void);
324extern int opal_async_comp_init(void);
325extern int opal_sensor_init(void);
326extern int opal_hmi_handler_init(void);
327extern int opal_event_init(void);
328
329extern int opal_machine_check(struct pt_regs *regs);
330extern bool opal_mce_check_early_recovery(struct pt_regs *regs);
331extern int opal_hmi_exception_early(struct pt_regs *regs);
332extern int opal_handle_hmi_exception(struct pt_regs *regs);
333
334extern void opal_shutdown(void);
335extern int opal_resync_timebase(void);
336
337extern void opal_lpc_init(void);
338
339extern void opal_kmsg_init(void);
340
341extern int opal_event_request(unsigned int opal_event_nr);
342
343struct opal_sg_list *opal_vmalloc_to_sg_list(void *vmalloc_addr,
344 unsigned long vmalloc_size);
345void opal_free_sg_list(struct opal_sg_list *sg);
346
347extern int opal_error_code(int rc);
348
349ssize_t opal_msglog_copy(char *to, loff_t pos, size_t count);
350
351static inline int opal_get_async_rc(struct opal_msg msg)
352{
353 if (msg.msg_type != OPAL_MSG_ASYNC_COMP)
354 return OPAL_PARAMETER;
355 else
356 return be64_to_cpu(msg.params[1]);
357}
358
359void opal_wake_poller(void);
360
361void opal_powercap_init(void);
362void opal_psr_init(void);
363void opal_sensor_groups_init(void);
364
365#endif
366
367#endif
368
