1#ifndef __ASM_SH_RENESAS_SDK7780_H 2#define __ASM_SH_RENESAS_SDK7780_H 3 4/* 5 * linux/include/asm-sh/sdk7780.h 6 * 7 * Renesas Solutions SH7780 SDK Support 8 * Copyright (C) 2008 Nicholas Beck <nbeck@mpc-data.co.uk> 9 * 10 * This file is subject to the terms and conditions of the GNU General Public 11 * License. See the file "COPYING" in the main directory of this archive 12 * for more details. 13 */ 14#include <linux/sh_intc.h> 15#include <asm/addrspace.h> 16 17/* Box specific addresses. */ 18#define SE_AREA0_WIDTH 4 /* Area0: 32bit */ 19#define PA_ROM 0xa0000000 /* EPROM */ 20#define PA_ROM_SIZE 0x00400000 /* EPROM size 4M byte */ 21#define PA_FROM 0xa0800000 /* Flash-ROM */ 22#define PA_FROM_SIZE 0x00400000 /* Flash-ROM size 4M byte */ 23#define PA_EXT1 0xa4000000 24#define PA_EXT1_SIZE 0x04000000 25#define PA_SDRAM 0xa8000000 /* DDR-SDRAM(Area2/3) 128MB */ 26#define PA_SDRAM_SIZE 0x08000000 27 28#define PA_EXT4 0xb0000000 29#define PA_EXT4_SIZE 0x04000000 30#define PA_EXT_USER PA_EXT4 /* User Expansion Space */ 31 32#define PA_PERIPHERAL PA_AREA5_IO 33 34/* SRAM/Reserved */ 35#define PA_RESERVED (PA_PERIPHERAL + 0) 36/* FPGA base address */ 37#define PA_FPGA (PA_PERIPHERAL + 0x01000000) 38/* SMC LAN91C111 */ 39#define PA_LAN (PA_PERIPHERAL + 0x01800000) 40 41 42#define FPGA_SRSTR (PA_FPGA + 0x000) /* System reset */ 43#define FPGA_IRQ0SR (PA_FPGA + 0x010) /* IRQ0 status */ 44#define FPGA_IRQ0MR (PA_FPGA + 0x020) /* IRQ0 mask */ 45#define FPGA_BDMR (PA_FPGA + 0x030) /* Board operating mode */ 46#define FPGA_INTT0PRTR (PA_FPGA + 0x040) /* Interrupt test mode0 port */ 47#define FPGA_INTT0SELR (PA_FPGA + 0x050) /* Int. test mode0 select */ 48#define FPGA_INTT1POLR (PA_FPGA + 0x060) /* Int. test mode0 polarity */ 49#define FPGA_NMIR (PA_FPGA + 0x070) /* NMI source */ 50#define FPGA_NMIMR (PA_FPGA + 0x080) /* NMI mask */ 51#define FPGA_IRQR (PA_FPGA + 0x090) /* IRQX source */ 52#define FPGA_IRQMR (PA_FPGA + 0x0A0) /* IRQX mask */ 53#define FPGA_SLEDR (PA_FPGA + 0x0B0) /* LED control */ 54#define PA_LED FPGA_SLEDR 55#define FPGA_MAPSWR (PA_FPGA + 0x0C0) /* Map switch */ 56#define FPGA_FPVERR (PA_FPGA + 0x0D0) /* FPGA version */ 57#define FPGA_FPDATER (PA_FPGA + 0x0E0) /* FPGA date */ 58#define FPGA_RSE (PA_FPGA + 0x100) /* Reset source */ 59#define FPGA_EASR (PA_FPGA + 0x110) /* External area select */ 60#define FPGA_SPER (PA_FPGA + 0x120) /* Serial port enable */ 61#define FPGA_IMSR (PA_FPGA + 0x130) /* Interrupt mode select */ 62#define FPGA_PCIMR (PA_FPGA + 0x140) /* PCI Mode */ 63#define FPGA_DIPSWMR (PA_FPGA + 0x150) /* DIPSW monitor */ 64#define FPGA_FPODR (PA_FPGA + 0x160) /* Output port data */ 65#define FPGA_ATAESR (PA_FPGA + 0x170) /* ATA extended bus status */ 66#define FPGA_IRQPOLR (PA_FPGA + 0x180) /* IRQx polarity */ 67 68 69#define SDK7780_NR_IRL 15 70/* IDE/ATA interrupt */ 71#define IRQ_CFCARD evt2irq(0x3c0) 72/* SMC interrupt */ 73#define IRQ_ETHERNET evt2irq(0x2c0) 74 75 76/* arch/sh/boards/renesas/sdk7780/irq.c */ 77void init_sdk7780_IRQ(void); 78 79#define __IO_PREFIX sdk7780 80#include <asm/io_generic.h> 81 82#endif /* __ASM_SH_RENESAS_SDK7780_H */ 83